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| To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER 7700 FAMILY / 7700 SERIES 7721 Group User's Manual keep safety first in your circuit designs ! q Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials q These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. q Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. q All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. q Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. q The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. q If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of JAPAN and/or the country of destination is prohibited. q Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. REVISION DESCRIPTION LIST Rev. No. 1.0 First Edition Revision Description 7721 Group User's Manual Rev. date 970926 (1/1) Preface This manual describes the hardware of the Mitsubishi CMOS 16-bit microcomputers 7721 Group. After reading this manual, the user will be able to understand the functions, so that their capabilities can fully be utilized. BEFORE USING THIS MANUAL 1. Constitution This user's manual consists of the following chapters. Refer to the chapters relevant to the products. q Chapter 1. DESCRIPTION through Chapter 16. APPLICATION Functions which are common to the M37721S1BFP and the M37721S2BFP are explained, using the M37721S2BFP as an example. Differences between the M37721S1BFP and the M37721S2BFP are described as notes. q Appendix Practical information for using the 7721 Group is described. 2. Remark q Product expansion Refer to the latest catalog and data book, or contact the appropriate office, as listed in "CONTACT ADDRESSES FOR FURTHER INFORMATION" on the last page. q Electrical characteristics Refer to the latest data book. q Software Refer to "7700 Family Software Manual." q Development support tools Refer to the latest data book of the development support tools. 3. Signal levels in Figure As a rule, signal levels in each operation example and timing diagram are as follows. * Signal levels The upper line indicates "1," and the lower line indicates "0." * Input/output levels of pin The upper line indicates "H," and the lower line indicates "L." For the exception, the level is shown on the left side of a signal. 1 4. Register structure Below is the structure diagram for all registers: V1 b7 b6 b5 b4 b3 b2 b1 b0 !0 XXX register (Address XX16) V2 Functions 0 : ... 1 : ... 0 : ... 1 : ... The value is "0" at reading. 0 : ... 1 : ... At reset V3 RW RW WO Bit 0 1 Bit name ... select bit ... select bit 0 Undefined 2 3 4 ... flag Fix this bit to "0." This bit is invalid in ... mode. 0 0 0 Undefined RO RW RW - 7 to 5 Nothing is assigned. V1 Blank 0 1 ! V2 0 1 Undefined V3 RW RO WO : "0" immediately after reset. : "1" immediately after reset. : Undefined immediately after reset. : Set to "0" or "1" according to the usage. : Set to "0" at writing. : Set to "1" at writing. : Invalid depending on the mode or state. It may be "0" or "1." : Nothing is assigned. V4 -- : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. Accordingly, the written value may be "0" or "1." : The written value becomes valid. It is impossible to read the bit state. The value is undefined at reading. However, when ["0" at reading"] is indicated in the "Function" or "Note" column, the bit is always "0" at reading. (See V4 above.) : It is impossible to read the bit state. The value is undefined at reading. However, when ["0" at reading"] is indicated in the "Function" or "Note" column, the bit is always "0" at reading. (See V4 above.) The written value becomes invalid. Accordingly, the written value may be "0" or "1." 2 Table of contents Table of contents CHAPTER 1 DESCRIPTION 1.1 1.2 1.3 1.4 Performance overview.......................................................................................................... Pin configuration................................................................................................................... Pin description ...................................................................................................................... Block diagram ........................................................................................................................ 1-2 1-3 1-4 1-7 CHAPTER 2 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit ....................................................................................................... 2-2 2.1.1 Accumulator (Acc) ......................................................................................................... 2-3 2.1.2 Index register X (X) ....................................................................................................... 2-3 2.1.3 Index register Y (Y) ....................................................................................................... 2-3 2.1.4 Stack pointer (S) ............................................................................................................ 2-4 2.1.5 Program counter (PC) ................................................................................................... 2-5 2.1.6 Program bank register (PG) ......................................................................................... 2-5 2.1.7 Data bank register (DT) ................................................................................................ 2-5 2.1.8 Direct page register (DPR) ........................................................................................... 2-6 2.1.9 Processor status register (PS) ..................................................................................... 2-7 2.2 Bus interface unit ................................................................................................................. 2-9 2.2.1 Overview ......................................................................................................................... 2-9 2.2.2 Functions of bus interface unit (BIU) ........................................................................ 2-11 2.2.3 Operation of bus interface unit (BIU)........................................................................ 2-13 2.3 Access space ....................................................................................................................... 2-15 2.3.1 Banks ............................................................................................................................ 2-16 2.3.2 Direct page ................................................................................................................... 2-16 2.4 Memory assignment ........................................................................................................... 2-17 2.4.1 Memory assignment in internal area ......................................................................... 2-17 2.4.2 External area ................................................................................................................ 2-18 2.5 Bus access right ................................................................................................................. 2-23 CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES 3.1 Signals required for accessing external devices .......................................................... 3-2 3.1.1 Descriptions of signals .................................................................................................. 3-2 3.1.2 Operation of bus interface unit (BIU).......................................................................... 3-5 3.2 Software Wait ......................................................................................................................... 3-8 3.3 Ready function .................................................................................................................... 3-10 3.3.1 Operation description .................................................................................................. 3-11 3.4 Hold function ....................................................................................................................... 3-12 3.4.1 Operation description .................................................................................................. 3-12 [Precautions for Hold function] ............................................................................................ 3-16 7721 Group User's Manual i Table of contents CHAPTER 4 RESET 4.1 Hardware reset ...................................................................................................................... 4-2 4.1.1 Pin state .......................................................................................................................... 4-3 4.1.2 State of CPU, SFR area, and internal RAM area..................................................... 4-4 4.1.3 Internal processing sequence after reset ................................................................. 4-11 ______ 4.1.4 Time supplying "L" level to RESET pin .................................................................... 4-12 4.2 Software reset ...................................................................................................................... 4-13 CHAPTER 5 CLOCK GENERATING CIRCUIT 5.1 Oscillation circuit examples ............................................................................................... 5-2 5.1.1 Connection example using resonator/oscillator .......................................................... 5-2 5.1.2 Externally generated clock input example .................................................................. 5-2 5.2 Clocks .......................................................................................................................................5-3 5.2.1 Clocks generated in clock generating circuit ............................................................. 5-4 5.3 Stop mode .............................................................................................................................. 5-5 5.3.1 Stop mode ...................................................................................................................... 5-5 [Precautions for Stop mode] .................................................................................................. 5-8 5.4 Wait mode ............................................................................................................................... 5-9 5.4.1 Wait mode ...................................................................................................................... 5-9 [Precautions for Wait mode] ................................................................................................. 5-11 CHAPTER 6 INPUT/OUTPUT PINS 6.1 Overview ..................................................................................................................................6-2 6.2 Programmable I/O ports ...................................................................................................... 6-2 6.2.1 Direction register ............................................................................................................ 6-3 6.2.2 Port register .................................................................................................................... 6-4 6.3 Examples of handling unused pins .................................................................................. 6-7 CHAPTER 7 INTERRUPTS 7.1 Overview ..................................................................................................................................7-2 7.2 Interrupt sources ................................................................................................................... 7-4 7.3 Interrupt control .................................................................................................................... 7-5 7.3.1 Interrupt disable flag (I) ................................................................................................ 7-7 7.3.2 Interrupt request bit ....................................................................................................... 7-7 7.3.3 Interrupt priority level select bits and processor interrupt priority level (IPL) ....... 7-7 7.4 Interrupt priority level .......................................................................................................... 7-9 7.5 Interrupt priority level detection circuit ........................................................................ 7-10 7.6 Interrupt priority level detection time ............................................................................ 7-12 7.7 Sequence from acceptance of interrupt request until execution of interrupt routine .................................................................................................................................... 7-13 7.7.1 Change in IPL at acceptance of interrupt request .................................................. 7-14 7.7.2 Push operation for registers ....................................................................................... 7-15 7.8 Return from interrupt routine........................................................................................... 7-16 7.9 Multiple interrupts ............................................................................................................... 7-16 ____ 7.10 External interrupts (INTi interrupt) ............................................................................... 7-18 ____ 7.10.1 Functions of ____ interrupt request bit .................................................................... 7-20 INTi 7.10.2 Switching of INTi interrupt request occurrence factor .......................................... 7-21 7.11 Precautions for interrupts ............................................................................................... 7-22 ii 7721 Group User's Manual Table of contents CHAPTER 8 TIMER A 8.1 Overview ..................................................................................................................................8-2 8.2 Block description .................................................................................................................. 8-3 8.2.1 Counter and reload register (timer Ai register) ......................................................... 8-4 8.2.2 Count start register........................................................................................................ 8-5 8.2.3 Timer Ai mode register ................................................................................................. 8-6 8.2.4 Timer Ai interrupt control register ............................................................................... 8-7 8.2.5 Port P5 direction register ............................................................................................. 8-8 8.3 Timer mode ............................................................................................................................ 8-9 8.3.1 Setting for timer mode ................................................................................................ 8-11 8.3.2 Count source ................................................................................................................ 8-13 8.3.3 Operation in timer mode ............................................................................................. 8-14 8.3.4 Selectable functions .................................................................................................... 8-15 [Precautions for timer mode] ................................................................................................ 8-17 8.4 Event counter mode ........................................................................................................... 8-18 8.4.1 Setting for event counter mode ................................................................................. 8-21 8.4.2 Operation in event counter mode .............................................................................. 8-23 8.4.3 Switching between countup and countdown ............................................................ 8-24 8.4.4 Selectable functions .................................................................................................... 8-25 [Precautions for event counter mode] ................................................................................. 8-28 8.5 One-shot pulse mode ......................................................................................................... 8-29 8.5.1 Setting for one-shot pulse mode ............................................................................... 8-31 8.5.2 Count source ................................................................................................................ 8-33 8.5.3 Trigger ........................................................................................................................... 8-34 8.5.4 Operation in one-shot pulse mode ............................................................................ 8-35 [Precautions for one-shot pulse mode] ............................................................................... 8-37 8.6 Pulse width modulation (PWM) mode ............................................................................ 8-38 8.6.1 Setting for PWM mode ............................................................................................... 8-40 8.6.2 Count source ................................................................................................................ 8-42 8.6.3 Trigger ........................................................................................................................... 8-42 8.6.4 Operation in PWM mode ............................................................................................ 8-43 [Precautions for PWM mode] ............................................................................................... 8-47 CHAPTER 9 TIMER B 9.1 Overview ..................................................................................................................................9-2 9.2 Block description .................................................................................................................. 9-2 9.2.1 Counter and reload register (timer Bi register) ......................................................... 9-3 9.2.2 Count start register........................................................................................................ 9-4 9.2.3 Timer Bi mode register ................................................................................................. 9-5 9.2.4 Timer Bi interrupt control register ............................................................................... 9-6 9.2.5 Port P5 direction register ............................................................................................. 9-7 9.3 Timer mode ............................................................................................................................ 9-8 9.3.1 Setting for timer mode ................................................................................................ 9-10 9.3.2 Count source ................................................................................................................ 9-11 9.3.3 Operation in timer mode ............................................................................................. 9-12 [Precautions for timer mode] ................................................................................................ 9-13 9.4 Event counter mode ........................................................................................................... 9-14 9.4.1 Setting for event counter mode ................................................................................. 9-16 9.4.2 Operation in event counter mode .............................................................................. 9-17 [Precautions for event coutner mode] ................................................................................. 9-18 7721 Group User's Manual iii Table of contents 9.5 Pulse period/Pulse width measurement mode ............................................................. 9-19 9.5.1 Setting for pulse period/pulse width measurement mode ...................................... 9-21 9.5.2 Count source ................................................................................................................ 9-22 9.5.3 Operation in pulse period/pulse width measurement mode ................................... 9-23 [Precautions for pulse period/pulse width measurement mode] ...................................... 9-25 CHAPTER 10 REAL-TIME OUTPUT 10.1 Overview ............................................................................................................................. 10-2 10.2 Block description .............................................................................................................. 10-4 10.2.1 Real-time output control register ............................................................................. 10-4 10.2.2 Pulse output data registers 0 and 1 ....................................................................... 10-5 10.2.3 Port P6 direction register ......................................................................................... 10-6 10.2.4 Timers A0 and A1 ..................................................................................................... 10-6 10.3 Setting of real-time output ............................................................................................. 10-7 10.4 Real-time output operation ........................................................................................... 10-10 CHAPTER 11 SERIAL I/O 11.1 Overview ............................................................................................................................. 11-2 11.2 Block description .............................................................................................................. 11-3 11.2.1 UARTi transmit/receive mode register .................................................................... 11-4 11.2.2 UARTi transmit/receive control register 0 .............................................................. 11-6 11.2.3 UARTi transmit/receive control register 1 .............................................................. 11-7 11.2.4 UARTi transmit register and UARTi transmit buffer register ............................... 11-9 11.2.5 UARTi receive register and UARTi receive buffer register ................................ 11-11 11.2.6 UARTi baud rate register (BRGi) .......................................................................... 11-13 11.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers ......................... 11-14 11.2.8 Port P8 direction register ....................................................................................... 11-15 11.3 Clock synchronous serial I/O mode ........................................................................... 11-16 11.3.1 Transfer clock (Synchronizing clock) .................................................................... 11-17 11.3.2 Method of transmission ........................................................................................... 11-18 11.3.3 Transmit operation ................................................................................................... 11-21 11.3.4 Method of reception ................................................................................................ 11-23 11.3.5 Receive operation .................................................................................................... 11-27 11.3.6 Processing on detecting overrun error ................................................................. 11-29 [Precautions for clock synchronous serial I/O mode] ..................................................... 11-30 11.4 Clock asynchronous serial I/O (UART) mode .......................................................... 11-31 11.4.1 Transfer rate (Frequency of transfer clock) ......................................................... 11-32 11.4.2 Transfer data format ............................................................................................... 11-33 11.4.3 Method of transmission ........................................................................................... 11-34 11.4.4 Transmit operation ................................................................................................... 11-38 11.4.5 Method of reception ................................................................................................ 11-41 11.4.6 Receive operation .................................................................................................... 11-44 11.4.7 Processing on detecting error ................................................................................ 11-46 11.4.8 Sleep mode .............................................................................................................. 11-47 iv 7721 Group User's Manual Table of contents CHAPTER 12 A-D CONVERTER 12.1 Overview ............................................................................................................................. 12-2 12.2 Block description .............................................................................................................. 12-3 12.2.1 A-D control register ................................................................................................... 12-4 12.2.2 A-D sweep pin select register ................................................................................. 12-6 12.2.3 A-D register i (i = 0 to 7) ......................................................................................... 12-7 12.2.4 A-D conversion interrupt control register ................................................................ 12-8 12.2.5 Port P7 direction register ......................................................................................... 12-9 12.3 A-D conversion method ................................................................................................. 12-10 12.4 Absolute accuracy and differential non-linearity error .......................................... 12-12 12.4.1 Absolute accuracy ................................................................................................... 12-12 12.4.2 Differential non-linearity error................................................................................. 12-13 12.5 One-shot mode ................................................................................................................ 12-14 12.5.1 Settings for one-shot mode .................................................................................... 12-14 12.5.2 One-shot mode operation description ................................................................... 12-16 12.6 Repeat mode .................................................................................................................... 12-17 12.6.1 Settings for repeat mode ........................................................................................ 12-17 12.6.2 Repeat mode operation description ...................................................................... 12-19 12.7 Single sweep mode ........................................................................................................ 12-20 12.7.1 Settings for single sweep mode ............................................................................ 12-20 12.7.2 Single sweep mode operation description ............................................................ 12-22 12.8 Repeat sweep mode ....................................................................................................... 12-24 12.8.1 Settings for repeat sweep mode ........................................................................... 12-24 12.8.2 Repeat sweep mode operation description .......................................................... 12-26 12.9 Precautions for A-D converter ..................................................................................... 12-28 CHAPTER 13 DMA CONTROLLER 13.1 Overview ............................................................................................................................. 13-2 13.1.1 Performance overview ............................................................................................... 13-2 13.1.2 Bus use priority levels .............................................................................................. 13-3 13.1.3 Modes .......................................................................................................................... 13-3 13.2 Block description .............................................................................................................. 13-6 13.2.1 Bus access control circuit ........................................................................................ 13-7 13.2.2 DMAC control register L ......................................................................................... 13-10 13.2.3 DMAC control register H ........................................................................................ 13-11 13.2.4 Source address register i (SARi) .......................................................................... 13-12 13.2.5 Destination address register i (DARi) ................................................................... 13-12 13.2.6 Transfer counter register i (TCRi) ......................................................................... 13-12 13.2.7 Incrementer/Decrementer ........................................................................................ 13-13 13.2.8 Decrementer ............................................................................................................. 13-13 13.2.9 DMA latch ................................................................................................................. 13-13 13.2.10 DMAi mode register L ........................................................................................... 13-14 13.2.11 DMAi mode register H .......................................................................................... 13-15 13.2.12 DMAi control register ............................................................................................ 13-16 13.2.13 DMAi interrupt control register ............................................................................. 13-17 13.2.14 Port P9 direction register ..................................................................................... 13-18 [Precautions for DMAC] ...................................................................................................... 13-18 7721 Group User's Manual v Table of contents 13.3 Control ............................................................................................................................... 13-19 13.3.1 DMA enabling ........................................................................................................... 13-19 13.3.2 DMA requests .......................................................................................................... 13-20 13.3.3 Channel priority levels ............................................................................................ 13-21 13.3.4 Processing from DMA request until DMA transfer execution ............................ 13-23 13.3.5 Termination of DMA transfer .................................................................................. 13-25 13.3.6 DMA transfer restart after termination .................................................................. 13-28 13.4 Operation .......................................................................................................................... 13-30 13.4.1 2-bus cycle transfer ................................................................................................. 13-30 [Precautions for 2-bus cycle transfer] ............................................................................... 13-37 13.4.2 1-bus cycle transfer ................................................................................................. 13-38 [Precautions for 1-bus cycle transfer] ............................................................................... 13-47 13.4.3 Burst transfer mode................................................................................................. 13-48 [Precautions for burst transfer mode] ............................................................................... 13-50 13.4.4 Cycle-steal transfer mode ....................................................................................... 13-51 [Precautions for cycle-steal transfer mode] ...................................................................... 13-52 13.5 Single transfer mode...................................................................................................... 13-54 13.5.1 Setting of single transfer mode ............................................................................. 13-56 13.5.2 Operation in single transfer mode ......................................................................... 13-59 13.6 Repeat transfer mode .................................................................................................... 13-61 13.6.1 Setting of repeat transfer mode ............................................................................ 13-63 13.6.2 Operation in repeat transfer mode ........................................................................ 13-66 13.7 Array chain transfer mode ............................................................................................ 13-68 13.7.1 Transfer parameter memory in array chain transfer mode ................................ 13-70 13.7.2 Setting of array chain transfer mode .................................................................... 13-72 13.7.3 Operation in array chain transfer mode ............................................................... 13-75 [Precautions for array chain transfer mode] .................................................................... 13-79 13.8 Link array chain transfer mode ................................................................................... 13-80 13.8.1 Transfer parameter memory in link array chain transfer mode ......................... 13-82 13.8.2 Setting of link array chain transfer mode ............................................................. 13-84 13.8.3 Operation in link array chain transfer mode ........................................................ 13-87 [Precautions for link array chain transfer mode] ............................................................. 13-97 13.9 DMA transfer time ........................................................................................................... 13-98 13.9.1 Cycle-steal transfer mode ....................................................................................... 13-98 13.9.2 Burst transfer mode............................................................................................... 13-101 CHAPTER 14 DRAM CONTROLLER 14.1 Overview ............................................................................................................................. 14-2 14.2 Block description .............................................................................................................. 14-2 14.2.1 DRAM control register ............................................................................................... 14-3 14.2.2 Refresh timer .............................................................................................................. 14-5 14.2.3 ____ Address comparator .................................................................................................. 14-6 ____ 14.2.4 RAS and CAS generating circuit ............................................................................. 14-6 14.2.5 Address multiplexer ................................................................................................... 14-6 14.3 Setting for DRAMC ........................................................................................................... 14-7 14.4 DRAMC operation ............................................................................................................. 14-8 14.4.1 Waveform example of DRAM control signals ........................................................ 14-8 14.4.2 Refresh request ....................................................................................................... 14-10 14.5 Precautions for DRAMC ................................................................................................ 14-12 vi 7721 Group User's Manual Table of contents CHAPTER 15 WATCHDOG TIMER 15.1 Block description .............................................................................................................. 15-2 15.1.1 Watchdog timer .......................................................................................................... 15-3 15.1.2 Watchdog timer frequency select register .............................................................. 15-3 15.2 Operation description ...................................................................................................... 15-4 15.2.1 Basic operation .......................................................................................................... 15-4 15.2.2 Stop period ................................................................................................................. 15-6 15.2.3 Operation in Stop mode ........................................................................................... 15-6 15.3 Precautions for Watchdog timer ................................................................................... 15-7 CHAPTER 16 APPLICATION 16.1 Memory connection .......................................................................................................... 16-2 16.1.1 Memory connection model ........................................................................................ 16-2 16.1.2 How to calculate timing ............................................................................................ 16-4 16.1.3 Example of memory connection ............................................................................ 16-20 16.1.4 Example of I/O expansion ...................................................................................... 16-40 16.2 Examples of using DMA controller ............................................................................. 16-43 16.2.1 Example of Centronics interface configuration .................................................... 16-43 16.2.2 Example of stepping motor control ....................................................................... 16-48 16.2.3 Example of dynamic lighting for LED ................................................................... 16-53 16.3 Comparison of sample program execution rate ...................................................... 16-56 16.3.1 Differences depending on data bus width and software Wait ........................... 16-56 16.3.2 Comparison between software Wait (f(XIN) = 20 MHz) and software Wait + Ready (f(XIN) = 25 MHz) .... 16-58 APPENDIX Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix 1. Memory assignment of 7721 Group ............................................................... 17-2 2. Memory assignment in SFR area ................................................................... 17-3 3. Control registers ................................................................................................. 17-9 4. Package outline ................................................................................................ 17-40 5. Examples of handling unused pins ............................................................. 17-41 6. Machine instructions ....................................................................................... 17-42 7. Hexadecimal instruction code table ............................................................. 17-56 8. Countermeasure against noise ...................................................................... 17-59 9. 7721 Group Q & A ........................................................................................... 17-65 10. Differences between 7721 Group and 7720 Group ................................. 17-79 11. Electrical characteristics .............................................................................. 17-80 12. Standard characteristics ............................................................................. 17-107 GLOSSARY 7721 Group User's Manual vii Table of contents MEMORANDUM viii 7721 Group User's Manual CHAPTER 1 DESCRIPTION 1.1 1.2 1.3 1.4 Performance overview Pin configuration Pin description Block diagram DESCRIPTION 1.1 Performance overview 1.1 Performance overview Table 1.1.1 lists the performance overview of the M37721. Table 1.1.1 M37721 performance overview Parameters Number of basic instructions Instruction execution time External clock input frequency f(XIN) ROM Memory sizes RAM Programmable Input/Output ports Multifunctional timers Serial I/O A-D converter Watchdog timer DMA controller P5-P10 P4 TA0-TA4 TB0-TB2 UART0, UART1 M37721S2BFP M37721S1BFP Functions 103 160 ns (the minimum instruction at f(XIN) = 25 MHz) 25 MHz (maximum) External 1024 bytes 512 bytes 8 bits ! 6 5 bits ! 1 16 bits ! 5 16 bits ! 3 (UART or clock synchronous serial I/O) ! 2 8-bit successive approximation method ! 1 (8 channels) 12 bits ! 1 4 channels Maximum transfer rate : 12.5 Mbytes/sec. (at f(XIN) = 25 MHz, 1-bus cycle transfer) Maximum transfer rate : 6.25 Mbytes/sec. ____ (at f(XIN) = 25 MHz, 2-bus cycle transfer) ____ CAS before RAS refreshing method 4 bits ! 2 channels or 6 bits ! 1 channel + 2 bits ! 1 channel 3 external, 20 internal (priority levels 0 to 7 can be set for each interrupt with software) Built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) 5 V 10 % 135 mW (at f(XIN) = 25 MHz, typ.) DRAM controller Real-time output Interrupts Clock generating circuit Supply voltage Power dissipation Port Input/Output characteristics Memory expansion Operating temperature range Device structure Package Input/Output withstand voltage 5 V 5 mA Output current Maximum 16 Mbytes -20C to 85C CMOS high-performance silicon gate process 100-pin plastic molded QFP 1-2 7721 Group User's Manual DESCRIPTION 1.2 Pin configuration 1.2 Pin configuration Figure 1.2.1 shows the M37721S2BFP pin configuration. 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P86/RXD1 P85/CLK1 P84/CTS1/RTS1 P83/TXD0 P82/RXD0 P81/CLK0 P80/CTS0/RTS0 VCC AVCC VREF AVSS VSS P77/AN7/ADTRG P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 P57/TB1IN P56/TB0IN P55/TA4IN P54/TA4OUT P53/TA3IN P52/TA3OUT P51/TA2IN P50/TA2OUT P107/MA9 P106/MA8 P105/RAS P104/CAS P103/TC P102/INT2 P101/INT1 P100/INT0 P47 P46 P45 P44 P43 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P87/TXD1 P90/DMAACK0 P91/DMAREQ0 P92/DMAACK1 P93/DMAREQ1 P94/DMAACK2 P95/DMAREQ2 P96/DMAACK3 P97/DMAREQ3 A0/MA0 A1/MA1 A2/MA2 A3/MA3 A4/MA4 A5/MA5 A6/MA6 A7/MA7 A8/D8 A9/D9 A10/D10 A11/D11 A12/D12 A13/D13 A14/D14 A15/D15 A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Outline 100P6S-A Fig. 1.2.1 M37721S2BFP pin configuration (top view) 7721 Group User's Manual M37721S2BFP A21/D5 A22/D6 A23/D7 R/W BHE BLE ALE ST0 ST1 VCC VSS E XOUT XIN RESET RESETOUT CNVSS BYTE HOLD RDY 1-3 DESCRIPTION 1.3 Pin description 1.3 Pin description Tables 1.3.1 to 1.3.3 list the pin description. Table 1.3.1 Pin description (1) Pin Vcc, Vss CNVss ______ Name Power supply CNVss Reset input Reset output Input/Output Input Input Output Functions Supply 5 V 10 % to Vcc pin and 0 V to Vss pin. Connect to Vss or Vcc pin. The microcomputer is reset when supplying "L" level to this pin. ______ When input to RESET pin is "L," this pin outputs "L." Output from this pin returns "H" after the release of reset. When writing "1" to the software reset bit, this pin outputs "L." These are I/O pins of the internal clock generating circuit. Connect a ceramic resonator or quartz-crystal oscillator between pins XIN and XOUT. When using an external clock, the clock source should be input to XIN pin and XOUT pin should be left open. RESET ________ RESETOUT XIN Clock input Input XOUT _ Clock output Output E BYTE Enable output Output Data/instruction code read or data write is performed when output from this pin is "L" level. Input level to this pin determines whether the external data bus has a 16-bit width or an 8-bit width. The width is 16 bits when the level is "L", and 8 bits when the level is "H". The bus use state is output in 2-bit code. ST1 ST0 Bus use state 0 0 DRAM refresh 0 1 1 1 0 1 Hold DMA CPU Exernal data bus width Input selection input ST0 ST1 Status signal output Output AVcc AVss VREF Analog supply input Reference voltage input Input The power supply pin for the A-D converter. Connect AVcc to Vcc pin. Connect AVss to Vss pin. This is a reference voltage input pin for the A-D converter. 1-4 7721 Group User's Manual DESCRIPTION 1.3 Pin description Table 1.3.2 Pin description (2) Pin A0/MA0- A7/MA7 A8/D8- A15/D15 Name Input/Output Address low-order/ Output DRAM address Address middle-order/ data high-order I/O Functions Low-order 8 bits (A0-A7) of the address are output. When the DRAM is accessed, the row and column addresses are output with the time-sharing. qExternal data bus width = 8 bits (When the BYTE pin is "H" level) Middle-order 8 bits (A8-A15) of the address are output. qExternal data bus width = 16 bits (When the BYTE pin is "L" level) Data (D8-D15) input/output and output of the middleorder 8 bits (A8-A15) of the address are performed with the time-sharing. A16/D0- A23/D7 __ Address high-order/ data low-order I/O Data (D0-D7) input/output and output of the high-order 8 bits (A16-A23) of the address are performed with the time-sharing. __ qR/W The Read/Write signal indicates the data bus state. The state is read while this signal is "H" level, and write while this signal is "L" level. ____ qBHE "L" level is output when an odd-numbered address is accessed. ____ R/W, ____ ____ BHE, BLE, ALE Memory control signal Output output qBLE "L" level is output when an even-numbered address is accessed. qALE This is used to obtain only the address from address and data multiplex signals. _____ HOLD ____ Hold input Ready input Clock 1 output Input Input Output The microcomputer is in Hold state while "L" level is _____ input to the HOLD pin. The microcomputer is in Ready state while "L" level is ____ input to the RDY pin. This is the 1 output pin. RDY 1 7721 Group User's Manual 1-5 DESCRIPTION 1.3 Pin description Table 1.3.3 Pin description (3) Pin P43-P47 Name I/O port P4 Input/Output I/O Functions Port P4 is a 5-bit CMOS I/O port. This port has an I/O direction register and each pin can be programmed for input or output. Port P5 is an 8-bit I/O port with the same function as P4. These pins can be programmed as I/O pins for Timers A2-A4 and I/O pins for Timers B0, B1. Port P6 is an 8-bit I/O port with the same function as P4. These pins can be programmed as output pins for the real-time output. Port P7 is an 8-bit I/O port with the same function as P4. These pins can be programmed as input pins for A-D converter. Port P8 is an 8-bit I/O port with the same function as P4. These pins can be programmed as I/O pins for Serial I/O. Port P9 is an 8-bit I/O port with the same function as P4. These pins can be programmed as I/O pins for DMA controller. Port P10 is an 8-bit I/O port with the same function __ as P4. These pins can be programmed as I/O pin for TC and output pins for DRAM controller. ___ ___ P50-P57 I/O port P5 I/O P60-P67 I/O port P6 I/O P70-P77 I/O port P7 I/O P80-P87 I/O port P8 I/O P90-P97 I/O port P9 I/O P100- P107 I/O port P10 I/O P100-P102 also function as input pins for INT0-INT2. 1-6 7721 Group User's Manual Clock input Clock output XIN XOUT VCC HOLD BLE ALE R/W BHE (0V) VSS CNVss (0V) AVSS Clock 1 output Enable output E Reset output RESETOUT Status signal output ST0 ST1 Reset input RESET Memory control signal output 1 Reference External data bus width voltage input selection input VREF AVCC BYTE RDY Clock Generating Circuit 1.4 Block diagram Fig. 1.4.1 M37721 block diagram Instruction Register (8) Figure 1.4.1 shows the M37721 block diagram. Program Counter PC (16) Data Bank Register DT (8) Incrementer/Decrementer (24) Program Bank Register PG (8) Instruction Queue Buffer Q0 (8) Instruction Queue Buffer Q1 (8) Instruction Queue Buffer Q2 (8) Data Address Register DA (24) Input Buffer Register IB (16) Program Address Register PA (24) Processor Status Register PS (11) Direct Page Register DPR (16) Arithmetic Logic Unit (16) Incrementer (24) Stack Pointer S (16) Index Register X (16) Index Register Y (16) Accumulator A (16) Accumulator B (16) Data Buffer DBH (8) Data Buffer DBL (8) Note: For the M37721S1BFP, the RAM size is 512 bytes. Timer TA4 (16) Timer TA3 (16) Timer TA2 (16) Timer TA1 (16) UART1 (9) UART0 (9) A-D Converter (8) DRAM Controller Timer TA0 (16) Timer TB0 (16) Timer TB1 (16) Timer TB2 (16) Watchdog Timer 7721 Group User's Manual Central Processing Unit (CPU) Bus Interface Unit (BIU) DMA3 (16) DMA2 (16) DMA1 (16) DMA0 (16) Data Bus (Even) Data Bus (Odd) Address Bus ROM 1024 Bytes P10 (8) P9 (8) P8 (8) P7 (8) P6 (8) P5 (8) P4 (5) Address/Data (16) Address (8) Input/Output port P10 Input/Output port P9 Input/Output port P8 Input/Output port P7 Input/Output port P6 Input/Output port P5 Input/Output port P4 Address/Data DESCRIPTION 1.4 Block diagram 1-7 DESCRIPTION 1.4 Block diagram MEMORANDUM 1-8 7721 Group User's Manual CHAPTER 2 CENTRAL PROCESSING UNIT (CPU) 2.1 2.2 2.3 2.4 2.5 Central processing unit Bus interface unit Access space Memory assignment Bus access right CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1 Central processing unit The CPU (Central Processing Unit) has the ten registers as shown in Figure 2.1.1. b15 b8 b7 b0 AH b15 b8 b7 AL b0 Accumulator A (A) BH b15 b8 b7 BL b0 Accumulator B (B) XH b15 b8 b7 XL b0 Index register X (X) YH b15 b8 b7 YL b0 Index register Y (Y) SH b7 b0 SL Stack pointer (S) DT b23 b16 b15 b8 b7 b0 Data bank register (DT) PG b7 b0 PCH PCL Program counter (PC) Program bank register (PG) b15 b8 b7 b0 DPRH b15 b8 b7 DPRL b0 Direct page register (DPR) PSH PSL Processor status register (PS) b15 b10 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 IPL NV m x D I Z C Carry flag Zero flag Interrupt disable flag Decimal mode flag Index register length flag Data length flag Overflow flag Negative flag Processor interrupt priority level Fig. 2.1.1 CPU registers structure 2-2 7721 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1.1 Accumulator (Acc) Accumulators A and B are available. (1) Accumulator A (A) Accumulator A is the main register of the microcomputer. The transaction of data such as calculation, data transfer, and input/output are performed mainly through accumulator A. It consists of 16 bits, and the low-order 8 bits can also be used separately. The data length flag (m) determines whether the register is used as a 16-bit register or as an 8-bit register. When an 8-bit register is selected, only the low-order 8 bits of accumulator A are used and the contents of the high-order 8 bits is unchanged. (2) Accumulator B (B) Accumulator B is a 16-bit register with the same function as accumulator A. Accumulator B can be used instead of accumulator A. The use of accumulator B, however except for some instructions, requires more instruction bytes and execution cycles than that of accumulator A. Accumulator B is also controlled by the data length flag (m) just as in accumulator A. 2.1.2 Index register X (X) Index register X consists of 16 bits and the low-order 8 bits can also be used separately. The index register length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. When an 8-bit register is selected, only the low-order 8 bits of index register X are used and the contents of the high-order 8 bits is unchanged. In an addressing mode in which index register X is used as an index register, the address obtained by adding the contents of this register to the operand's contents is accessed. In the MVP or MVN instruction, a block transfer instruction, the contents of index register X indicate the low-order 16 bits of the source address. The third byte of the instruction is the high-order 8 bits of the source address. Note: Refer to "7700 Family Software Manual" for addressing modes. 2.1.3 Index register Y (Y) Index register Y is a 16-bit register with the same function as index register X. Just as in index register X, the index register length flag (x) determines whether this register is used as a 16-bit register or as an 8-bit register. In the MVP or MVN instruction, a block transfer instruction, the contents of index register Y indicate the low-order 16 bits of the destination address. The second byte of the instruction is the high-order 8 bits of the destination address. 7721 Group User's Manual 2-3 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1.4 Stack pointer (S) The stack pointer (S) is a 16-bit register. It is used for a subroutine call or an interrupt. It is also used when addressing modes using the stack are executed. The contents of S indicate an address (stack area) for storing registers during subroutine calls and interrupts. Stack area is selected by the stack bank select bit described later (bit 7 at address 5E16). The stack area is specified to bank 016 when the stack bank select bit is "0," and the stack area is specified to bank FF16 when it is "1." When an interrupt request is accepted, the microcomputer stores the contents of the program bank register (PG) at the address indicated by the contents of S and decrements the contents of S by 1. Then the contents of the program counter (PC) and the processor status register (PS) are stored. The contents of S after accepting an interrupt request is equal to the contents of S decremented by 5 before the accepting of the interrupt request. (Refer to "Figure 2.1.2.") When completing the process in the interrupt routine and returning to the original routine, the contents of registers stored in the stack area are restored into the original registers in the reverse sequence (PSPCPG) by executing the RTI instruction. The contents of S is returned to the state before accepting an interrupt request. The same operation is performed during a subroutine call, however, the contents of PS is not automatically stored. (The contents of PG may not be stored. This depends on the addressing mode.) The user should store registers other than those described above with software when the user needs them during interrupts or subroutine calls. Additionally, initialize S at the beginning of the program because its contents are undefined at reset. The stack area changes when subroutines are nested or when multiple interrupt requests are accepted. Therefore, make sure of the subroutine's nesting depth not to destroy the necessary data. Note: Refer to "7700 Family Software Manual" for addressing modes. Stack area Address S-5 S-4 Processor status register's low-order byte (PSL) S-3 Processor status register's high-order byte (PSH) S-2 S-1 S Program counter's low-order byte (PCL) Program counter's high-order byte (PCH) Program bank register (PG) q "S" is the initial address that the stack pointer (S) indicates at accepting an interrupt request. The S's contents become "S-5" after storing the above registers. Fig. 2.1.2 Stored registers of the stack area 2-4 7721 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1.5 Program counter (PC) The program counter is a 16-bit counter that indicates the low-order 16 bits of the address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from an instruction queue buffer next) is stored. The contents of the high-order program counter (PCH) become "FF16," and the low-order program counter (PCL) becomes "FE16" at reset. The contents of the program counter becomes the contents of the reset's vector address (addresses FFFE16, FFFF16) immediately after reset. Figure 2.1.3 shows the program counter and the program bank register. (b23) b7 (b16) b0 b15 b8 b7 b0 PG PCH PCL Fig. 2.1.3 Program counter and program bank register 2.1.6 Program bank register (PG) The access space is divided in units of 64 Kbytes. This unit is called "bank." (Refer to section "2.3 Access space.") The program bank register is an 8-bit register. This register indicates the high-order 8 bits (bank) of the address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from an instruction queue buffer next) is stored. These 8 bits are called bank. When a carry occurs after adding the contents of the program counter or adding the offset value to the contents of the program counter in the branch instruction and others, the contents of the program bank register is automatically incremented by 1. When a borrow occurs after subtracting the contents of the program counter, the contents of the program bank register is automatically decremented by 1. Accordingly, there is no need to consider bank boundaries in programming, usually. This register is cleared to "0016" at reset. 2.1.7 Data bank register (DT) The data bank register is an 8-bit register. In the following addressing modes using the data bank register, the contents of this register is used as the high-order 8 bits (bank) of a 24-bit address to be accessed. Use the LDT instruction to set a value to this register. This register is cleared to "0016" at reset. qAddressing modes using data bank register *Direct indirect *Direct indexed X indirect *Direct indirect indexed Y *Absolute *Absolute bit *Absolute indexed X *Absolute indexed Y *Absolute bit relative *Stack pointer relative indirect indexed Y 7721 Group User's Manual 2-5 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1.8 Direct page register (DPR) The direct page register is a 16-bit register. The contents of this register indicate the direct page area which is allocated in bank 016 or in the space across banks 016 and 116. The following addressing modes use the direct page register. The contents of the direct page register indicate the base address (the lowest address) of the direct page area. The space which extends to 256 bytes above that address is specified as a direct page. The direct page register can contain a value from "000016" to "FFFF16." When it contains a value equal to or more than "FF0116," the direct page area spans the space across banks 016 and 116. When the contents of low-order 8 bits of the direct page register is "0016," the number of cycles required to generate an address is 1 cycle smaller than the number when its contents are not "0016." Accordingly, the access efficiency can be enhanced in this case. This register is cleared to "000016" at reset. Figure 2.1.4 shows a setting example of the direct page area. qAddressing modes using direct page register *Direct *Direct bit *Direct indexed X *Direct indexed Y *Direct indirect *Direct indexed X indirect *Direct indirect indexed Y *Direct indirect long *Direct indirect long indexed Y *Direct bit relative 016 016 FF16 12316 Direct page area when DPR = "000016" Bank 016 22216 Direct page area when DPR = "012316"(Note 1) FF1016 FFFF16 1000016 1000F16 Bank 116 Direct page area when DPR = "FF1016" (Note 2) Notes 1: The number of cycles required to generate an address is 1 cycle smaller when the low-order 8 bits of the DPR are "0016." 2: The direct page area spans the space across banks 016 and 116 when the DPR is "FF0116" or more. Fig. 2.1.4 Setting example of direct page area 2-6 7721 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1.9 Processor status register (PS) The processor status register is an 11-bit register. Figure 2.1.5 shows the structure of the processor status register. b15 b14 b13 b12 b11 b10 b9 0 0 0 0 0 IPL b8 b7 N b6 V b5 m b4 x b3 D b2 I b1 Z b0 C Processor status register (PS) Note: Bits 11-15 is always "0" at reading. Fig. 2.1.5 Processor status register structure (1) Bit 0: Carry flag (C) It retains a carry or a borrow generated in the arithmetic and logic unit (ALU) during an arithmetic operation. This flag is also affected by shift and rotate instructions. When the BCC or BCS instruction is executed, this flag's contents determine whether the program causes a branch or not. Use the SEC or SEP instruction to set this flag to "1," and use the CLC or CLP instruction to clear it to "0." (2) Bit 1: Zero flag (Z) It is set to "1" when a result of an arithmetic operation or data transfer is "0," and cleared to "0" when otherwise. When the BNE or BEQ instruction is executed, this flag's contents determine whether the program causes a branch or not. Use the SEP instruction to set this flag to "1," and use the CLP instruction to clear it to "0." Note: This flag is invalid in the decimal mode addition (the ADC instruction). (3) Bit 2: Interrupt disable flag (I) It disables all maskable interrupts (interrupts other than watchdog timer, the BRK instruction, and zero division). Interrupts are disabled when this flag is "1." When an interrupt request is accepted, this flag is automatically set to "1" to avoid multiple interrupts. Use the SEI or SEP instruction to set this flag to "1," and use the CLI or CLP instruction to clear it to "0." This flag is set to "1" at reset. (4) Bit 3: Decimal mode flag (D) It determines whether addition and subtraction are performed in binary or decimal. Binary arithmetic is performed when this flag is "0." When it is "1," decimal arithmetic is performed with 8 bits treated as two digits decimal (the data length flag (m) = "1") or 16 bits treated as four digits decimal (the data length flag (m) = "0"). Decimal adjust is automatically performed. Decimal operation is possible only with the ADC and SBC instructions. Use the SEP instruction to set this flag to "1," and use the CLP instruction to clear it to "0." This flag is cleared to "0" at reset. (5) Bit 4: Index register length flag (x) It determines whether each of index register X and index register Y is used as a 16-bit register or an 8-bit register. That register is used as a 16-bit register when this flag is "0," and as an 8-bit register when it is "1." Use the SEP instruction to set this flag to "1," and use the CLP instruction to clear it to "0." This flag is cleared to "0" at reset. Note: When transferring data between registers which are different in bit length, the data is transferred with the length of the destination register, but except for the TXA, TYA, TXB, TYB, and TXS instructions. Refer to "7700 Family Software Manual" for details. 7721 Group User's Manual 2-7 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (6) Bit 5: Data length flag (m) It determines whether to use a data as a 16-bit unit or as an 8-bit unit. A data is treated as a 16bit unit when this flag is "0," and as an 8-bit unit when it is "1." Use the SEM or SEP instruction to set this flag to "1," and use the CLM or CLP instruction to clear it to "0." This flag is cleared to "0" at reset. Note: When transferring data between registers which are different in bit length, the data is transferred with the length of the destination register, but except for the TXA, TYA, TXB, TYB, and TXS instructions. Refer to "7700 Family Software Manual" for details. (7) Bit 6: Overflow flag (V) It is used when adding or subtracting with a word regarded as signed binary. When the data length flag (m) is "0," the overflow flag is set to "1" when the result of addition or subtraction exceeds the range between -32768 and +32767, and cleared to "0" in all other cases. When the data length flag (m) is "1," the overflow flag is set to "1" when the result of addition or subtraction exceeds the range between -128 and +127, and cleared to "0" in all other cases. The overflow flag is also set to "1" when a result of division exceeds the register length to be stored in a division instruction DIV. When the BVC or BVS instruction is executed, this flag's contents determine whether the program causes a branch or not. Use the SEP instruction to set this flag to "1," and use the CLV or CLP instruction to clear it to "0." Note: This flag is invalid in the decimal mode. (8) Bit 7: Negative flag (N) It is set to "1" when a result of arithmetic operation or data transfer is negative. (Bit 15 of the result is "1" when the data length flag (m) is "0," or bit 7 of the result is "1" when the data length flag (m) is "1.") It is cleared to "0" in all other cases. When the BPL or BMI instruction is executed, this flag determines whether the program causes a branch or not. Use the SEP instruction to set this flag to "1," and use the CLP instruction to clear it to "0." Note: This flag is invalid in the decimal mode. (9) Bits 10 to 8: Processor interrupt priority level (IPL) These three bits can determine the processor interrupt priority level to one of levels 0 to 7. The interrupt is enabled when the interrupt priority level of a required interrupt, which is set in each interrupt control register, is higher than IPL. When an interrupt request is accepted, IPL is stored in the stack area, and IPL is replaced by the interrupt priority level of the accepted interrupt request. There are no instruction to directly set or clear the bits of IPL. IPL can be changed by storing the new IPL into the stack area and updating the processor status register with the PUL or PLP instruction. The contents of IPL is cleared to "0002" at reset. 2-8 7721 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit 2.2 Bus interface unit A bus interface unit (BIU) is built-in between the central processing unit (CPU) and memory*I/O devices. BIU's function and operation are described below. When externally connecting devices, refer to "CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES." 2.2.1 Overview Transfer operation between the CPU and memory*I/O devices is always performed via the BIU. The BIU reads an instruction from the memory before the CPU executes it. When the CPU reads data from the memory*I/O device, the CPU first specifies the address from which data is read to the BIU. The BIU reads data from the specified address and passes it to the CPU. When the CPU writes data to the memory*I/O device, the CPU first specifies the address to which data is written to the BIU and write data. The BIU writes the data to the specified address. To perform the above operations to , the BIU inputs and outputs the control signals, and control the bus. Figure 2.2.1 shows the bus and bus interface unit (BIU). 7721 Group User's Manual 2-9 Fig. 2.2.1 Bus and bus interface unit (BIU) Internal bus D8 to D15 Internal bus D0 to D7 Internal bus A0 to A23 Internal control signal 2-10 M37721 Internal bus Internal memory CPU bus Central processing unit (BIU) Bus interface unit 2.2 Bus interface unit (CPU) Internal peripheral device (SFR) CENTRAL PROCESSING UNIT (CPU) 7721 Group User's Manual External bus A0 to A7 A8/D8 to A15/D15 Bus conversion circuit A16/D0 to A23/D7 Control signals External device SFR : Special Function Register Notes 1: The CPU bus, internal bus, and external bus are independent of one another. 2: Refer to "CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES" about control signals of the external bus. CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit 2.2.2 Functions of bus interface unit (BIU) The bus interface unit (BIU) consists of four registers shown in Figure 2.2.2. Table 2.2.1 lists the functions of each register. b23 b0 PA b7 b0 Program address register Q0 Q1 Q2 b23 b0 Instruction queue buffer DA b15 b0 Data address register DBL Data buffer DBH Fig. 2.2.2 Register structure of bus interface unit (BIU) Table 2.2.1 Functions of each register Name Program address register Instruction queue buffer Data address register Data buffer Functions Indicates the storage address for the instruction which is next taken into the instruction queue buffer. Temporarily stores the instruction which has been taken in. Indicates the address for the data which is next read from or written to. Temporarily stores the data which is read from the memory*I/O device by the BIU or which is written to the memory*I/O device by the CPU. 7721 Group User's Manual 2-11 CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit The CPU and the bus send or receive data via BIU because each operates based on different clocks (Note). The BIU allows the CPU to operate at high speed without waiting for access to the memory * I/O devices that require a long access time. The BIU's functions are described bellow. CPU. The period of CPU is normally the same as that of . The internal Note: The CPU operates based on _ _ bus operates based on the E signal. The period of the E signal is twice that of at a minimum. (1) Reading out instruction (Instruction prefetch) When the CPU does not require to read or write data, that is, when the bus is not in use, the BIU reads instructions from the memory and stores them in the instruction queue buffer. This is called instruction prefetch. The CPU reads instructions from the instruction queue buffer and executes them, so that the CPU can operate at high speed without waiting for access to the memory which requires a long access time. When the instruction queue buffer becomes empty or contains only 1 byte of an instruction, the BIU performs instruction prefetch. The instruction queue buffer can store instructions up to 3 bytes. The contents of the instruction queue buffer is initialized when a branch or jump instruction is executed, and the BIU reads a new instruction from the destination address. When instructions in the instruction queue buffer are insufficient for the CPU's needs, the BIU extends the pulse duration of clock CPU in order to keep the CPU waiting until the BIU fetches the required number of instructions or more. (2) Reading data from memory*I/O device The CPU specifies the storage address of data to be read to the BIU's data address register, and requires data. The CPU waits until data is ready in the BIU. The BIU outputs the address received from the CPU onto the address bus, reads contents at the specified address, and takes it into the data buffer. The CPU continues processing, using data in the data buffer. However, if the BIU uses the bus for instruction prefetch when the CPU requires to read data, the BIU keeps the CPU waiting. (3) Writing data to memory*I/O device The CPU specifies the address of data to be written to the BIU's data address register. Then, the CPU writes data into the data buffer. The BIU outputs the address received from the CPU onto the address bus and writes data in the data buffer into the specified address. The CPU advances to the next processing without waiting for completion of BIU's write operation. However, if the BIU uses the bus for instruction prefetch when the CPU requires to write data, the BIU keeps the CPU waiting. (4) Bus control To perform the above operations (1) to (3), the BIU inputs and outputs the control signals, and controls the address bus and the data bus. The cycle in which the BIU controls the bus and accesses the memory*I/O device is called the bus cycle. Refer to "CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES" about the bus cycle at accessing the external devices. 2-12 7721 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit 2.2.3 Operation of bus interface unit (BIU) Figure 2.2.3 shows the basic operating waveforms of the bus interface unit (BIU). About signals which are input/output externally when accessing external devices, refer to "CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES." (1) When fetching instructions into the instruction queue buffer When the instruction which is next fetched is located at an even address, the BIU fetches 2 bytes at a time with the timing of waveform (a). However, when accessing an external device which is connected with the 8-bit external data bus width (BYTE = "H"), only 1 byte of the instruction is fetched. When the instruction which is next fetched is located at an odd address, the BIU fetches only 1 byte with the timing of waveform (a). The contents at the even address are not taken into the instruction queue buffer. (2) When reading or writing data to and from the memory*I/O device When accessing a 16-bit data which begins at an even address, waveform (a) is applied. The 16 bits of data are accessed at a time. When accessing a 16-bit data which begins at an odd address, waveform (b) is applied. The 16 bits of data are accessed separately in 2 operations, 8 bits at a time. Invalid data is not fetched into the data buffer. When accessing an 8-bit data at an even address, waveform (a) is applied. The data at the odd address is not fetched into the data buffer. When accessing an 8-bit data at an odd address, waveform (a) is applied. The data at the even address is not fetched into the data buffer. For instructions that are affected by the data length flag (m) and the index register length flag (x), operation or is applied when flag m or x = "0"; operation or is applied when flag m or x = "1." 7721 Group User's Manual 2-13 CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit (a) E Internal address bus (A0 to A23) Address Internal data bus (D0 to D7) Data (Even address) Internal data bus (D8 to D15) Data (Odd address) (b) E Internal address bus (A0 to A23) Address (Odd address) Address (Even address) Internal data bus (D0 to D7) Invalid data Data (Even address) Internal data bus (D8 to D15) Data (Odd address) Invalid data Fig. 2.2.3 Basic operating waveforms of bus interface unit (BIU) 2-14 7721 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.3 Access space 2.3 Access space Figure 2.3.1 shows the M37721's access space. By combination of the program counter (PC), which is 16 bits of structure, and the program bank register (PG), a 16-Mbyte space from addresses 016 to FFFFFF16 can be accessed. For details about access of an external area, refer to "CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES." The memory and I/O devices are assigned in the same access space. Accordingly, it is possible to perform transfer and arithmetic operations using the same instructions without discrimination of the memory from I/O devices. 00000016 00007F16 00008016 00047F16 Bank 016 001FC016 001FFF16 SFR area SFR area Internal RAM area 00FFFF16 01000016 Bank 116 02000016 FE000016 Bank FE16 FF000016 Bank FF16 FFFFFF16 : Indicates that nothing is assigned. : Indicates the memory assignment of the internal areas. : : : : Note : Memory assignment of internal RAM area varies according to the type of microcomputer. This figure shows the case of the M37721S2BFP. Refer to "Figure 2.4.1" for the M37721S1BFP. SFR : Special Function Register Fig. 2.3.1 M37721's access space 7721 Group User's Manual 2-15 CENTRAL PROCESSING UNIT (CPU) 2.3 Access space 2.3.1 Banks The access space is divided in units of 64 Kbytes. This unit is called "bank." The high-order 8 bits of address (24 bits) indicate a bank, which is specified by the program bank register (PG) or data bank register (DT). Each bank can be accessed efficiently by using an addressing mode that uses the data bank register (DT). If the program counter (PC) overflows at a bank boundary, the contents of the program bank register (PG) is incremented by 1. If a borrow occurs in the program counter (PC) as a result of subtraction, the contents of the program bank register (PG) is decremented by 1. Normally, accordingly, the user can program without concern for bank boundaries. SFR (Special Function Register) and internal RAM are assigned in bank 016. For details, refer to section "2.4 Memory assignment." 2.3.2 Direct page A 256-byte space specified by the direct page register (DPR) is called "direct page." A direct page is specified by setting the base address (the lowest address) of the area to be specified as a direct page into the direct page register (DPR). By using a direct page addressing mode, a direct page can be accessed with less instruction cycles than otherwise. Note: Refer also to section "2.1 Central processing unit." 2-16 7721 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.4 Memory assignment 2.4 Memory assignment This section describes the internal area's memory assignment. For more information about the external area, refer also to "CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES." Figure 2.4.1 shows the memory assignment. 2.4.1 Memory assignment in internal area SFR (Special Function Register) and internal RAM are assigned in the internal area. (1) SFR area The registers for setting internal peripheral devices are assigned at addresses 016 to 7F16 and 1FC016 to 1FFF16. This area is called SFR. Figures 2.4.2 and 2.4.3 show the SFR area's memory assignment. For each register in the SFR area, refer to each functional description in this manual. For the state of the SFR area immediately after reset, refer to section "4.1.2 State of CPU, SFR area, and internal RAM area." (2) Internal RAM area The M37721S2BFP (Note 1) assigns the 1024-byte static RAM at addresses 8016 to 47F16. 512 bytes of that can be selected either it is used as the internal RAM or it is used as the external area. (Note 2) The internal RAM area is used as a stack area (Note 3), as well as an area to store data. Accordingly, note that set the nesting depth of a subroutine and multiple interrupts' level not to destroy the necessary data. Notes 1: The M37721S1BFP assigns the 512-byte static RAM at addresses 8016 to 27F16. 2: The internal RAM area becomes 512 bytes after reset because the internal RAM area select bit is "0." 3: Either bank 016 or bank FF16 can be selected as the stack area by the stack bank select bit (bit 7 at address 5E16). Figure 2.4.4 shows the structure of the processor mode registers 0, 1. 7721 Group User's Manual 2-17 CENTRAL PROCESSING UNIT (CPU) 2.4 Memory assignment 2.4.2 External area Table 2.4.1 lists the external area. When connecting the external device, follow the procedure described bellow: *Connect the ROM to addresses FFCE16 to FFFF16 because they are interrupt vector table. *Stack area can be assigned to bank 016 or bank FF16. Select the stack area by the stack bank select bit (bit 7 at address 5E16). (Refer to "Figure 2.4.4.") *When using the DRAM controller, DRAM area can be selected from address FFFFFF16 toward the loworder address in a unit of 1 Mbytes. (Refer to "CHAPTER 14. DRAM CONTROLLER.") In the case connecting an external device to the area where overlaps the internal area, when reading out the overlapping area, the central processing unit (CPU) take in data of the internal area and do not take in data of the external area. When writing to the overlapping area, data is written to the internal area. The signal is output to the external at the same timing when data is written to the internal area. Table 2.4.1 External area Type name Internal RAM area select bit 216-916 External area 48016-1FBF16 200016-FFFFFF16 Internal RAM area select bit : bit 1 at address 5F16 M37721S2BFP 1 0 216-916 28016-1FBF16 200016-FFFFFF16 M37721S1BFP "0" (Fix this bit to "0.") 2-18 7721 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.4 Memory assignment M37721S2BFP 00000016 00007F16 00008016 00027F16 00FFCE16 00FFD016 00FFD216 00FFD416 00FFD616 00FFD816 00FFDA16 00FFDC16 00FFDE16 00FFE016 00FFE216 00FFE416 00FFE616 00FFE816 00FFEA16 00FFEC16 00FFEE16 00FFF016 00FFF216 00FFF416 00FFF616 00FFF816 00FFFA16 00FFFC16 00FFFE16 Interrupt vector table L DMA3 H L DMA2 H L DMA1 H L DMA0 H A-D conversion L H L UART1 transmit H L UART1 receive H UART0 transmit L H UART0 receive L H L Timer B2 H L Timer B1 H L Timer B0 H L Timer A4 H L Timer A3 H L Timer A2 H L Timer A1 H L Timer A0 H L INT2 H L INT1 H L INT0 H L Watchdog timer H L DBC (Note 3) H BRK instruction L H L zero divide H L RESET H M37721S1BFP SFR area (Note 1) Case of Internal RAM area select bit = "0" SFR area (Note 1) (512 bytes) Internal RAM area (512 bytes) Case of Internal RAM area select bit = "1" Internal RAM area (512 bytes) (Note 2) 00047F16 001FC016 SFR area 001FFF16 SFR area 00FFCE16 00FFFF16 FFFFFF16 : The internal memory is not assigned. SFR area: Refer to "Figure 2.4.2" and "Figure 2.4.3." Notes 1: Addresses 216 to 916 are the external memory area. 2: For the M37721S1BFP, fix the internal RAM area select bit to "0." 3: DBC is an interrupt only for debugging; do not use this interrupt. Fig. 2.4.1 Memory assignment 7721 Group User's Manual 2-19 CENTRAL PROCESSING UNIT (CPU) 2.4 Memory assignment Address 00000016 00000116 00000216 00000316 00000416 00000516 00000616 00000716 00000816 00000916 00000A16 Port P4 register 00000B16 Port P5 register 00000C16 Port P4 direction register 00000D16 Port P5 direction register 00000E16 Port P6 register 00000F16 Port P7 register 00001016 Port P6 direction register 00001116 Port P7 direction register 00001216 Port P8 register 00001316 Port P9 register 00001416 Port P8 direction register 00001516 Port P9 direction register 00001616 Port P10 register 00001716 00001816 Port P10 direction register 00001916 00001A16 Pulse output data register 0 00001B16 00001C16 Pulse output data register 1 00001D16 00001E16 A-D control register 00001F16 A-D sweep pin select register 00002016 A-D register 0 00002116 00002216 A-D register 1 00002316 00002416 A-D register 2 00002516 00002616 A-D register 3 00002716 00002816 A-D register 4 00002916 00002A16 A-D register 5 00002B16 00002C16 A-D register 6 00002D16 00002E16 A-D register 7 00002F16 00003016 UART0 transmit/receive mode register 00003116 UART0 baud rate register (BRG0) 00003216 UART0 transmit buffer register 00003316 00003416 UART0 transmit/receive control register 0 00003516 UART0 transmit/receive control register 1 00003616 UART0 receive buffer register 00003716 00003816 UART1 transmit/receive mode register 00003916 UART1 baud rate register (BRG1) 00003A16 UART1 transmit buffer register 00003B16 00003C16 UART1 transmit/receive control register 0 00003D16 UART1 transmit/receive control register 1 00003E16 UART1 receive buffer register 00003F16 Address 00004016 Count start register 00004116 00004216 One-shot start register 00004316 00004416 Up-down register 00004516 00004616 Timer A0 register 00004716 00004816 Timer A1 register 00004916 00004A16 Timer A2 register 00004B16 00004C16 Timer A3 register 00004D16 00004E16 Timer A4 register 00004F16 00005016 Timer B0 register 00005116 00005216 Timer B1 register 00005316 00005416 Timer B2 register 00005516 00005616 Timer A0 mode register 00005716 Timer A1 mode register 00005816 Timer A2 mode register 00005916 Timer A3 mode register 00005A16 Timer A4 mode register 00005B16 Timer B0 mode register 00005C16 Timer B1 mode register 00005D16 Timer B2 mode register 00005E16 Processor mode register 0 00005F16 Processor mode register 1 00006016 Watchdog timer register 00006116 Watchdog timer frequency select register 00006216 Real-time output control register 00006316 00006416 DRAM control register 00006516 00006616 Refresh timer 00006716 00006816 DMAC control register L 00006916 DMAC control register H 00006A16 00006B16 00006C16 DMA0 interrupt control register 00006D16 DMA1 interrupt control register 00006E16 DMA2 interrupt control register 00006F16 DMA3 interrupt control register 00007016 A-D conversion interrupt control register 00007116 UART0 transmit interrupt control register 00007216 UART0 receive interrupt control register 00007316 UART1 transmit interrupt control register 00007416 UART1 receive interrupt control register 00007516 Timer A0 interrupt control register 00007616 Timer A1 interrupt control register 00007716 Timer A2 interrupt control register 00007816 Timer A3 interrupt control register 00007916 Timer A4 interrupt control register 00007A16 Timer B0 interrupt control register 00007B16 Timer B1 interrupt control register 00007C16 Timer B2 interrupt control register 00007D16 INT0 interrupt control register 00007E16 INT1 interrupt control register 00007F16 INT2 interrupt control register Fig. 2.4.2 SFR area's memory map (1) 2-20 7721 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.4 Memory assignment Address 001FC016 001FC116 001FC216 001FC316 001FC416 001FC516 001FC616 001FC716 001FC816 001FC916 001FCA16 001FCB16 001FCC16 001FCD16 001FCE16 001FCF16 001FD016 001FD116 001FD216 001FD316 001FD416 001FD516 001FD616 001FD716 001FD816 001FD916 001FDA16 001FDB16 001FDC16 001FDD16 001FDE16 001FDF16 001FE016 001FE116 001FE216 001FE316 001FE416 001FE516 001FE616 001FE716 001FE816 001FE916 001FEA16 001FEB16 001FEC16 001FED16 001FEE16 001FEF16 001FF016 001FF116 001FF216 001FF316 001FF416 001FF516 001FF616 001FF716 001FF816 001FF916 001FFA16 001FFB16 001FFC16 001FFD16 001FFE16 001FFF16 Source address register 0 L M H L M H L M H Destination address register 0 Transfer counter register 0 DMA0 mode register L DMA0 mode register H DMA0 control register L M H L M H L M H Source address register 1 Destination address register 1 Transfer counter register 1 DMA1 mode register L DMA1 mode register H DMA1 control register L M H L M H L M H Source address register 2 Destination address register 2 Transfer counter register 2 DMA2 mode register L DMA2 mode register H DMA2 control register L M H L M H L M H Source address register 3 Destination address register 3 Transfer counter register 3 DMA3 mode register L DMA3 mode register H DMA3 control register Fig. 2.4.3 SFR area's memory map (2) 7721 Group User's Manual 2-21 CENTRAL PROCESSING UNIT (CPU) 2.4 Memory assignment b7 b6 b5 b4 b3 b2 b1 b0 0 0 Processor mode register 0 (Address 5E16) Bit 0 1 2 Bit name Fix this bit to "0." Nothing is assigned. The value is "1" at reading. Wait bit Functions At reset RW RW - RW 0 1 0 : Software Wait is inserted when accessing external area. 1 : No software Wait is inserted when accessing external area. The microcomputer is reset by writing "1" to this bit. The value is "0" at reading. b5 b4 0 3 Software reset bit 0 WO 4 5 6 7 Interrupt priority detection time select bits 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : Do not select. 0 0 0 RW RW RW RW Fix this bit to "0." Stack bank select bit 0 : Bank 016 1 : Bank FF16 0 : Bits 0 to 6 are not used for the memory assignment. b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 1 (Address 5F16) Bit 0 1 Bit name Nothing is assigned. Internal RAM area select bit (Notes 1, 2) Functions At reset RW - RW - Undefined 0 : 512 bytes (addresses 8016 to 27F16) 1 : 1024 bytes (addresses 8016 to 47F16) 0 Undefined 7 to 2 Nothing is assigned. Notes 1: For the M37721S1BFP, fix bit 1 to "0." 2: For the M37721S2BFP, set bit 1 before setting the stack pointer. Fig. 2.4.4 Structure of processor mode registers 0, 1 2-22 7721 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.5 Bus access right 2.5 Bus access right The M37721's bus is used for DRAMC, Hold function, and DMAC besides CPU. When the bus requests of two or more source are detected at the same timing, the highest bus access priority levels get the access right. The bus priority levels are fixed by hardware. Additionally the bus use state is output from the status signal output pins ST0 and ST1. Table 2.5.1 lists the bus use priority levels and the status signals depending on the bus use state. Table 2.5.1 Bus use priority levels and status signals depending on bus use state Bus use priority levels 1 (Highest) 2 3 4 (Lowest) DRAM refresh Hold DMAC CPU (Including the term that CPU does not use the bus during calculation etc.) Bus use state Status signal ST1 0 0 1 1 ST0 0 1 0 1 For details, refer to section "13.2.1 Bus access control circuit" and chapter for each peripheral devices. 7721 Group User's Manual 2-23 CENTRAL PROCESSING UNIT (CPU) 2.5 Bus access right MEMORANDUM 2-24 7721 Group User's Manual CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES 3.1 Signals required for accessing external devices 3.2 Software Wait 3.3 Ready function 3.4 Hold function [Precautions for Hold function] CONNECTION WITH EXTERNAL DEVICES 3.1 Signals required for accessing external devices 3.1 Signals required for accessing external devices The functions and operations of the signals which are required for accessing the external devices are described below. When connecting an external device that requires long access time, refer to sections "3.2 Software Wait," "3.3 Ready function," and "3.4 Hold function," as well as this section. When the external DRAM is controlled by using DRAM controller, refer to "CHAPTER 14. DRAM CONTROLLER." 3.1.1 Descriptions of signals Figure 3.1.1 shows the pin configurations when the external data bus width is 16 bits and 8 bits. (1) External buses (A0-A7, A8/D8-A15/D15, A16/D0-A23/D7) The external area is specified by the address (A0-A23) output. The A8-A23 pins of the external address bus and the D0-D15 pins of the external data bus are assigned to the same pins. When the BYTE pin level, described later, is "L" (external data bus width is 16 bits), the A8/D8- A15/D15 and A16/D0-A23/D7 pins perform address output and data input/output with time-sharing. When the BYTE pin level is "H" (external data bus width is 8 bits), the A16/D0-A23/D7 pins perform address output and data input/output with time-sharing, and the A8-A15 pins output the address. (2) External data bus width switching signal (BYTE pin level) This signal is used to select the external data bus width from 8 bits and 16 bits. The width is 16 bits when the level is "L," and 8 bits when the level is "H." Fix this signal to either "H" or "L" level. This signal is valid only for the external area. (When accessing the internal area, the data bus width is always 16 bits.) __ (3) Enable signal (E) This signal becomes "L" level while reading or writing data from and to the data bus. (Refer to "Table 3.1.1.") __ (4) Read/Write signal (R/W) This signal indicates the state of the data bus. This signal becomes "L" level while writing data to __ __ the data bus. Table 3.1.1 lists the state of the data bus indicated with the E and R/W signals. _ Table 3.1.1 State of data bus indicated with E and __ R/W signals __ __ State of data bus E R/W H H Not used L L H L Read data Write data 3-2 7721 Group User's Manual 100 100 P86/RXD1 P85/CLK1 P84/CTS1/RTS1 P83/TXD0 P82/RXD0 P81/CLK0 P80/CTS0/RTS0 VCC AVCC VREF AVSS VSS P77/AN7/ADTRG P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 23 24 25 26 27 28 29 1 30 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P86/RXD1 P85/CLK1 P84/CTS1/RTS1 P83/TXD0 P82/RXD0 P81/CLK0 P80/CTS0/RTS0 VCC AVCC VREF AVSS VSS P77/AN7/ADTRG P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 qExternal data bus width = 8 bits (BYTE = "H") qExternal data bus width = 16 bits (BYTE = "L") 17 M37721S2BFP M37721S2BFP 18 19 20 21 Note: For the DRAM control signals, refer to "CHAPTER 14. DRAM CONTROLLER." Fig. 3.1.1 Pin configurations when external data bus width is 16 bits and 8 bits (top view) P87/TXD1 P90/DMAACK0 P91/DMAREQ0 P92/DMAACK1 P93/DMAREQ1 P94/DMAACK2 P95/DMAREQ2 P96/DMAACK3 P97/DMAREQ3 A0/MA0 A1/MA1 A2/MA2 A3/MA3 A4/MA4 A5/MA5 A6/MA6 A7/MA7 A8 A9 A10 A11 A12 A13 A14 A15 A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 P57/TB1IN P56/TB0IN P55/TA4IN P54/TA4OUT P53/TA3IN P52/TA3OUT P51/TA2IN P50/TA2OUT P107/MA9 P106/MA8 P105/RAS P104/CAS P103/TC P102/INT2 P101/INT1 P100/INT0 P47 P46 P45 P44 P43 P87/TXD1 P90/DMAACK0 P91/DMAREQ0 P92/DMAACK1 P93/DMAREQ1 P94/DMAACK2 P95/DMAREQ2 P96/DMAACK3 P97/DMAREQ3 A0/MA0 A1/MA1 A2/MA2 A3/MA3 A4/MA4 A5/MA5 A6/MA6 A7/MA7 A8/D8 A9/D9 A10/D10 A11/D11 A12/D12 A13/D13 A14/D14 A15/D15 A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 CONNECTION WITH EXTERNAL DEVICES 3.1 Signals required for accessing external devices 7721 Group User's Manual bus control signal : External address bus, external data bus, 22 23 24 25 26 27 28 P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 P57/TB1IN P56/TB0IN P55/TA4IN P54/TA4OUT P53/TA3IN P52/TA3OUT P51/TA2IN P50/TA2OUT P107/MA9 P106/MA8 P105/RAS P104/CAS P103/TC P102/INT2 P101/INT1 P100/INT0 P47 P46 P45 P44 P43 29 1 30 : External address bus, external data bus, bus control signal 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A21/D5 A22/D6 A23/D7 R/W BHE BLE ALE ST0 ST1 VCC VSS E XOUT XIN RESET RESETOUT CNVSS BYTE HOLD RDY A21/D5 A22/D6 A23/D7 R/W BHE BLE ALE ST0 ST1 VCC VSS E XOUT XIN RESET RESETOUT CNVSS BYTE HOLD RDY 3-3 CONNECTION WITH EXTERNAL DEVICES 3.1 Signals required for accessing external devices ____ ____ (5) Byte____ enable signal (BLE), Byte high enable signal (BHE) low The BLE signal indicates the access to an even address. This signal becomes "L" level when accessing only an even address or when simultaneously accessing both an even and an odd address. ____ The BHE signal indicates the access to an odd address. This signal becomes "L" level when accessing only an odd address or when simultaneously accessing both an odd and an even address. These signals are used to connect memories or I/O devices of which data bus width is 8 bits when ____ ____ the external data bus width is 16 bits. Table 3.1.2 lists levels of the BLE and BHE signals and access addresses. ____ ____ Table 3.1.2 Levels of BLE and BHE signals and access addresses Access address ____ ____ Even and odd addresses (Simultaneous 2-byte access) L L Even address (1-byte access) L H Odd address (1-byte access) H L BLE BHE (6) Address latch enable signal (ALE) This signal is used to latch the address from the multiplexed signal, which consists of the address and data. (This multiplexed signal is input to or output from the A8/D8-A15/D15 and A16/D0-A23/D7 pins.) When the ALE signal is "H," latch the address and simultaneously output the addresses. When this signal is "L," retain the latched address. ____ (7) Ready function-related signal (RDY) This is the signal to use Ready function (Refer to section "3.3 Ready function.") _____ (8) Hold function-related signal (HOLD) This is the signal to use Hold function. (Refer to section "3.4 Hold function.") (9) Status signals (ST0, ST1) These signals indicate the bus use status. Table 3.1.3 lists the bus use status indicated by the ST0 and ST1 signals. (10) Clock 1 This signal has the same period as . Table 3.1.3 Bus use status indicated by ST0 and ST1 signals ST1 L L H H ST0 L H L H Bus use status DRAM refresh Hold DMA CPU 3-4 7721 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.1 Signals required for accessing external devices 3.1.2 Operation of bus interface unit (BIU) Figures 3.1.2 and 3.1.3 show the examples of operating waveforms of the signals input from or output to the external when accessing external devices. The following explains these waveforms, being compared with the basic operating waveform. (Refer to section "2.2.3 Operation of bus interface unit (BIU).") (1) When fetching instructions into instruction queue buffer When the instruction which is next fetched is located at an even address When the external data bus width is 16 bits, the BIU fetches 2 bytes of the instruction at a time with waveform (a). When the external data bus width is 8 bits, the BIU fetches only 1 byte of the instruction with the first half of waveform (e). When the instruction which is next fetched is located at an odd address When the external data bus width is 16 bits, the BIU fetches only 1 byte of the instruction with waveform (d). When the external data bus width is 8 bits, the BIU fetches only 1 byte of the instruction with the first half of waveform (f). When a branch to an odd address is caused by a branch instruction etc. with the 16-bit external data bus width, the BIU first fetches 1 byte of the instruction with waveform (d), and after that, fetches instructions in a unit of 2 bytes with waveform (a). (2) When reading or writing data from and to memories or I/O devices When accessing 16-bit data which begins at an even address, waveform (a) or (e) is applied. When accessing 16-bit data which begins at an odd address, waveform (b) or (f) is applied. When accessing 8-bit data at an even address, waveform (c) or the first half of (e) is applied. When accessing 8-bit data at an odd address, waveform (d) or the first half of (f) is applied. For instructions that are affected by the data length flag (m) and the index register length flag (x), operation or is applied when flag m or x = "0"; operation or is applied when flag m or x = "1." The setup of flags m and x and the selection of the external data bus width do not affect each other. 7721 Group User's Manual 3-5 CONNECTION WITH EXTERNAL DEVICES 3.1 Signals required for accessing external devices q External data bus width = 16 bits (BYTE = "L") <16-bit data access> (a) Access beginning at even address E ALE A0 to A7 A8/D8 to A15/D15 A16/D0 to A23/D7 BLE BHE Address Address Address Data(odd) Data(even) (b) Access beginning at odd address E ALE A0 to A7 A8/D8 to A15/D15 A16/D0 to A23/D7 BLE BHE Address Address Address Data(odd) Address Address Address Data(even) <8-bit data access> (c) Access to even address E ALE A0 to A7 A8/D8 to A15/D15 A16/D0 to A23/D7 BLE BHE Address Address Address Data(even) (d) Access to odd address E ALE A0 to A7 A8/D8 to A15/D15 A16/D0 to A23/D7 BLE BHE Address Address Address Data(odd) Fig. 3.1.2 Examples of operating waveforms of signals input from or output to the external (1) 3-6 7721 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.1 Signals required for accessing external devices q External data bus width = 8 bits (BYTE = "H") <8/16-bit data access> (e) Access beginning at even address E ALE A0 to A7 A8 to A15 A16/D0 to A23/D7 BLE BHE 8-bit data access 16-bit data access Address Address Address Data Address Address Address Data (f) Access beginning at odd address E ALE A0 to A7 A8 to A15 A16/D0 to A23/D7 BLE BHE 8-bit data access 16-bit data access Address Address Address Data Address Address Address Data Note: When accessing 16-bit data, 2 times of access are performed; the low-order 8 bits are accessed first, and after that, the highorder 8 bits are accessed. Fig. 3.1.3 Examples of operating waveforms of signals input from or output to the external (2) 7721 Group User's Manual 3-7 CONNECTION WITH EXTERNAL DEVICES 3.2 Software Wait 3.2 Software Wait Software Wait provides a function to facilitate access to external devices that require long access time. To select the software Wait, use the wait bit (bit 2 at address 5E16). Figure 3.2.1 shows the structure of processor mode register 0 (address 5E16). Figure 3.2.2 shows examples of bus timing when software Wait is used. Software Wait is valid only for the eternal area. The internal area is always accessed with no Wait. b7 b6 b5 b4 b3 b2 b1 b0 0 0 Processor mode register 0 (Address 5E16) Bit 0 1 2 Bit name Fix this bit to "0." Nothing is assigned. The value is "1" at reading. Wait bit Functions At reset RW RW - RW 0 1 0 : Software Wait is inserted when accessing external area. 1 : No software Wait is inserted when accessing external area. The microcomputer is reset by writing "1" to this bit. The value is "0" at reading. b5 b4 0 3 Software reset bit 0 WO 4 5 6 7 Interrupt priority detection time select bits 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : Do not select. 0 0 0 RW RW RW RW Fix this bit to "0." Stack bank select bit 0 : Bank 016 1 : Bank FF16 0 : Bits 0, 1, and 3 to 6 are not used for accessing external area. Fig. 3.2.1 Structure of processor mode register 0 3-8 7721 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.2 Software Wait 1 bus cycle Clock 1 E ALE A0--A7 (Note) Address Address Data Address Address Data A8/D8--A15/D15, A16/D0--A23/D7 qInternal areas are always accessed with this waveform. 1 bus cycle Clock 1 E ALE A0--A7 (Note) Address Address Data Address Address Data A8/D8--A15/D15, A16/D0--A23/D7 Note: When the external data bus is 8 bits wide (BYTE = "H"), A8/D8 to A15/D15 operate with the same bus timing as A0 to A7. Fig. 3.2.2 Examples of bus timing when software Wait is used (BYTE = "L") 7721 Group User's Manual 3-9 CONNECTION WITH EXTERNAL DEVICES 3.3 Ready function 3.3 Ready function Ready function provides the function to facilitate access to external devices that require long access time. ____ The microcomputer enters Ready state by input of "L" level to the RDY pin and retains this state while the ____ level of the RDY pin is at "L." Table 3.3.1 lists the microcomputer's state in Ready state. In Ready state, the oscillator's oscillation does not stop. Accordingly, the internal peripheral devices can operate. Ready function is valid for the internal and external areas. Table 3.3.1 Microcomputer's state in Ready state Item Oscillation Operating State Stopped at "L" CPU, _ __ Pins A0 to A7, A8/D8 to A15/D15, A16/D0 to A23/D7, E, R/W, Retain the state when Ready request was accepted. ____ ____ BHE, BLE, ST0, ST1, ALE Pins P43 to P47, P5 to P10 (Note) Outputs clock 1. Pin 1 Watchdog timer Operating Note: This applies when this functions as a programmable I/O port. 3-10 7721 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.3 Ready function 3.3.1 Operation description ____ The input level of the RDY pin is judged at the falling edge of clock 1. When "L" level is detected at this point, the microcomputer enters Ready state. (This is called "Acceptance of Ready request.") ____ In Ready state, the input level of the RDY pin is judged at every falling edge of clock 1. When "H" level is detected at this point, the microcomputer terminates Ready state at the next rising edge of clock 1. Figure 3.3.1 shows timing of acceptance of Ready request and termination of Ready state. Refer also to section "16.1 Memory connection" for usage of Ready function. RDY pin input level sampling timing Clock 1 The "L" level which is input to the RDY pin is accepted, so that E stops at "H " level for 1 cycle of clock 1 (indicated by ), and CPU stops at "L" level. CPU E The "L" level which is input to the RDY pin is not accepted, however CPU stops at "L" level. ALE The "L" level which is input to th e RDY pin is accepted, so that E stops at "L" level for 1 cycle of clock 1 (indicated by ), and CPU stops at "L" level. RDY Bus not in use Bus in use Ready state is terminated. The "L" level which is input to the RDY pin is not RDY pin input level sampling timing Clock 1 accepted because it is sampled immediately before Wait by software Wait (indicated by ), however CPU stops at "L" level. CPU E ALE RDY Bus in use Fig. 3.3.1 Timing of acceptance of Ready request and termination of Ready state 7721 Group User's Manual 3-11 CONNECTION WITH EXTERNAL DEVICES 3.4 Hold function 3.4 Hold function When composing the external circuit which accesses the bus without using the central processing unit (CPU), Hold function is used to generate a timing for transferring the right to use the bus from the CPU to the external circuit. _____ The microcomputer enters Hold state by input of "L" level to the HOLD pin and retains this state while the _____ level of the HOLD pin is at "L." Table 3.4.1 lists the microcomputer's state in Hold state. In Hold state, the oscillation of the oscillator does not stop. Accordingly, the internal peripheral devices can operate. However, Watchdog timer stops operating. Table 3.4.1 Microcomputer's state in Hold state Item Oscillation Operating State Operating Stopped at "L" CPU _ Stopped at "H" E __ Pins A0 to A7, A8/D8 to A15/D15, A16/D0 to A23/D7, R/W, Floating ___ ____ BHE, BLE Output "L" level. Pins ALE, ST1 Pin ST0 Outputs "H" level. Pin 1 Outputs clock 1. Pins P43 to P47, P5 to P10 (Note) Retain the state when Hold request was accepted. Watchdog timer Stopped Note: This applies when this functions as a programmable I/O port. 3.4.1 Operation _____ description Judgment of the HOLD pin input level is performed at every falling edge of 1. When "L" level is detected at judgment of the input level, bus request (Hold) becomes "1," when "H" level is detected, bus request (Hold) becomes "0." Bus request (Hold) is sampled within a period when the bus request sampling signal is "1" and bus request is accepted when there is no bus request (DRAMC). (This is called "Acceptance of Hold request.") For bus request, refer to section "13.2.1 Bus access control circuit." When Hold request is accepted, CPU stops at "L" level at the next rising edge of and the ST0 pin's level becomes "H," the ST1 pin's level becomes "L." When 1 cycle of has passed after the levels of the ST0 __ ____ ____ and ST1 pins are changed, the R/W, BHE, BLE pins and the external bus enter the floating state. _____ In Hold state, when the HOLD pin's input level becomes "H," the ST0 and ST1 pins' levels are changed at the next rising edge of . When 1 cycle of has passed after the levels of the ST0 and ST1 pins are changed, the microcomputer terminates Hold state. Figures 3.4.1 to 3.4.3 show timing of acceptance of Hold request and termination of Hold state. Note: has the same polarity and the same frequency as clock 1. However, stops by acceptance of Ready request, or executing the STP or WIT instruction. Accordingly, _____ judgment of the input level of the HOLD pin is not performed during Ready state. 3-12 7721 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.4 Hold function External data bus Unused Data length External data bus width 8 16 8, 16 8, 16 Clock 1 (Note 1) ALE E Floating R/W External address bus / External data bus External address bus BLE, BHE HOLD Bus request (Hold) (Note 2) Floating Address A Floating Address B Bus request sampling (Note 2) ST1 ST0 Hold state Bus not in use Transfer of right to use bus Bus in use Transfer of right to use bus This is the period in which the bus is not used, so that not a new address but the address which was output immediately before is output again. Notes 1: Clock 1 has the same polarity and the same frequency as . Timing of signals to be input from or output to the external is ordained on the basis of clock 1. 2: Bus request (Hold) and bus request sampling are internal signals. Fig. 3.4.1 Timing of acceptance of Hold request and termination of Hold state (1) 7721 Group User's Manual 3-13 CONNECTION WITH EXTERNAL DEVICES 3.4 Hold function External data bus Data length External data bus width 8 Used 8, 16 16 (Access beginning at even address) 16 Clock 1 (Note 2) ALE E Floating R/W Address A Address A Floating Data Floating Address B External address bus / External data bus External address bus BLE, BHE HOLD Bus request (Hold) (Note 3) Bus request sampling (Note 3) ST1 ST0 Hold state Bus in use Bus in use Transfer of right to use bus Transfer of right to use bus When a Hold request is accepted, not a new address but the address which was output immediately before is output again. Notes 1: The above diagram shows the case of no Wait. 2: Clock 1 has the same polarity and the same frequency as . Timing of signals to be input from or output to the external is ordained on the basis of clock 1. 3: Bus request (Hold) and bus request sampling are internal signals. Fig. 3.4.2 Timing of acceptance of Hold request and termination of Hold state (2) 3-14 7721 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.4 Hold function External data bus Data length External data bus width Used 16 8 16 (Access beginning at odd address) Clock 1 (Note 2) ALE E Floating R/W Address A Address A + 1 Floating Address B External address bus / External data bus External address bus BLE, BHE HOLD Bus request (Hold) (Note 3) Bus request sampling (Note 3) ST1 ST0 Data Data Floating Hold state Bus in use Transfer of right to use bus Transfer of right to use bus Bus in use When a Hold request is accepted, not a new address but the address which was output immediately before is output again. Notes 1: The above diagram shows the case of 2- access in low-speed running. 2: Clock 1 has the same polarity and the same frequency as . Timing of signals to be input from or output to the external is ordained on the basis of clock 1. 3: Bus request (Hold) and bus request sampling are internal signals. Fig. 3.4.3 Timing of acceptance of Hold request and termination of Hold state (3) 7721 Group User's Manual 3-15 CONNECTION WITH EXTERNAL DEVICES 3.4 Hold function [Precautions for Hold function] When a DRAM refresh request occurs in Hold state, DRAM refresh is performed immediately because the bus use priority level of DRAM refresh is higher than that of Hold function. 3-16 7721 Group User's Manual CHAPTER 4 RESET 4.1 Hardware reset 4.2 Software reset RESET 4.1 Hardware reset 4.1 Hardware reset When the power source voltage satisfies the microcomputer's recommended operating conditions, the ______ microcomputer is reset by supplying "L" level to the RESET pin. This is called a hardware reset. Figure 4.1.1 shows an example of hardware reset timing. RESET 2 s or more 4 to 5 cycles of Internal processing sequence after reset Program is executed. Note: When the clock is stably supplied. (Refer to section "4.1.4 Time supplying "L" level to RESET pin.") Fig. 4.1.1 Example of hardware reset timing The following explains how the microcomputer operates in periods to above. After supplying "L" level to the RESET pin, the microcomputer initializes pins within a period of several ten ns. (Refer to "Table 4.1.1.") ______ ______ While the RESET pin is "L" level and within a period of 4 to 5 cycles of after the RESET pin goes from "L" to "H," the microcomputer initializes the central processing unit (CPU) and SFR area. At this time, the contents of the internal RAM area become undefined (except when Stop or Wait mode is terminated). (Refer to "Figures 4.1.3 to 4.1.9.") After , the microcomputer performs "Internal processing sequence after reset." (Refer to "Figure 4.1.10.") The microcomputer executes a program beginning with the address set into the reset vector addresses (FFFE16 and FFFF16). ______ 4-2 7721 Group User's Manual RESET 4.1 Hardware reset 4.1.1 Pin state ______ Table 4.1.1 lists the microcomputer's pin state while RESET pin is at "L" level. Figure 4.1.2 shows the ________ RESETOUT output retaining timing. ______ Table 4.1.1 Pin state while RESET pin is at "L" level Pin (Bus, Port) name ____ ____ A0/MA0-A7/MA7, A8/D8-A15/D15, A16/D0-A23/D7, BHE, BLE __ _ Pin state Outputs "H" or "L" level. Outputs "H" level. Outputs "L" level. Outputs 1. Floating. R/W, E, ST0, ST1 _________ ALE, RESETOUT 1 _____ ____ HOLD, RDY, P43-P47, P5-P10 When RESET pin input level goes from "L" to "H" in this period 1 RESET 3.5 cycles of RESETOUT 1 ________ Fig. 4.1.2 RESETOUT output retaining timing 7721 Group User's Manual 4-3 RESET 4.1 Hardware reset 4.1.2 State of CPU, SFR area, and internal RAM area Figure 4.1.3 shows the state of the CPU registers immediately after reset. Figures 4.1.4 to 4.1.9 show the state of the SFR and internal RAM areas immediately after reset. 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. 0 : Always "0" at reading. Register name b15 Accumulator A (A) State immediately after reset b8 b7 b0 ? b15 b8 b7 ? b0 Accumulator B (B) ? b15 b8 b7 ? b0 Index register X (X) ? b15 b8 b7 ? b0 Index register Y (Y) ? b15 b8 b7 ? b0 Stack pointer (S) ? b7 ? b0 Data bank register (DT) 0016 b7 b0 Program bank register (PG) 0016 b15 b8 b7 b0 Program counter (PC) Contents at address FFFF16 b15 b8 Contents at address FFFE16 b7 b0 Direct page register (DPR) 0016 b15 b8 b7 0016 b0 Processor status register (PS) 0 0 0 0 0 0 0 IPL 0 ? N ? V 0 m 0 x 0 D 1 I ? Z ? C Fig. 4.1.3 State of CPU registers immediately after reset 4-4 7721 Group User's Manual RESET 4.1 Hardware reset qSFR area (016 to 7F16, 1FC016 to 1FFF16) Access characteristics R W : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Underfined immediately after reset. 0 1 ? : Always "0" at reading. : Always "1" at reading. : Always undefined at reading. : "0" immediately after reset. Fix this bit to "0." State immediately after reset ? ? ? ? ? ? ? ? ? ? 0 Address Register name 016 116 216 316 416 516 616 716 816 916 Port P4 register A16 Port P5 register B16 C16 Port P4 direction register D16 Port P5 direction register Port P6 register E16 Port P7 register F16 1016 Port P6 direction register 1116 Port P7 direction register 1216 Port P8 register Port P9 register 1316 1416 Port P8 direction register 1516 Port P9 direction register Port P10 register 1616 1716 1816 Port P10 direction register 1916 1A16 Pulse output data register 0 1B16 1C16 Pulse output data register 1 1D16 1E16 A-D control register 1F16 A-D sweep pin select register b7 Access characteristics b0 b7 b0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW WO WO RW RW 0 ? 0 ? 0 0 ? ? 0 00 0016 ? ? 0016 0016 ? ? 0016 0016 ? ? 0016 ? ? ? ? ? 00 ?? 0 0 0 0 0 0 0 ? ? ? ? 1 ? 1 Fig. 4.1.4 State of SFR and internal RAM areas immediately after reset (1) 7721 Group User's Manual 4-5 RESET 4.1 Hardware reset Address 2016 2116 2216 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 2C16 2D16 2E16 2F16 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C16 3D16 3E16 3F16 Register name A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 UART0 transmit/receive mode register UART0 baud rate register UART0 transmit buffer register b7 Access characteristics RO RO RO RO RO RO RO RO RW WO WO RO RO RO b0 b7 State immediately after reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0016 ? ? ? ?1 00 ? 00 0016 ? ? ? ?1 00 ? 00 b0 UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 baud rate register UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register WO RW RW RO RW RO ? 0 0 ? 0 0 ? 0 0 0 0 0 0 1 0 0 0 ? RW WO WO RO RO RO RO 0 0 0 WO RW RW RO RW ? 0 ? 0 ? 0 0 0 0 0 1 0 0 0 ? Fig. 4.1.5 State of SFR and internal RAM areas immediately after reset (2) 4-6 7721 Group User's Manual RESET 4.1 Hardware reset Address Register name b7 Count start register Access characteristics b0 State immediately after reset b7 b0 4016 4116 4216 One-shot start register 4316 Up-down register 4416 4516 4616 Timer A0 register 4716 4816 Timer A1 register 4916 4A16 Timer A2 register 4B16 4C16 Timer A3 register 4D16 4E16 Timer A4 register 4F16 5016 Timer B0 register 5116 5216 Timer B1 register 5316 5416 Timer B2 register 5516 5616 Timer A0 mode register 5716 Timer A1 mode register 5816 Timer A2 mode register 5916 Timer A3 mode register 5A16 Timer A4 mode register 5B16 Timer B0 mode register 5C16 Timer B1 mode register 5D16 Timer B2 mode register 5E16 Processor mode register 0 5F16 Processor mode register 1 RW WO WO RW RW RW RW (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) (Note 2) RW RW RW RW RW RW RW RW RW RW (Note 3) (Note 3) (Note 3) ? 0 0 0 RW 0 0 0 0 0 0 RW RW RW RW WO RW RW RW 0 0 0 0 0 0 0 0 ? ? ? 0 ? 0016 ? 00 ? 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 00 00 0016 0016 0016 ?0 ?0 ?0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 (Note 4) 0 0 0 0 ? Notes 1: The access characteristics at addresses 4A16 to 4F16 vary according to Timer A's operating mode. (Refer to "CHAPTER 8. TIMER A.") 2: The access characteristics at addresses 5016 to 5316 vary according to Timer B's operating mode. (Refer to "CHAPTER 9. TIMER B.") 3: The access characteristics for bit 5 at addresses 5B16 and 5C16 vary according to Timer B's operating mode. Bit 5 at address 5D16 is invalid. (Refer to "CHAPTER 9. TIMER B.") 4: Bit 1 at address 5F16 becomes "0" immediately after reset. For the M37721S1BFP, fix this bit to "0." Fig. 4.1.6 State of SFR and internal RAM areas immediately after reset (3) 7721 Group User's Manual 4-7 RESET 4.1 Hardware reset Address Register name b7 Access characteristics (Note 5) b0 b7 State immediately after reset ?(Note 6) ? 00 ? 00 ? ? ? 0? 00 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 b0 Watchdog timer register 6016 Watchdog timer frequency select register 6116 6216 Real-time output control register 6316 DRAM control register 6416 6516 Refresh timer 6616 6716 DM AC control register L 6816 DM AC control register H 6916 6A16 6B16 DM A0 interrupt control register 6C16 DM A1 interrupt control register 6D16 DM A2 interrupt control register 6E16 DM A3 interrupt control register 6F16 7016 A-D conversion interrupt control register 7116 UART0 transmit interrupt control register 7216 UART0 receive interrupt control register 7316 UART1 transmit interrupt control register 7416 UART1 receive interrupt control register Timer A0 interrupt control register 7516 Timer A1 interrupt control register 7616 Timer A2 interrupt control register 7716 Timer A3 interrupt control register 7816 Timer A4 interrupt control register 7916 Timer B0 interrupt control register 7A16 Timer B1 interrupt control register 7B16 Timer B2 interrupt control register 7C16 INT0 interrupt control register 7D16 INT1 interrupt control register 7E16 INT2 interrupt control register 7F16 RW RW RW WO (Note 7) RW 00 RW 00 0 0 0 0 0 0 0 0 0 RW WO RW 0 0 0 0 0 0 ? 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Notes 5: By writing dummy data to address 6016, the value "FFF16" is set to the watchdog timer. The dummy data is not retained anywhere. 6: The value "FFF16" is set to the watchdog timer. (Refer to "CHAPTER 15. WATCHDOG TIMER.") 7: It is possible to read the bit state at reading. When writing "0" to this bit, this bit becomes "0." But when writing "1" to this bit, this bit does not change. Fig. 4.1.7 State of SFR and internal RAM areas immediately after reset (4) 4-8 7721 Group User's Manual RESET 4.1 Hardware reset Address 1FC016 1FC116 1FC216 1FC316 1FC416 1FC516 1FC616 1FC716 1FC816 1FC916 1FCA16 1FCB16 1FCC16 1FCD16 1FCE16 1FCF16 1FD016 1FD116 1FD216 1FD316 1FD416 1FD516 1FD616 1FD716 1FD816 1FD916 1FDA16 1FDB16 1FDC16 1FDD16 1FDE16 1FDF16 Register name b7 Access characteristics RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW b0 b7 State immediately after reset ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 0 ? 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 0 ? 0 0 0 0 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b0 Source address register 0 Destination address register 0 Transfer counter register 0 DMA0 mode register L DMA0 mode register H DMA0 control register 0 0 0 Source address register 1 Destination address register 1 Transfer counter register 1 DMA1 mode register L DMA1 mode register H DMA1 control register 0 0 0 Fig. 4.1.8 State of SFR and internal RAM areas immediately after reset (5) 7721 Group User's Manual 4-9 RESET 4.1 Hardware reset Address 1FE016 1FE116 1FE216 1FE316 1FE416 1FE516 1FE616 1FE716 1FE816 1FE916 1FEA16 1FEB16 1FEC16 1FED16 1FEE16 1FEF16 1FF016 1FF116 1FF216 1FF316 1FF416 1FF516 1FF616 1FF716 1FF816 1FF916 1FFA16 1FFB16 1FFC16 1FFD16 1FFE16 1FFF16 Register name b7 Access characteristics RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW b0 b7 State immediately after reset ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 0 ? 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 0 ? 0 0 0 0 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b0 Source address register 2 Destination address register 2 Transfer counter register 2 DMA2 mode register L DMA2 mode register H DMA2 control register 0 0 0 Source address register 3 Destination address register 3 Transfer counter register 3 DMA3 mode register L DMA3 mode register H DMA3 control register 0 0 0 qInternal RAM area (addresses 8016 to 27F16) *At hardware reset (Except the case where Stop or Wait mode is terminated)............................................... Undefined. *At software reset.............................................................. Retains the state immediately before reset *At termination of Stop or Wait mode (Hardware reset is used to terminate it.)............... Retains the state immediately before the STP or WIT instruction is executed V For the M37721S2BFP, the internal RAM area can be assigned to addresses 8016 to 47F16 by setting the internal RAM area select bit (bit 1 at address 5F16). (Refer to section "2.4 Memory assignment.") V Fig. 4.1.9 State of SFR and internal RAM areas immediately after reset (6) 4-10 7721 Group User's Manual RESET 4.1 Hardware reset 4.1.3 Internal processing sequence after reset Figure 4.1.10 shows the internal processing sequence after reset. qExternal bus width = 16 bits (BYTE = "L") CPU A0-A7 A8/D8-A15/D15 A16/D0-A23/D7 E "H" 0016 FE16 ADL 0016 0016 FF16 (ADH) ADH (Next op-code or operand) 0016 0016 0016 (ADL) 0016 (Next op-code) R/W ALE qExternal bus width = 8 bits (BYTE = "H") CPU A0-A7 A8-A15 A16/D0-A23/D7 E "H" 0016 FE16 FF16 ADL 0016 0016 FF16 FF16 ADH 0016 0016 (ADL) 0016 ( ADH) 0016 (Next op-code) R/W ALE Fig. 4.1.10 Internal processing sequence after reset 7721 Group User's Manual 4-11 RESET 4.1 Hardware reset ______ 4.1.4 Time supplying "L" level to RESET pin ______ Time supplying "L" level to the RESET pin varies according to the state of the clock oscillation circuit. qWhen the oscillator is stably oscillating or a stable clock is input from the XIN pin, supply "L" level for 2 s or more. qWhen the oscillator is not stably oscillating (including the case at power-on reset or in Stop mode), supply "L" level until the oscillation is stabilized. The time required for stabilizing oscillation varies according to the oscillator. For details, contact the oscillator manufacturer. Figure 4.1.11 shows the power-on reset conditions. Figure 4.1.12 shows an example of a power-on reset circuit. V For details about Stop mode, refer to section "5.3 Stop mode." For details about clocks, refer to "CHAPTER 5. CLOCK GENERATING CIRCUIT." Powered on here 4.5V Vcc 0V RESET 0.9V 0V Fig. 4.1.11 Power-on reset conditions 5V M37721 1 M51957AL Vcc 27 k 2 10 k IN OUT 5 47 Vss Cd SW RESET Vcc Delay 4 capacity GND 3 GND V The delay time is about 11 ms when Cd = 0.033 F. td 0.34 ! Cd [ s], Cd: [ pF ] Fig. 4.1.12 Example of power-on reset circuit 4-12 7721 Group User's Manual RESET 4.2 Software reset 4.2 Software reset When the power source voltage satisfies the microcomputer's recommended operating conditions, the microcomputer is reset by writing "1" to the software reset bit (bit 3 at address 5E16). (This is called " Software reset.") In this case, the microcomputer initializes pins, CPU, and SFR area just as in the case of a hardware reset. However, the microcomputer retains the contents of the internal RAM area. (Refer to "Table 4.1.1" and "Figures 4.1.3 to 4.1.9.") Figure 4.2.1 shows the structure of the processor mode register 0 (address 5E16). After completing initialization, the microcomputer performs "internal processing sequence after reset." (Refer to "Figure 4.1.10.") After that, it executes a program beginning from the address set into the reset vector addresses (FFFE16 and FFFF16). b7 b6 b5 b4 b3 b2 b1 b0 0 0 Processor mode register 0 (Address 5E16) Bit 0 1 2 Bit name Fix this bit to "0" Nothing is assigned. This bit is "1" at reading. Wait bit Functions At reset RW RW 0 1 0 : Software Wait is inserted when accessing external area. 1 : No software Wait is inserted i when accessing external area. The microcomputer is reset by writing "1" to this bit. The value of this bit is "0" at reading. b5 b4 0 RW 3 Software reset bit 0 WO 4 5 6 7 Interrupt priority detection time select bits 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : Do not select. 0 0 0 RW RW RW RW Fix this bit to " 0" Stack bank select bit 0 : Bank 016 1 : Bank FF16 0 : Bits 0 to 2 and bits 4 to 7 are not used for software reset. Fig. 4.2.1 Structure of processor mode register 0 7721 Group User's Manual 4-13 RESET 4.2 Software reset ________ When the software reset bit is set to "1," the RESETOUT pin's output level becomes "L." In a period of 4.5 ________ cycles of clock 1________ software reset bit is set to "1," the RESETOUT pin's output level is "L." Figure after the 4.2.2 shows the RESETOUT output timing at software reset. Set software reset bit to "1" 1 E RESETOUT ________ Fig. 4.2.2 RESETOUT output timing 4-14 7721 Group User's Manual CHAPTER 5 CLOCK GENERATING CIRCUIT 5.1 Oscillation circuit examples 5.2 Clocks 5.3 Stop mode [Precautions for Stop mode] 5.4 Wait mode [Precautions for Wait mode] CLOCK GENERATING CIRCUIT 5.1 Oscillation circuit examples 5.1 Oscillation circuit examples To the oscillation circuit, a ceramic resonator or a quartz-crystal oscillator can be connected, or the clock which is externally generated can be input. Oscillation circuit examples are shown below. 5.1.1 Connection example using resonator/oscillator Figure 5.1.1 shows an example when connecting a ceramic resonator/quartz-crystal oscillator between pins XIN and XOUT. The circuit constants such as Rf, Rd, CIN, and COUT (shown in "Figure 5.1.1") depend on the resonator/ oscillator. These values shall be set to the values recommended by the resonator/oscillator manufacturer. 5.1.2 Externally generated clock input example Figure 5.1.2 shows an input example of the clock which is externally generated. The external clock must be input from the XIN pin, and the XOUT pin must be left open. M37721 XIN XOUT Rf Rd CIN COUT Fig. 5.1.1 Connection example using resonator/oscillator M37721 XIN XOUT Open Externally generated clock Vcc Vss Fig. 5.1.2 Externally generated clock input example 5-2 7721 Group User's Manual CLOCK GENERATING CIRCUIT 5.2 Clocks 5.2 Clocks Figure 5.2.1 shows the clock generating circuit block diagram. f2 XIN XOUT 1/2 1 f16 f64 1/8 1/2 1/2 1/8 f512 f512 "0" Operation clock for internal peripheral devices Interrupt request S Q Watchdog timer frequency select bit Watchdog timer STP instruction R f32 "1" Q S WIT instruction R (Note) Ready request Reset S Q CPU wait request from BIU Bus request DRAMC Hold DMAC CPU R CPU : Central Processing Unit BIU : Bus Interface Unit Watchdog timer frequency select bit : Bit 0 at address 6116 Note: This signal is generated when the watchdog timer's most significant bit becomes "0." Fig. 5.2.1 Clock generating circuit block diagram 7721 Group User's Manual 5-3 CLOCK GENERATING CIRCUIT 5.2 Clocks 5.2.1 Clocks generated in clock generating circuit (1) It is the operation clock of BIU. It is also the clock source of CPU. stops by acceptance of Ready request or execution of the STP or WIT instruction. It is not stopped by acceptance of bus request. (2) CPU It is the operation clock of CPU. CPU stops by the following: *Execution of the STP or WIT instruction, ____ *Acceptance of Ready request; "L" level input to the RDY pin *CPU wait request from BIU; Acceptance of bus request is included. (3) Clock 1 It has the same period as and is output to the external from the 1 pin. Clock 1 stops by execution of the STP instruction. It is not stopped by acceptance of Ready or bus request, or execution of the WIT instruction. (4) f2 to f512 Each of them is the internal peripheral devices' operation clock. Note: Refer to each functional description for details: *Execution of STP instruction ............. "5.3 Stop mode" *Execution of WIT instruction .............. "5.4 Wait mode" *Ready ..................................................... "3.3 Ready function" *Bus request ........................................... "13.2.1 Bus access control circuit" 5-4 7721 Group User's Manual CLOCK GENERATING CIRCUIT 5.3 Stop mode 5.3 Stop mode Stop mode is used to stop oscillation when there is no need to operate the central processing unit (CPU). The microcomputer enters Stop mode when the STP instruction is executed. Stop mode can be terminated by an interrupt request occurrence or the hardware reset. 5.3.1 Stop mode When the STP instruction is executed, the oscillator stops oscillating. This state is called "Stop mode." In Stop mode, the contents of the internal RAM can be retained intact when Vcc (power source voltage) is 2 V or more. Additionally, the microcomputer's power consumption is lowered. It is because the CPU and all internal peripheral devices using clocks f2 to f512 stop the operation. Table 5.3.1 lists the microcomputer's state and operation in and after Stop mode. Table 5.3.1 Microcomputer's state and operation in and after Stop mode Item State in Stop mode Oscillation State and Operation Stopped CPU, Clock 1, f2 to f512 Can operate only in event counter mode Timers A, B Can operate only when an external clock is selected Serial I/O A-D converter Stopped DMA controller Stopped (Note) DRAM controller Stopped Watchdog timer Retains the same state in which the STP instruction was executed Pins Operation By interrupt request Supply of CPU and starts after a certain time measured by after terminating occurrence Watchdog timer has passed. Stop mode By hardware reset Operates in the same way as hardware reset Note: DRAM refresh is not performed because the refresh timer also stops. Internal peripheral devices 7721 Group User's Manual 5-5 CLOCK GENERATING CIRCUIT 5.3 Stop mode (1) Termination by interrupt request occurrence When terminating Stop mode by interrupt request occurrence, instructions are executed after a certain time measured by the watchdog timer has passed. When an interrupt request occurs, the oscillator starts oscillating. Simultaneously, supply of clock 1, f2 to f512 starts. The watchdog timer starts counting owing to the oscillation start. The watchdog timer counts f32 regardless of the watchdog timer frequency select bit's (bit 0 at address 6116) contents. When the watchdog timer's MSB becomes "0," supply of CPU and starts. At the same time, the watchdog timer's count source returns to f32 or f512 that is selected by the watchdog timer frequency select bit. The interrupt request which occurred in is accepted. Table 5.3.2 lists the interrupts used to terminate Stop mode. Table 5.3.2 Interrupts used to terminate Stop mode Interrupt Conditions for using each function to generate interrupt request ____ INTi interrupt (i = 0 to 2) Timer Ai interrupt (i = 2 to 4) Timer Bi interrupt (i = 0, 1) UARTi transmit interrupt (i = 0, 1) UARTi receive interrupt (i = 0, 1) In event counter mode When external clock is selected Notes 1: Since the oscillator has stopped oscillating, interrupts not listed above cannot be used. Also, even the interrupts listed above cannot be used when the above conditions are not satisfied. The A-D converter does not operate, also. 2: When multiple interrupts listed above are enabled, Stop mode is terminated by the interrupt request which occurs first. 3: Refer to "CHAPTER 7. INTERRUPTS" and the description of each internal peripheral device for details about each interrupt. Before executing the STP instruction, interrupts used to terminate Stop mode must be enabled. In addition, the interrupt priority level of the interrupt used to terminate Stop mode must be higher than the processor interrupt priority level (IPL) of the routine where the STP instruction is executed. When multiple interrupts in Table 5.3.2 are enabled, Stop mode is terminated by the first interrupt request. There is a possibility that any of all interrupt requests occurs after the oscillation starts in and until supply of CPU and starts in . The interrupt requests which occur during this period are accepted in order of priority after the watchdog timer's MSB becomes "0." For interrupts not to be accepted, set their interrupt priority levels to level 0 (interrupt disabled) before executing the STP instruction. 5-6 7721 Group User's Manual CLOCK GENERATING CIRCUIT 5.3 Stop mode Stop mode f(XIN) 1 CPU, Interrupt request used to terminate Stop mode (Interrupt request bit) f32 ! 2048 counts "FFF16" Value of Watchdog timer "7FF16" CPU Internal peripheral devices Operating Operating Stopped Stopped Stopped Operating Operating Operating qSTP instruction is executed qInterrupt request used to terminate Stop mode occurs. qOscillation starts.(When an external clock is input from the XIN pin, clock input starts.) qWatchdog timer starts counting. qWatchdog timer's MSB = "0" (However, watchdog timer interrupt request does not occur.) qSupply of CPU, starts. qInterrupt request which has been used to terminate Stop mode is accepted. Fig. 5.3.1 Stop mode terminating sequence by interrupt request occurrence (2) Termination by hardware reset ______ Supply "L" level to the RESET pin by using the external circuit until the oscillation of the oscillator is stabilized. The CPU and the SFR area are initialized in the same way as system reset. However, the internal RAM area retains the same contents as that before executing the STP instruction. The terminating sequence is the same as the internal processing sequence which is performed after reset. Refer to "CHAPTER 4. RESET" for details about reset. 7721 Group User's Manual 5-7 CLOCK GENERATING CIRCUIT 5.3 Stop mode [Precautions for Stop mode] When executing the STP instruction after writing to an internal area or an external area, three NOP instructions must be inserted to complete the write operation before the STP instruction is executed. (Refer to "Figure 5.3.2.") STA A, !!!! ; Write instruction NOP ; NOP instruction inserted NOP ; NOP ; STP ; STP instruction Fig. 5.3.2 NOP instruction insertion example 5-8 7721 Group User's Manual CLOCK GENERATING CIRCUIT 5.4 Wait mode 5.4 Wait mode Wait mode is used to stop CPU and when there is no need to operate the central processing unit (CPU). The microcomputer enters Wait mode when the WIT instruction is executed. Wait mode can be terminated by an interrupt request occurrence or the hardware reset. 5.4.1 Wait mode When the WIT instruction is executed, CPU and stop. The oscillator's oscillation is not stopped. This state is called "Wait mode." In Wait mode, the microcomputer's power consumption is lowered though Vcc (power source voltage) is maintained. Table 5.4.1 lists the microcomputer's state and operation in and after Wait mode. Table 5.4.1 Microcomputer's state and operation in and after Wait mode Item State and Operation State in Operating Oscillation Stopped Wait mode CPU, Operating Clock 1, f2 to f512 Internal peripheral devices Timer A Timer B Serial I/O A-D converter DMA controller Operating Stopped Stopped (Note) DRAM controller Operating Watchdog timer Retains the same state in which the WIT instruction was executed Pins Operation after By interrupt request occurrence Supply of CPU and starts just after the termination. terminating Operates in the same way as hardware reset. By hardware reset Wait mode Note: The refresh timer operates, but DRAM refresh is not performed because the bus request (DRAMC) does not occur. (Refer to section "Appendix 9. 7721 Group Q & A.") 7721 Group User's Manual 5-9 CLOCK GENERATING CIRCUIT 5.4 Wait mode (1) Termination by interrupt request occurrence When an interrupt request occurs, supply of CPU and starts. The interrupt request which occurred in is accepted. The following interrupts are used to terminate Wait mode. When a watchdog timer interrupt request occurs, Wait mode is also terminated. ___ *INTi interrupt (i = 0 to 2) *Timer Ai interrupt (i = 0 to 4) *Timer Bi interrupt (i = 0 to 2) *UARTi transmit interrupt (i = 0, 1) *UARTi receive interrupt (i = 0, 1) *A-D converter interrupt Note: Refer to "CHAPTER 7. INTERRUPTS" and each functional description about interrupts. Before executing the WIT instruction, interrupts used to terminate Wait mode must be enabled. In addition, the interrupt priority level of the interrupt used to terminate Wait mode must be higher than the processor interrupt priority level (IPL) of the routine where the WIT instruction is executed. When multiple interrupts listed above are enabled, Wait mode is terminated by the interrupt request which occurs first. (2) Termination by hardware reset The CPU and the SFR area are initialized in the same way as system reset. However, the internal RAM area retains the same contents as that before executing the WIT instruction. The terminating sequence is the same as the internal processing sequence which is performed after reset. Refer to "CHAPTER 4. RESET" for details about reset. 5-10 7721 Group User's Manual CLOCK GENERATING CIRCUIT 5.4 Wait mode [Precautions for Wait mode] When executing the WIT instruction after writing to an internal area or an external area, three NOP instructions must be inserted to complete the write operation before the WIT instruction is executed. (Refer to "Figure 5.4.1.") STA A, !!!! ; Write instruction NOP ; NOP instruction inserted NOP ; NOP ; WIT ; WIT instruction Fig. 5.4.1 NOP instruction insertion example 7721 Group User's Manual 5-11 CLOCK GENERATING CIRCUIT 5.4 Wait mode MEMORANDUM 5-12 7721 Group User's Manual CHAPTER 6 INPUT/OUTPUT PINS 6.1 Overview 6.2 Programmable I/O ports 6.3 Examples of handling unused pins INPUT/OUTPUT PINS 6.1 Overview, 6.2 Programmable I/O ports 6.1 Overview Input/output pins (hereafter called I/O pins) have functions as programmable I/O ports, internal peripheral devices's I/O pins, external buses, etc. For the basic functions of each I/O pin, refer to section "1.3 Pin description." For the I/O functions of the internal peripheral devices, refer to relevant sections of each internal peripheral device. For the external address bus, external data bus, bus control signals, etc., refer to "CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES." This chapter describes the programmable I/O ports and examples of handling unused pins. 6.2 Programmable I/O ports The programmable I/O ports have direction registers and port registers in the SFR area. Figure 6.2.1 shows the memory map of direction registers and port registers. Addresses A16 B16 C16 D16 E16 F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 Port P10 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P9 register Port P8 direction register Port P9 direction register Port P10 register Fig. 6.2.1 Memory map of direction registers and port registers 6-2 7721 Group User's Manual INPUT/OUTPUT PINS 6.2 Programmable I/O ports 6.2.1 Direction register This register determines the I/O direction of programmable I/O ports. Each bit of this register corresponds one for one to each pin of the microcomputer. Figure 6.2.2 shows the structure of port Pi (i = 4 to 10) direction register. b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (i = 4 to 10) (Addresses C16, D16, 1016, 1116, 1416, 1516, 1816) Bit 0 1 2 3 4 5 6 7 Bit name Port Pi0 direction bit Port Pi1 direction bit Port Pi2 direction bit Port Pi3 direction bit Port Pi4 direction bit Port Pi5 direction bit Port Pi6 direction bit Port Pi7 direction bit Functions 0 : Input mode (The port functions as an input port) 1 : Output mode (The port functions as an output port) At reset RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Note: For bits 0 to 2 of the port P4 direction register, nothing is assigned and these bits are fixed to "0" at reading. Fig. 6.2.2 Structure of port Pi (i = 4 to 10) direction register 7721 Group User's Manual 6-3 INPUT/OUTPUT PINS 6.2 Programmable I/O ports 6.2.2 Port register Data is input from or output to the external by writing/reading data to/from a port register. A port register consists of a port latch which holds the output data and a circuit which reads the pin state. Each bit of the port register corresponds one for one to each pin of the microcomputer. Figure 6.2.3 shows the structure of the port Pi (i = 4 to 10) register. q When outputting data from programmable I/O port set to output mode By writing data to the corresponding bit of the port register, the data is written into the port latch. The data is output from the pin according to the contents of the port latch. By reading the port register of a port set to the output mode, the contents of the port latch is read out, instead of the pin state. Accordingly, the output data is correctly read without being affected by an external load, etc. (Refer to "Figures 6.2.4 and 6.2.5.") q When inputting data from programmable I/O port set to input mode A pin which is set to the input mode enters the floating state. By reading the corresponding bit of the port register, the data which is input from the pin can be read out. By writing data to the port register of a programmable I/O port set to the input mode, the data is written only into the port latch and is not output to the external (Note). The pin remains floating. Note: When executing a read-modify-write instruction (CLB, SEB, INC, DEC, ASL, ASR, LSR, ROL, ROR) to the port register of a programmable I/O port set to the input mode, the instruction is executed to the data which is input from the pin and the result is written into the port register. b7 b6 b5 b4 b3 b2 b1 b0 Port Pi register (i = 4 to 10) (Addresses A16, B16, E16, F16, 1216, 1316, 1616) Bit 0 1 2 3 4 5 6 7 Bit name Port Pi0's pin Port Pi1's pin Port Pi2's pin Port Pi3's pin Port Pi4's pin Port Pi5's pin Port Pi6's pin Port Pi7's pin Functions Data is input from or output to a pin by reading from or writing to the corresponding bit. 0 : "L" level 1 : "H" level At reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined RW RW RW RW RW RW RW RW RW Note: For bits 0 to 2 of the port P4 register, nothing is assigned and these bits are fixed to "0" at reading. Fig. 6.2.3 Structure of port Pi (i = 4 to 10) register 6-4 7721 Group User's Manual INPUT/OUTPUT PINS 6.2 Programmable I/O ports Figures 6.2.4 and 6.2.5 show the port peripheral circuits. [Inside dotted-line not included] Ports P43 to P46 Direction register Data bus [Inside dotted-line included] Ports P47, P51/TA2 IN, P53/TA3IN, P55/TA4IN, P56/TB0IN, P57/TB1IN, P82/RxD0, P86/RxD1, P91/DMAREQ0, P93/DMAREQ1, P95/DMAREQ2, P97/DMAREQ3, P100/INT0, P101/INT1, P102/INT2, (There is no hysteresis for P82/RxD0 and P86/RxD1.) Port latch [Inside dotted-line not included] Ports P83/TxD0, P87/TxD1, P90/DMAACK0, P92/DMAACK1, P94/DMAACK2, P96/DMAACK3, P104/CAS, P105/RAS, P106/MA8, P107/MA9 [Inside dotted-line included] Ports P50/TA2OUT, P52/TA3OUT, P54/TA4OUT Direction register "1" (internal peripheral device) Output Data bus Port latch Ports P60/RTP00 to P67/RTP13 Direction register Data bus Port latch Latch Timer underflow signal T Q CK Fig. 6.2.4 Port peripheral circuits (1) 7721 Group User's Manual 6-5 INPUT/OUTPUT PINS 6.2 Programmable I/O ports [Inside dotted-line not included] Ports P70/AN0 to P76/AN6 [Inside dotted-line included] Port P77/AN7/ADTRG Data bus Port latch Direction register Analog input Ports P80/CTS0/RTS0, P81/CLK0, P84/CTS1/RTS1, P85/CLK1 "0" "1" Direction register Data bus Port latch (internal peripheral device) Output Port P103/TC Direction register "0" Data bus Port latch Output (TC) E output pin Fig. 6.2.5 Port peripheral circuits (2) 6-6 7721 Group User's Manual INPUT/OUTPUT PINS 6.3 Examples of handling unused pins 6.3 Examples of handling unused pins When unusing an I/O pin, some handling is necessary for the pin. Examples of handling unused pins are described below. The following are just examples. The user shall modify them according to the user's actual application and test them. Table 6.3.1 Examples of handling unused pins Pin name P43 to P47, P5 to P10 Handling example Set these pins to the input mode and connect each pin to Vcc or Vss via a resistor; or set these pins to the output mode and leave them open (Notes 1 and 2). Leave them open. Connect these pins to Vcc via a resistor (pull-up) (Note 2). Connect this pin to Vcc or Vss. Connect this pin to Vcc. Connect these pins to Vss. BLE, BHE, ALE, 1, ST0, ST1 XOUT (Note 3) _____ ____ ___ ___ HOLD, RDY CNVss AVcc AVss, VREF Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. After reset, immediately set these ports to the output mode. Software reliability can be enhanced by setting the contents of the above ports' direction registers periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 3: This applies when a clock externally generated is input to the XIN pin. q When setting ports to input mode q When setting ports to output mode P43-P47, P5-P10 ST0 ST1 BLE BHE ALE 1 P43-P47, P5-P10 ST0 ST1 BLE BHE ALE Left open Left open Left open M37721 Fig. 6.3.1 Examples of handling unused pins M37721 1 XOUT Left open VCC XOUT Left open VCC HOLD RDY AVCC CNVSSV AVSS VREF VSS HOLD RDY AVCC CNVSSV AVSS VREF VSS V CNVSS can be connected to VCC, too. 7721 Group User's Manual 6-7 INPUT/OUTPUT PINS 6.3 Examples of handling unused pins MEMORANDUM 6-8 7721 Group User's Manual CHAPTER 7 INTERRUPTS 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Overview Interrupt sources Interrupt control Interrupt priority level Interrupt priority level detection circuit Interrupt priority level detection time Sequence from acceptance of interrupt request until execution of interrupt routine 7.8 Return from interrupt routine 7.9 Multiple interrupts ____ 7.10 External interrupts (INTi interrupt) 7.11 Precautions for interrupts INTERRUPTS 7.1 Overview 7.1 Overview The M37721 provides 23 interrupt sources to generate interrupt requests. Figure 7.1.1 shows the interrupt processing sequence. When an interrupt request is accepted, a branch is made to the start address of the interrupt routine set in the interrupt vector table (addresses FFCE16 to FFFF16). Set the start address of each interrupt routine to the corresponding interrupt vector address in the interrupt vector table. Routine in progress d t ad star e. s to outin r che ran errupt B nt of i ress Interrupt routine Interrupt processing Interrupt request is accepted. Processing is suspended. Processing is resumed. Retu rns t o ori ginal routi ne. RTI instruction Fig. 7.1.1 Interrupt processing sequence 7-2 7721 Group User's Manual INTERRUPTS 7.1 Overview When an interrupt request is accepted, the following registers' contents just before acceptance of an interrupt request are automatically pushed onto the stack area in that order. Program bank register (PG) Program counter (PCL, PCH) Processor status register (PSL, PSH) Figure 7.1.2 shows the state of the stack area just before entering the interrupt routine. Execute the RTI instruction at the end of this interrupt routine to return to the routine that the microcomputer was executing before the interrupt request was accepted. By executing the RTI instruction, the register contents pushed onto the stack area are pulled in that order. Then, the suspended processing is resumed from where it left off. Stack area Address [S] - 5 [S] - 4 Processor status register's low-order byte (PSL) [S] - 3 Processor status register's high-order byte (PSH) [S] - 2 [S] - 1 [S]V Program counter's low-order byte (PCL) Program counter's high-order byte (PCH) Program bank register (PG) V [S] is an initial address that the stack pointer (S) indicates when an interrupt request is accepted. The S's contents become "[S] - 5" after all of the above registers are pushed. Fig. 7.1.2 State of stack area just before entering interrupt routine 7721 Group User's Manual 7-3 INTERRUPTS 7.2 Interrupt sources 7.2 Interrupt sources Table 7.2.1 lists the interrupt sources and the interrupt vector addresses. When programming, set the start address of each interrupt routine at the vector addresses listed in this table. Table 7.2.1 Interrupt sources and interrupt vector addresses Remarks Interrupt source Interrupt vector addresses High-order address Reset Zero division ____ Reference Low-order address FFFE16 FFFC16 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16 FFDA16 FFD816 FFD616 FFD416 FFD216 FFD016 FFCE16 Maskable internal interrupt 12. A-D CONVERTER Maskable internal interrupts 13. DMA CONTROLLER Maskable internal interrupts 11. SERIAL I/O Maskable internal interrupts 9. TIMER B Maskable internal interrupts 8. TIMER A 4. RESET Non-maskable software interrupt 7700 Family Software Non-maskable software interrupt Manual Do not use. Non-maskable interrupt 15. WATCHDOG TIMER Maskable external interrupts 7.10 External interrupts ____ FFFF16 FFFD16 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16 FFDB16 FFD916 FFD716 FFD516 FFD316 FFD116 FFCF16 Non-maskable BRK instruction DBC (Note) ____ Watchdog timer INT1 INT2 INT0 ____ ____ (INTi interrupt) Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 UART0 receive UART0 transmit UART1 receive UART1 transmit A-D conversion DMA0 DMA1 DMA2 DMA3 ____ Note: The DBC interrupt is used exclusively for debugger control. qMaskable interrupt: An interrupt of which request's acceptance can be disabled by software. qNon-maskable interrupt (including Zero division, BRK instruction, Watchdog timer interrupts): An interrupt which is certain to be accepted when its request occurs. These interrupts do not have their interrupt control registers and are not affected by the interrupt disable flag (I). 7-4 7721 Group User's Manual INTERRUPTS 7.3 Interrupt control 7.3 Interrupt control The maskable interrupts are controlled by the following : *Interrupt request bit Assigned to the interrupt control register of each interrupt. *Interrupt priority level select bits *Processor interrupt priority level (IPL) Assigned to the processor status register (PS). *Interrupt disable flag (I) } } Figure 7.3.1 shows the memory assignment of the interrupt control registers, and Figure 7.3.2 shows their structures. Address 6C16 6D16 6E16 6F16 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C16 7D16 7E16 7F16 DMA0 interrupt control register DMA1 interrupt control register DMA2 interrupt control register DMA3 interrupt control register A-D conversion interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register Fig. 7.3.1 Memory assignment of interrupt control registers 7721 Group User's Manual 7-5 INTERRUPTS 7.3 Interrupt control b7 b6 b5 b4 b3 b2 b1 b0 DMA0 to DMA3, A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2 interrupt control registers (Addresses 6C16 to 7C16) Bit 0 Bit name Interrupt priority level select bits b2 b1 b0 Functions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested At reset RW RW 0 1 0 RW 2 0 RW 3 Interrupt request bit 0 Undefined RW 7 to 4 Nothing is assigned. - b7 b6 b5 b4 b3 b2 b1 b0 INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16) Bit 0 Bit name Interrupt priority level select bits b2 b1 b0 Functions 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 : : : : : : : : Level Level Level Level Level Level Level Level 0 (Interrupt disabled) 1 2 3 4 5 6 7 At reset RW RW 0 1 0 RW 2 0 RW 3 4 Interrupt request bit (Note) 0 : No interrupt requested 1 : Interrupt requested 0 : Interrupt request bit is set to "1" at "H" level when level sense is selected; this bit is set to "1" at falling edge when edge sense is selected. 1 : Interrupt request bit is set to "1" at "L" level when level sense is selected; this bit is set to "1" at rising edge when edge sense is selected. 0 0 RW RW Polarity select bit 5 7, 6 Level sense/Edge sense select bit Nothing is assigned. 0 : Edge sense 1 : Level sense 0 Undefined RW - Note: The interrupt request bits of INT0 to INT2 interrupts are invalid when the level sense is selected. Fig. 7.3.2 Structures of interrupt control register 7-6 7721 Group User's Manual INTERRUPTS 7.3 Interrupt control 7.3.1 Interrupt disable flag (I) All maskable interrupts can be disabled by this flag. When this flag is set to "1," all maskable interrupts are disabled; when this flag is cleared to "0," those interrupts are enabled. Because this flag is set to "1" at reset, clear this flag to "0" when enabling interrupts. 7.3.2 Interrupt request bit When an interrupt request occurs, this bit is set to "1." This bit remains set to "1" until the interrupt request is accepted; it is cleared to "0" when the interrupt request is accepted. This ____ bit can also be set to "0" or "1" by software. ____ The INTi interrupt request bit (i = 0 to 2) is ignored when the INTi interrupt is used with level sense. 7.3.3 Interrupt priority level select bits and processor interrupt priority level (IPL) The interrupt priority level select bits are used to determine the priority level of each interrupt. When an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when the comparison result meets the following condition. Accordingly, an interrupt can be disabled by setting its interrupt priority level to 0. Each interrupt priority level > Processor interrupt priority level (IPL) Table 7.3.1 lists the setting of interrupt priority level, and Table 7.3.2 lists the interrupt enabled level corresponding to IPL contents. The interrupt disable flag (I), interrupt request bit, interrupt priority level select bits, and processor interrupt priority level (IPL) are independent of one another; they do not affect one another. Interrupt requests are accepted only when the following conditions are satisfied. *Interrupt disable flag (I) = "0" *Interrupt request bit = "1" *Interrupt priority level > Processor interrupt priority level (IPL) 7721 Group User's Manual 7-7 INTERRUPTS 7.3 Interrupt control Table 7.3.1 Setting of interrupt priority level Interrupt priority level select bits b0 b1 b2 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 Interrupt priority level Level 0 (Interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High Priority -- Low Table 7.3.2 Interrupt enabled level corresponding to IPL contents IPL2 0 0 0 0 1 1 1 1 IPL1 0 0 1 1 0 0 1 1 IPL0 0 1 0 1 0 1 0 1 Enabled interrupt priority level Enable level 1 and above interrupts. Enable level 2 and above interrupts. Enable level 3 and above interrupts. Enable level 4 and above interrupts. Enable level 5 and above interrupts. Enable level 6 and level 7 interrupts. Enable only level 7 interrupt. Disable all maskable interrupts. IPL0: Bit 8 in processor status register (PS) IPL1: Bit 9 in processor status register (PS) IPL2: Bit 10 in processor status register (PS) 7-8 7721 Group User's Manual INTERRUPTS 7.4 Interrupt priority level 7.4 Interrupt priority level When the interrupt disable flag (I) = "0" (interrupts enabled) and more than one interrupt request is detected at the same sampling timing, which means a timing to check whether an interrupt request exists or not, they are accepted in order of priority levels. In other words, the interrupt request with the highest priority level is accepted first. Among a total of 23 interrupt sources, the user can set the desired priority levels for 20 interrupt sources except software interrupts (zero division and BRK instruction interrupts) and the watchdog timer interrupt. Use the interrupt priority level select bits to set their priority levels. Priority levels of reset, which is handled as the interrupt request with the highest priority, and the watchdog timer interrupt are set by hardware. Figure 7.4.1 shows the interrupt priority set by hardware. Note that software interrupts are not affected by the interrupt priority levels. Whenever the instruction is executed, a program certainly branches to the interrupt routine. Reset Watchdog timer ****************** 20 interrupt sources except software interrupts and watchdog timer interrupt Priority levels determined by hardware The user can set the desired priority levels inside of the dotted line. Low Priority level High Fig. 7.4.1 Interrupt priority level set by hardware 7721 Group User's Manual 7-9 INTERRUPTS 7.5 Interrupt priority level detection circuit 7.5 Interrupt priority level detection circuit The interrupt priority level detection circuit selects the interrupt with the highest priority level when more than one interrupt request occurs at the same sampling timing. Figure 7.5.1 shows the interrupt priority level detection circuit. Interrupt priority level DMA3 Level 0 (initial value) DMA2 DMA1 DMA0 Interrupt priority level A-D conversion Timer A4 UART1 transmit Timer A3 UART1 receive Timer A2 UART0 transmit Timer A1 UART0 receive Timer A0 Timer B2 INT2 Timer B1 INT1 Timer B0 INT0 Interrupt with the highest priority level IPL Processor interrupt priority level Interrupt disable flag (I) Watchdog timer interrupt Reset Accepting of interrupt request Fig. 7.5.1 Interrupt priority level detection circuit 7-10 7721 Group User's Manual INTERRUPTS 7.5 Interrupt priority level detection circuit The following explains the operation of the interrupt priority detection circuit using Figure 7.5.2. The interrupt priority level of a requested interrupt (Y in Figure 7.5.2) is compared with the resultant priority level which is sent from the preceding comparator (X in Figure 7.5.2); the interrupt with the higher priority level is sent to the next comparator (Z in Figure 7.5.2). (Initial comparison value of "X" is "0.") For an interrupt which is not requested, the comparison is not performed and the priority level which is sent from the preceding comparator is forwarded to the next comparator as it is. When the two priority levels are found the same by comparison, the priority level which is sent from the preceding comparator is forwarded to the next comparator. Accordingly, when the same priority level is set by software, the interrupt priority levels are handled as follows: DMA3 > DMA2 > DMA1 > DMA0 > A-D conversion > UART1 transmit > UART1 receive > UART0 transmit > UART0 receive > Timer B2 > Timer B1 > Timer B0 > Timer A4 > Timer A3 > Timer A2 > Timer A1 > Timer ____ ____ ____ A0 > INT2 > INT1 > INT0 Among the multiple interrupt requests sampled at the same time, one request with the highest priority level is detected by the above comparison. Then, this highest interrupt priority level is compared with the processor interrupt priority level (IPL). When this interrupt priority level is higher than the processor interrupt priority level (IPL) and the interrupt disable flag (I) is "0," the interrupt request is accepted. A interrupt request which is not accepted here is held until it is accepted or its interrupt request bit is cleared to "0" by software. The interrupt priority is detected when the CPU fetches an op code, which is called the CPU's op-code fetch cycle. However, when an op-code fetch cycle starts during detection of an interrupt priority, a new interrupt priority detection does not start. (Refer to "Figure 7.6.1.") Since the state of the interrupt request bit and interrupt priority levels are latched during the interrupt priority detection, even if they change, the interrupt priority detection is performed for the previous state before the change occurred. The interrupt priority level is detected when the CPU fetches an op code. Therefore, in the following execution or states, after the execution or state is terminated, no interrupt request is accepted until the CPU fetches the op code of the next instruction. *Execution of an instruction which requires many cycles, such as the MVN or MVP instruction *During DRAM refreshment *During Hold state *During DMA transfer X Y Interrupt source Y Time Comparator (Priority level comparison) Z X : Priority level sent from the preceding comparator (Highest priority at this point) Y : Priority level of interrupt source Y Z : Highest priority at this point qWhen X qWhen X Y then Z = X Y then Z = Y Fig. 7.5.2 Interrupt priority level detection model 7721 Group User's Manual 7-11 INTERRUPTS 7.6 Interrupt priority level detection time 7.6 Interrupt priority level detection time When the interrupt priority level detection time has passed after sampling starts, an interrupt request is accepted. The interrupt priority level detection time can be selected by software. Figure 7.6.1 shows the interrupt priority level detection time. Usually, select "2 cycles of " as the interrupt priority level detection time. (1) Interrupt priority detection time select bits b7 b6 b5 b4 b3 b2 b1 b0 0 Processor mode register 0 (Address 5E16) Processor mode bits Wait bit Software reset bit b5, b4 Interrupt priority detection time select bits 00 01 10 11 7 cycles of 4 cycles of 2 cycles of Do not select. output select bit [(a) shown below] [(b) shown below] [(c) shown below] Must be fixed to "0." Clock 1 (2) Interrupt priority level detection time Op-code fetch cycle Sampling pulse (a) 7 cycles Interrupt priority level detection time (b) 4 cycles (c) 2 cycles Note: The pulse resides when "2 cycles of " is selected. (Note) Fig. 7.6.1 Interrupt priority level detection time 7-12 7721 Group User's Manual INTERRUPTS 7.7 Sequence from acceptance of interrupt request until execution of interrupt routine 7.7 Sequence from acceptance of interrupt request until execution of interrupt routine The sequence from the acceptance of interrupt request until the execution of the interrupt routine is described below. When an interrupt request is accepted, the interrupt request bit of the accepted interrupt is cleared to "0." And then, the interrupt processing starts from the cycle just after the completion of the instruction which was executed at accepting the interrupt request. Figure 7.7.1 shows the sequence from acceptance of interrupt request to execution of interrupt routine. After execution of an instruction at accepting the interrupt request is completed, an INTACK (Interrupt Acknowledge) sequence is executed, and a branch is made to the start address of the interrupt routine allocated in addresses 016 to FFFF16. The INTACK sequence is automatically performed in the following order. The contents of the program bank register (PG) just before performing the INTACK sequence are pushed onto stack. The contents of the program counter (PC) just before performing the INTACK sequence are pushed onto stack. The contents of the processor status register (PS) just before performing the INTACK sequence is pushed onto stack. The interrupt disable flag (I) is set to "1." The interrupt priority level of the accepted interrupt is set into the processor interrupt priority level (IPL). The contents of the program bank register (PG) are cleared to "0016," and the contents of the interrupt vector address are set into the program counter (PC). Performing the INTACK sequence requires at least 13 cycles of internal clock . Figure 7.7.2 shows the INTACK sequence timing. After the INTACK sequence is completed, the instruction execution starts from the start address of the interrupt routine. Interrupt request is accepted. Interrupt request occurs. @ Instruction Instruction 1 2 @ INTACK sequence Interrupt response time Time Instructions in interrupt routine @ : Interrupt priority level detection time Time from the occurrence of an interrupt request until the instruction execution which is in progress at that time is completed. Time from when execution of an instruction next to begins (Note) until the instruction execution which is in progress at completion of interrupt priority level detection. Note: At this time, detection of interrupt priority level begins. Time required to execute the INTACK sequence (13 cycles of at minimum) Fig. 7.7.1 Sequence from acceptance of interrupt request until execution of interrupt routine 7721 Group User's Manual 7-13 INTERRUPTS 7.7 Sequence from acceptance of interrupt request until execution of interrupt routine qWhen stack pointer (S)'s contents are even and no Wait Internal clock CPU AP PG 00 00 00 00 00 00 00 00 00 00 AH PCH 00 [S]H ([S]-1)H ([S]-2)H ([S]-3)H ([S]-4)H ([S]-5)H ([S]-5)H FF16 ADH AL PCL 00 [S]L ([S]-1)L ([S]-2)L ([S]-3)L ([S]-4)L ([S]-5)L ([S]-5)L XX16 ADL DH FF16 PCH PSH ADH Op-code DL Interrupt disable flag (I) XX16 PG PCL PSL ADL Op-code INTACK sequence CPU AP AH AL DH DL : CPU standard clock : High-order 8 bits of CPU internal address bus : Middle-order 8 bits of CPU internal address bus : Low-order 8 bits of CPU internal address bus : CPU internal data bus for odd address : CPU internal data bus for even address : Not used [S] : Contents of stack pointer (S) XX16 : Low-order 8 bits of vector address AD H : Contents of vector address (High-order address) AD L : Contents of vector address (Low-order address) Fig. 7.7.2 INTACK sequence timing (at minimum) 7.7.1 Change in IPL at acceptance of interrupt request When an interrupt request is accepted, the processor interrupt priority level (IPL) is replaced with the interrupt priority level of the accepted interrupt. This results in easy control of the processing for multiple interrupts. (Refer to section "7.9 Multiple interrupts.") At reset or when a watchdog timer interrupt or a software interrupt is accepted, a value listed in Table 7.7.1 is set into the IPL. Table 7.7.1 Change in IPL at acceptance of interrupt request Interrupts Reset Watchdog timer Zero division BRK instruction Other interrupts Level 0 ("0002") is set. Level 7 ("1112") is set. Not changed. Not changed. Accepted interrupt priority level is set. Change in IPL 7-14 7721 Group User's Manual INTERRUPTS 7.7 Sequence from acceptance of interrupt request until execution of interrupt routine 7.7.2 Push operation for registers The push operation for registers performed in the INTACK sequence depends on whether the contents of the stack pointer (S) at acceptance of an interrupt request are even or odd. When the contents of the stack pointer (S) are even, the contents of the program counter (PC) and the processor status register (PS) are simultaneously pushed in a unit of 16 bits. When the contents of the stack pointer (S) are odd, each of these registers is pushed in a unit of 8 bits. Figure 7.7.3 shows the push operation for registers. In the INTACK sequence, only the contents of the program bank register (PG), program counter (PC), and processor status register (PS) are pushed onto the stack area. The other necessary registers must be pushed by software at the start of the interrupt routine. By using the PSH instruction, all CPU registers except the stack pointer (S) can be pushed. (1) When contents of stack pointer (S) are even Address [S] - 5 (odd) Order for push Low-order byte of processor status register (PSL) High-order byte of processor status register (PSH) Low-order byte of program counter (PCL) High-order byte of program counter (PCH) [S] - 4 (even) [S] - 3 (odd) [S] - 2 (even) [S] - 1 (odd) [S] (even) Pushed in a unit of 16 bits. Pushed in a unit of 16 bits. Pushed in 3 times. Program bank register (PG) (2) When contents of stack pointer (S) are odd Address [S] - 5 (even) Order for push Low-order byte of processor status register (PSL) High-order byte of processor status register (PSH) Low-order byte of program counter (PCL) High-order byte of program counter (PCH) [S] - 4 (odd) [S] - 3 (even) [S] - 2 (odd) [S] - 1 (even) [S] (odd) Pushed in 5 times. Pushed in a unit of 8 bits. Program bank register (PG) V [S] is an initial address that the stack pointer (S) indicates when an interrupt request is accepted. The S's contents become "[S] - 5" after all of the above registers are pushed. Fig. 7.7.3 Push operation for registers 7721 Group User's Manual 7-15 INTERRUPTS 7.8 Return from interrupt routine, 7.9 Multiple interrupts 7.8 Return from interrupt routine When the RTI instruction is executed at the end of the interrupt routine, the contents of the program bank register (PG), program counter (PC), and processor status register (PS) which were pushed onto the stack area just before the INTACK sequence, are automatically pulled. After this, the control returns to the original routine. And then, the suspended processing, which was in progress before the acceptance of the interrupt request, is resumed. Before the RTI instruction is executed, pull registers which were pushed by software in the interrupt routine, using the PUL instruction, etc. 7.9 Multiple interrupts Just after a branch is made to an interrupt routine, the following occur: *Interrupt disable flag (I) = "1" (Interrupts are disabled) *Interrupt request bit of accepted interrupt = "0" *Processor interrupt priority level (IPL) = Interrupt priority level of accepted interrupt Accordingly, as long as the IPL remains unchanged, an interrupt request whose priority level is higher than that of the interrupt which is in progress can be accepted by clearing the interrupt disable flag (I) to "0" in an interrupt routine. In this way, multiple interrupts are processed. Figure 7.9.1 shows the processing for multiple interrupts. An interrupt request which has not been accepted because its priority level is lower is held. When the RTI instruction is executed, the interrupt priority level of the routine which was in progress at acceptance of an interrupt request is pulled into the IPL. Therefore, if the following relationship is satisfied when interrupt priority level detection is performed next, the held interrupt request is accepted. Held interrupt request's priority level > Processor interrupt priority level (IPL) 7-16 7721 Group User's Manual INTERRUPTS 7.9 Multiple interrupts Interrupt request generated Time Reset Main routine I=1 Interrupt 1 IPL = 0 I=0 Interrupt priority level=3 Nesting Interrupt 1 I=1 Interrupt 2 IPL = 3 I=0 Multiple interrupts Interrupt priority level=5 Interrupt 2 I=1 IPL = 5 Interrupt 3 RTI Interrupt priority level=2 I=0 IPL = 3 Interrupt 3 RTI I=0 This request cannot be accepted because its priority level is lower than the interrupt 1's one. IPL = 0 The instruction in the main routine is not executed. Interrupt 3 I=1 IPL = 2 RTI I=0 IPL = 0 I : Interrupt disable flag IPL : Processor interrupt priority level : They are automatically set. : They must be set by software. Fig. 7.9.1 Processing for multiple interrupts 7721 Group User's Manual 7-17 INTERRUPTS ___ 7.10 External interrupts (INTi interrupt) ____ 7.10 External interrupts (INTi interrupt) ____ An external interrupt request occurs by an input signal to the INTi (i = 0 to 2) pin. The occurrence factor of the interrupt request can be selected by the level sense/edge sense select bit and the polarity select bit (bits 5 and 4 at addresses 7D16 to 7F16) shown in Figure 7.10.1. Table 7.10.1 lists the occurrence factor of ____ INTi interrupt request. ____ ____ When using P100/INT0 to P102/INT2 pins as input pins of external interrupts, set the corresponding bits at address 1816 (port P10 direction register) to "0." (Refer to "Figure 7.10.2.") ____ The signals input to the INTi pin require "H"- or "L"- level____ of 250 ns or more, independent of f(XIN). width ____ Additionally, even when using the pins P100/INT0 to P102/INT2 as the input pins of external interrupts, the user can obtain the pin's state by reading bits 0 to 2 at address 1616 (port P10 register). Note: When selecting an input signal's falling or "L" level as the occurrence factor of an interrupt request, make sure that the input signal is held "L" for 250 ns or more. When selecting an input signal's rising or "H" level as that, make sure that the input signal is held "H" for 250 ns or more. ___ Table 7.10.1 Occurrence factor of INTi interrupt request ___ b5 b4 INTi interrupt request occurrence factor ___ 0 0 Interrupt request occurs at the falling edge of a signal input to pin ___ (Edge sense). INTi 0 1 Interrupt request occurs at the rising edge of a signal input to pin INTi (Edge sense). ___ 1 1 ___ 0 1 Interrupt request occurs when pin INTi is at "H" level (Level sense). ___ Interrupt request occurs when pin INTi is at "L" level (Level sense). ___ The INTi interrupt ___ request occurs by detecting the state of pin INTi all the time. Therefore, when the user ___ does not use the INTi interrupt, set the INTi interrupt's priority level to level 0. 7-18 7721 Group User's Manual INTERRUPTS ___ 7.10 External interrupts (INTi interrupt) b7 b6 b5 b4 b3 b2 b1 b0 INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16) Bit 0 Bit name Interrupt priority level select bits b2 b1 b0 Functions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested At reset RW RW 0 1 0 RW 2 0 RW 3 4 Interrupt request bit (Note) Polarity select bit 0 0 RW RW 0 : Interrupt request bit is set to "1" at "H" level when level sense is selected; this bit is set to "1" at falling edge when edge sense is selected. 1 : Interrupt request bit is set to "1" at "L" at level when level sense is selected; this bit is set to "1" at rising edge when edge sense is selected. 0 : Edge sense 1 : Level sense 5 7, 6 Level sense/Edge sense select bit Nothing is assigned. 0 Undefined RW - Note: The interrupt request bits of INT0 to INT2 interrupts are invalid when the level sense is selected. ___ Fig. 7.10.1 Structure of INTi (i=0 to 2) interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 Port P10 direction register (Address 1816) Bit 0 1 2 3 4 5 6 7 Corresponding pin INT0 pin INT1 pin INT2 pin TC pin CAS pin RAS pin MA8 pin MA9 pin Functions 0 : Input mode 1 : Output mode When using a pin as an input pin for an external interrupt,clear the corresponding bit to "0." At reset RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 : Bits 3 to 7 are not used for external interrupts. Fig. 7.10.2 Relationship between port P10 direction register and input pins of external interrupt 7721 Group User's Manual 7-19 INTERRUPTS ___ 7.10 External interrupts (INTi interrupt) ____ 7.10.1 Functions of INTi interrupt request bit (1) Functions when edge sense is selected The interrupt request bit has the same functions as that of an internal interrupt. That is, when an interrupt request occurs, the interrupt request bit is set to "1" and retains this state until the interrupt request is accepted. When this bit is cleared to "0" by software, the interrupt request is cancelled; when this bit is set to "1" by software, the interrupt request can be generated. (2) Functions when level sense is selected ___ The INTi interrupt request bit is ignored. ___ ___ Interrupt requests continuously occur while the level of the INTi pin is the valid levelV1; when the INTi ___ pin's level changes from the valid level to the invalid levelV2 before the INTi interrupt request is accepted, this interrupt request is not retained. (Refer to "Figure 7.10.4.") Valid levelV1: This means the level selected by the polarity select bit (bit 4 at addresses 7D16 to 7F16) Invalid levelV2: This means the reversed level of "valid level" Data bus INTi pin Edge detection circuit Interrupt request bit "0" Level sense/Edge sense select bit Interrupt request "1" ___ Fig. 7.10.3 INTi Interrupt request Interrupt request is accepted. When the INTi pin's level changes to the invalid level before an interrupt request is accepted, the interrupt request is not retained. Return to main routine. Valid INTi pin level Invalid Main routine First interrupt routine Second interrupt routine Third interrupt routine Main routine ____ Fig. 7.10.4 Occurrence of INTi interrupt request when level sense is selected 7-20 7721 Group User's Manual INTERRUPTS ___ 7.10 External interrupts (INTi interrupt) ___ 7.10.2 Switching of INTi interrupt request occurrence factor ___ When the INTi interrupt request occurrence factor is switched in one of the following ways, the interrupt request bit may be set to "1": *Switching the level sense to the edge sense *Switching polarity Therefore, after this switching, make sure to____ the interrupt request bit to "0." Figure 7.10.5 shows an clear example of the switching procedure for the INTi interrupt request occurrence factor. (1) Switching level sense to edge sense (2) Switching polarity Set the interrupt priority level to level 0 or set the interrupt disable flag (I) to "1." (INTi interrupt is disabled. ) Set the interrupt priority level to level 0 or set the interrupt disable flag (I) to "1." (INTi interrupt is disabled. ) Clear the level sense/edge sense select bit to "0." ( Edge sense is selected. ) Set the polarity select bit. Clear the interrupt request bit to "0." Clear the interrupt request bit to "0." Set the interrupt priority level to one of levels 1-7 or clear the interrupt disable flag (I) to "0." (INTi interrupt request is acceptable.) Set the interrupt priority level to one of levels 1-7 or clear the interrupt disable flag (I) to "0." (INTi interrupt request is acceptable.) Note: The above settings must be done separately. Multiple settings must not be done at the same time, in other words, they must not be done only by 1 instruction. ___ Fig. 7.10.5 Example of switching procedure for INTi interrupt request occurrence factor 7721 Group User's Manual 7-21 INTERRUPTS 7.11 Precautions for interrupts 7.11 Precautions for interrupts When changing the interrupt priority level select bits (bits 0 to 2 at addresses 6C16 to 7F16), 2 to 7 cycles of are required until the interrupt priority level is changed. Therefore, when the interrupt priority level of a certain interrupt source is repeatedly changed in a very short time, which consists of a few instructions, it is necessary to reserve the time required for the change by software. Figure 7.11.1 shows a program example to reserve the time required for the change. Note that the time required for the change depends on the contents of the interrupt priority detection time select bits (bits 4 and 5 at address 5E16). Table 7.11.1 lists the correspondence between the number of instructions inserted in Figure 7.11.1 and the interrupt priority detection time select bits. : LDM.B #0XH, 00XXH NOP NOP NOP LDM.B #0XH, 00XXH : ; Write instruction for the interrupt priority level select bits ; Inserted NOP instruction (Note) ; ; ; Write instruction for the interrupt priority level select bits Note: Except the write instruction for address XX16, any instruction which has the same cycles as the NOP instruction can also be inserted. For the number of inserted NOP instructions, refer to "Table 7.11.1." XX: any of 6C to 7F Fig. 7.11.1 Program example to reserve time required for change of interrupt priority level Table 7.11.1 Correspondence between number of instructions to be inserted in Figure 7.11.1 and interrupt priority detection time select bits Interrupt priority detection time select bits (Note) b5 b4 0 0 0 1 1 1 0 1 Interrupt priority level detection time 7 cycles of 4 cycles of 2 cycles of Do not select. Number of inserted NOP instructions 4 or more 2 or more 1 or more Note: We recommend [b5 = "1", b4 = "0"]. 7-22 7721 Group User's Manual CHAPTER 8 TIMER A 8.1 Overview 8.2 Block description 8.3 Timer mode [Precautions for timer mode] 8.4 Event counter mode [Precautions for event counter mode] 8.5 One-shot pulse mode [Precautions for one-shot pulse mode] 8.6 Pulse width modulation (PWM) mode [Precautions for pulse width modulation (PWM) mode] TIMER A 8.1 Overview 8.1 Overview Timer to A4 Timer A2 to A consists of five counters, Timers A0 to A4, each equipped with a 16-bit reload function. Timers A0 operate independently of one another. A has four operating modes listed below. Timers A0 and A1 operate in the timer mode only. Timers A4 have selective four operating modes listed below. (1) Timer mode (Timers A0 to A4) The timer counts an internally generated count source. For Timers A2 to A4, the following functions can be used in this mode: *Gate function *Pulse output function (2) Event counter mode (Timers A2 to A4) The timer counts an external signal. The following functions can be used in this mode: *Pulse output function *Two-phase pulse signal processing function (3) One-shot pulse mode (Timers A2 to A4) The timer outputs a pulse which has an arbitrary width once. (4) Pulse width modulation (PWM) mode (Timers A2 to A4) Timer outputs pulses which have an arbitrary width in succession. The counter functions as one of the following pulse width modulators: *16-bit pulse width modulator *8-bit pulse width modulator In this chapter, Timer Ai (i = 0 to 4) indicates Timers A0 to A4. Timer Aj (j = 2 to 4) indicates Timers A2 to A4; this is applies when the timer A's input/output pins are used etc. (Hereafter, input/output pins are called I/O pins.) 8-2 7721 Group User's Manual TIMER A 8.2 Block description 8.2 Block description Figure 8.2.1 shows the block diagram of Timer A. Explanation of registers relevant to Timer A is described below. f2 f 16 f 64 f 512 Count source select bits Data bus (odd) Data bus (even) (Low-order 8 bits) Timer mode One-shot pulse mode PWM mode (High-order 8 bits) Timer Ai reload register (16) Timer mode (Gate function) Polarity switching Event counter mode Count start bit Timer Ai counter (16) Countup/Countdown switching (Always "count down" except for event counter mode) Timer Ai interrupt request bit TAj IN Trigger Countdown Up-down bit Pulse output function select bit TAj OUT Toggle F.F. i = 0-4, j = 2-4 Fig. 8.2.1 Block diagram of Timer A 7721 Group User's Manual 8-3 TIMER A 8.2 Block description 8.2.1 Counter and reload register (timer Ai register) Each of timer Ai counter and reload register consists of 16 bits. Countdown in the counter is performed each time the count source is input. In the event counter mode, it can also function as an up-counter. The reload register is used to store the initial value of the counter. When a counter underflow or overflow occurs, the reload register's contents are reloaded into the counter. A value is set to the counter and reload register by writing the value to the timer Ai register. Table 8.2.1 lists the memory assignment of the timer Ai register. The value written into the timer Ai register while counting is not in progress is set to the counter and reload register. The value written into the timer Ai register while counting is in progress is set only to the reload register. In this case, the reload register's updated contents are transferred to the counter at the next reload time. The value obtained when reading out the timer Ai register varies according to the operating mode. Table 8.2.2 lists reading from and writing to the timer Ai register. Table 8.2.1 Memory assignment of timer Ai register Timer Ai register Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register High-order byte Address 4716 Address 4916 Address 4B16 Address 4D16 Address 4F16 Low-order byte Address 4616 Address 4816 Address 4A16 Address 4C16 Address 4E16 Note: At reset, the contents of the timer Ai register are undefined. Table 8.2.2 Reading from and writing to timer Ai register Operating mode Timer mode Event counter mode One-shot pulse mode Pulse width modulation (PWM) mode Read Counter value is read out. (Note 1) Undefined value is read out. Write Notes 1: Also refer to "[Precautions for timer mode]" and "[Precautions for event counter mode]." 2: When reading from and writing to the timer Ai register, perform it in a unit of 16 bits. 8-4 7721 Group User's Manual TIMER A 8.2 Block description 8.2.2 Count start register This register is used to start and stop counting. Each bit of this register corresponds to each timer. Figure 8.2.2 shows the structure of the count start register. b7 b6 b5 b4 b3 b2 b1 b0 Count start register (Address 4016) Bit 0 1 2 3 4 5 6 7 Bit name Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit Functions 0 : Stop counting 1 : Start counting At reset RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 : Bits 5 to 7 are not used for Timer A. Fig. 8.2.2 Structure of count start register 7721 Group User's Manual 8-5 TIMER A 8.2 Block description 8.2.3 Timer Ai mode register Figure 8.2.3 shows the structure of the timer Ai mode register. The operating mode select bits are used to select the operating mode of Timer Ai. Bits 2 to 7 have different functions according to the operating mode. These bits are described in the paragraph of each operating mode. b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Bit 0 Bit name Operating mode select bits b1 b0 Functions 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot pulse mode 1 1 : Pulse width modulation (PWM) mode At reset RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 These bits have different functions according to the operating mode. Fig. 8.2.3 Structure of timer Ai mode register 8-6 7721 Group User's Manual TIMER A 8.2 Block description 8.2.4 Timer Ai interrupt control register Figure 8.2.4 shows the structure of the timer Ai interrupt control register. For details about interrupts, refer to "CHAPTER 7. INTERRUPTS." b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai interrupt control register (i = 0 to 4) (Addresses 7516 to 7916) Bit 0 Bit name Interrupt priority level select bits b2 b1 b0 Functions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level 0 : No interrupt requested 1 : Interrupt requested At reset RW RW 0 1 0 RW 2 0 RW 3 Interrupt request bit 0 Undefined RW 7 to 4 Nothing is assigned. - Fig. 8.2.4 Structure of timer Ai interrupt control register (1) Interrupt priority level select bits (bits 2 to 0) These bits select a timer Ai interrupt's priority level. When using timer Ai interrupts, select one of the priority levels (1 to 7). When a timer Ai interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = "0.") To disable timer Ai interrupts, set these bits to "0002" (level 0). (2) Interrupt request bit (bit 3) This bit is set to "1" when a timer Ai interrupt request occurs. This bit is automatically cleared to "0" when the timer Ai interrupt request is accepted. This bit can be set to "1" or cleared to "0" by software. 7721 Group User's Manual 8-7 TIMER A 8.2 Block description 8.2.5 Port P5 direction register The I/O pins of Timers A2 to A4 are multiplexed with port P5. When using these pins as Timer Aj's input pins, set the corresponding bits of the port P5 direction register to "0" to set these port pins for the input mode. When used as Timer Aj's output pins, these pins are forcibly set to the output pins of Timer Aj regardless of the direction registers's contents. Figure 8.2.5 shows the relationship between the port P5 direction register and the Timer Aj's I/O pins. b7 b6 b5 b4 b3 b2 b1 b0 Port P5 direction register (Address D16) Bit 0 1 2 3 4 5 6 7 Bit name TA2OUT pin TA2IN pin TA3OUT pin TA3IN pin TA4OUT pin TA4IN pin TB0IN pin TB1IN pin Functions 0 : Input mode 1 : Output mode When using these pins as Timer Aj' s input pins, set the corresponding bits to "0." At reset RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 : Bits 6 and 7 are not used for Timer A. Fig. 8.2.5 Relationship between port P5 direction register and Timer Aj's I/O pins 8-8 7721 Group User's Manual TIMER A 8.3 Timer mode 8.3 Timer mode In this mode, the timer counts an internally generated count source. (Refer to "Table 8.3.1.") Figure 8.3.1 shows the structures of the timer Ai mode register and timer Ai register in the timer mode. Table 8.3.1 Specifications of timer mode Item Count source Count operation f2, f16, f64, or f512 * Countdown * When a counter underflow occurs, reload register's contents are reloaded, and counting continues. Division ratio Count start condition Count stop condition TAjIN pin's function TAjOUT pin's function Read from timer Ai register Write to timer Ai register 1 (n + 1) n : Timer Ai register's set value Specifications When the count start bit is set to "1." When the count start bit is cleared to "0." Programmable I/O port or gate input Programmable I/O port or pulse output Counter value can be read out. q While counting is stopped When a value is written to the timer Ai register, it is written to both of the reload register and counter. q While counting is in progress When a value is written to the timer Ai register, it is written only to the reload register. (Transferred to the counter at the next reload timing.) Interrupt request occurrence timing When a counter underflow occurs. 7721 Group User's Manual 8-9 TIMER A 8.3 Timer mode b7 b6 b5 b4 b3 b2 b1 b0 000000 Timer A0 mode register (Address 5616) Timer A1 mode register (Address 5716) Bit 0 1 2 3 4 5 6 7 Bit name Fix these bits to "0." Functions At reset RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 Count source select bits b7 b6 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 0 0 b7 b6 b5 b4 b3 b2 b1 b0 0 00 Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) Bit 0 1 2 Bit name Operating mode select bits b1 b0 Functions 0 0 : Timer mode At reset RW RW RW RW 0 0 Pulse output function select bit 0 : No pulse output (TAjOUT pin functions as a programmable I/O port.) 1 : Pulse output (TAjOUT pin functions as a pulse output pin.) b4 b3 0 3 Gate function select bits 0 RW 4 0 0 : No gate function 0 1 : (TAjIN pin functions as a programmable I/O port.) 1 0 : Counter counts only while TAjIN pin's input signal is at "L" level. 1 1 : Counter counts only while TAjIN pin's input signal is at "H" level. 0 RW 5 6 7 Fix this bit to "0" in timer mode. Count source select bits b7 b6 0 0 0 RW RW RW 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 (b15) b7 (b8) b0 b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Bit Functions At reset Undefined RW RW 15 to 0 These bits can be set to "000016" to "FFFF16." Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Note: Read from or write to this register in a unit of 16 bits. Fig. 8.3.1 Structures of timer Ai mode register and timer Ai register in timer mode 8-10 7721 Group User's Manual TIMER A 8.3 Timer mode 8.3.1 Setting for timer mode Figures 8.3.2 and 8.3.3 show an initial setting example for registers relevant to the timer mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to section "CHAPTER 7. INTERRUPTS." Selecting timer mode and each function b7 b0 0 00 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Selection of timer mode Pulse output function select bit 0: No pulse output. 1: Pulses output. Gate function select bits b4 b3 0 0: No gate function 0 1: 1 0: Gate function (Counter counts only while TAjIN pin's input signal is at "L" level.) 1 1: Gate function (Counter counts only while TAjIN pin's input signal is at "H" level.) Count source select bits b7 b6 0 0: f2 0 1: f16 1 0: f64 1 1: f512 Note: For Timers A0 and A1, set bits 0 to 5 to "0." Setting division ratio (b15) b7 (b8) b0 b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Can be set to "000016" to "FFFF16" (n). Note: The counter divides the count source frequency by (n + 1). Continue to Figure 8.3.3 on next page. Fig. 8.3.2 Initial setting example for registers relevant to timer mode (1) 7721 Group User's Manual 8-11 TIMER A 8.3 Timer mode From preceding Figure 8.3.2. Setting interrupt priority level b7 b0 Timer Ai interrupt control register (i = 0 to 4) (Addresses 7516 to 7916) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Setting port P5 direction register b7 b0 Port P5 direction register (Address D16) TA2IN pin TA3IN pin TA4IN pin When gate function is selected, set the bit corresponding to the TAjIN pin to "0." Setting count start bit to "1." b7 b0 Count start register (Address 4016) Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Count starts Fig. 8.3.3 Initial setting example for registers relevant to timer mode (2) 8-12 7721 Group User's Manual TIMER A 8.3 Timer mode 8.3.2 Count source In the timer mode, the count source select bits (bits 6 and 7 at addresses 5616 to 5A16) select the count source. Table 8.3.2 lists the count source frequency. Table 8.3.2 Count source frequency Count source select bits b7 0 0 1 1 b6 0 1 0 1 f2 f16 f64 f512 Count source f(XIN) = 8 MHz 4 MHz 500 kHz 125 kHz 15625 Hz Count source frequency f(XIN) = 16 MHz 8 MHz 1 MHz 250 kHz 31250 Hz f(XIN) = 25 MHz 12.5 MHz 1.5625 MHz 390.625 kHz 48.8281 kHz 7721 Group User's Manual 8-13 TIMER A 8.3 Timer mode 8.3.3 Operation in timer mode When the count start bit is set to "1," the counter starts counting of the count source. When a counter underflow occurs, the reload register's contents are reloaded, and counting continues. The timer Ai interrupt request bit is set to "1" at the underflow in . The interrupt request bit remains set to "1" until the interrupt request is accepted or the interrupt request bit is cleared to "0" by software. Figure 8.3.4 shows an example of operation in the timer mode. n = Reload register's contents FFFF16 Counter contents (Hex.) Starts counting. 1 / fi ! (n+1) Stops counting. n Restarts counting. 000016 Time Set to "1" by software. Cleared to "0" by software. Set to "1" by software. Count start bit Timer Ai interrupt request bit fi = frequency of count source (f2, f16, f64, f512) Cleared to "0" when interrupt request is accepted or cleared by software. Fig. 8.3.4 Example of operation in timer mode (without pulse output and gate functions) 8-14 7721 Group User's Manual TIMER A 8.3 Timer mode 8.3.4 Selectable functions The following describes the selectable gate function for Timers A2 to A4 and pulse output function. (1) Gate function The gate function is selected by setting the gate function select bits (bits 4 and 3 at addresses 5816 to 5A16 ) to "102" or "112." The gate function makes it possible to start or stop counting depending on the TAjIN pin's input signal. Table 8.3.3 lists the count valid levels. Figure 8.3.5 shows an example of operation with the gate function selected. When selecting the gate function, set the port P5 direction registers' bits which correspond to the TAjIN pin for the input mode. Additionally, make sure that the TAjIN pin's input signal has a pulse width equal to or more than two cycles of the count source. Table 8.3.3 Count valid levels Gate function select bits b3 b4 0 1 Count valid level (Duration while counter counts) While TAjIN pin's input signal is at "L" level While TAjIN pin's input signal is at "H" level 1 1 Note: The counter does not count while the TAjIN pin's input signal is not at the count valid level. FFFF16 n n = Reload register's contents Starts counting. Counter contents (Hex.) Stops counting. 000016 Set to "1" by software. Count start bit Count valid level Invalid level Time TAjIN pin's input signal Timer Aj interrupt request bit The counter counts when the count start bit = "1" and the TAjIN pin's input signal is at the count valid level. The counter stops counting while the TAjIN pin's input signal is not at the count valid level, and the counter value is retained. Cleared to "0" when interrupt request is accepted or cleared by software. Fig. 8.3.5 Example of operation selecting gate function 7721 Group User's Manual 8-15 TIMER A 8.3 Timer mode (2) Pulse output function The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses 5816 to 5A16) to "1." When this function is selected, the TAjOUT pin is forcibly set for the pulse output pin regardless of the corresponding bits of the port P5 direction register. The TAjOUT pin outputs pulses of which polarity is inverted each time a counter underflow occurs. When the count start bit (address 4016) is "0" (count stopped), the TAjOUT pin outputs "L" level. Figure 8.3.6 shows an example of operation with the pulse output function selected. n = Reload register's contents FFFF16 Starts counting. Starts counting. Restarts counting. Counter contents (Hex.) n 000016 Time Set to "1" by software. Count start bit Cleared to "0" by software. Set to "1" by software. Pulse output from TAjOUT pin Timer Aj interrupt request bit Cleared to "0" when interrupt request is accepted or cleared by software. Fig. 8.3.6 Example of operation selecting pulse output function 8-16 7721 Group User's Manual TIMER A 8.3 Timer mode [Precautions for timer mode] By reading the timer Ai register, the counter value can be read out at any timing. However, if the timer Ai register is read at the reload timing shown in Figure 8.3.7, the value "FFFF16" is read out. If reading is performed in the period from when a value is set into the timer Ai register with the counter stopped until the counter starts counting, the set value is correctly read out. Reload Counter value (Hex.) 2 1 0 n n-1 Read value (Hex.) 2 1 0 FFFF n - 1 Time n = Reload register's contents Fig. 8.3.7 Reading timer Ai register 7721 Group User's Manual 8-17 TIMER A 8.4 Event counter mode 8.4 Event counter mode In this mode, the timer counts an external signal. (Refer to "Tables 8.4.1 and 8.4.2.") Timers A2 to A4 can be used in this mode. Figure 8.4.1 shows the structures of the timer Aj mode register and timer Aj register in the event counter mode. Table 8.4.1 Specifications of event counter mode (when not using two-phase pulse signal processing function) Item Count source Specifications q External signal input to the TAjIN pin q The count source's valid edge can be selected from the falling edge and the rising edge by software. q Countup or countdown can be switched by external signal or software. q When a counter overflow or underflow occurs, reload register's contents are reloaded, and counting continues. Division ratio q For countdown q For countup Count start condition Count stop condition 1 (n + 1) n : Timer Aj register's set value Count operation 1 (FFFF16 - n + 1) When the count start bit is set to "1." When the count start bit is cleared to "0." Interrupt request occurrence timing When a counter overflow or underflow occurs. Count source input TAjIN pin's function TAjOUT pin's function Read from timer Aj register Write to timer Aj register Programmable I/O port, pulse output, or countup/countdown switch signal input Counter value can be read out. q While counting is stopped When a value is written to the timer Aj register, it is written to both of the reload register and counter. q While counting is in progress When a value is written to the timer Aj register, it is written only to the reload register. (Transferred to the counter at the next reload time.) 8-18 7721 Group User's Manual TIMER A 8.4 Event counter mode Table 8.4.2 Specifications of event counter mode (when using two-phase pulse signal processing function) Item Count source Count operation Specifications External signal (two-phase pulse) input to the TAjIN or TAjOUT pin q Countup or countdown can be switched by external signal (twophase pulse). q When a counter overflow or underflow occurs, reload register's contents are reloaded, and counting continues. 1 q For countdown (n + 1) n : Timer Aj register's set value q For countup Count start condition Count stop condition 1 (FFFF16 - n + 1) Division ratio When the count start bit is set to "1." When the count start bit is cleared to "0." Interrupt request occurrence timing When a counter overflow or underflow occurs. TAjIN, TAjOUT pin function Read from timer Aj register Write to timer Aj register Two-phase pulse input Counter value can be read out. q While counting is stopped When a value is written to the timer Aj register, it is written to both of the reload register and counter. q While counting is in progress When a value is written to the timer Aj register, it is written only to the reload register. (Transferred to the counter at the next reload time.) 7721 Group User's Manual 8-19 TIMER A 8.4 Event counter mode b7 b6 b5 b4 b3 b2 b1 b0 !!0 01 Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) Bit 0 1 2 Bit name Operating mode select bits b1 b0 Functions 0 1 : Event counter mode At reset RW RW RW RW 0 0 Pulse output function select bit 0 : No pulse output (TAjOUT pin functions as a programmable I/O port.) 1 : Pulse output (TAjOUT pin functions as a pulse output pin.) 0 : Counts at falling edge of external signal 1 : Counts at rising edge of external signal 0 : Contents of up-down register 1 : Input signal to TAjOUT pin 0 3 4 5 6 7 Count polarity select bit Up-down switching factor select bit 0 0 0 0 0 RW RW RW RW RW Fix this bit to "0" in event counter mode. These bits are invalid in event counter mode. (b15) b7 (b8) b0 b7 b0 Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) At reset Undefined Bit Functions RW RW 15 to 0 These bits can be set to "000016" to "FFFF16." Assuming that the set value = n, the counter divides the count source frequency by (n + 1) during countdown, or by (FFFF16 - n + 1) during countup. When reading, the register indicates the counter value. Note: Read from or write to this register in a unit of 16 bits. Fig. 8.4.1 Structures of timer Aj mode register and timer Aj register in event counter mode 8-20 7721 Group User's Manual TIMER A 8.4 Event counter mode 8.4.1 Setting for event counter mode Figures 8.4.2 and 8.4.3 show an initial setting example for registers relevant to the event counter mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Selecting event counter mode and each function b7 b0 !! 0 01 Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) Selection of event counter mode Pulse output function select bit 0: No pulse output 1: Pulse output Count polarity select bit 0: Counts at falling edge of external signal. 1: Counts at rising edge of external signal. Up-down switching factor select bit 0: Contents of up-down register 1: Input signal to TAjOUT pin ! : It may be either "0" or "1." Setting up-down register b7 b0 00 Up-down register (Address 4416) Set the corresponding up-down bit when the contents of the up-down register are selected as the up-down switching factor. 0: Countdown 1: Countup Timer A2 up-down bit Timer A3 up-down bit Timer A4 up-down bit Timer A2 two-phase pulse signal processing select bit Timer A3 two-phase pulse signal processing select bit Timer A4 two-phase pulse signal processing select bit Set the corresponding bit to "1" when the two-phase pulse signal processing function is selected for timers A2 to A4. 0: Two-phase pulse signal processing function disabled 1: Two-phase pulse signal processing function enabled Setting division ratio (b15) b7 (b8) b0 b7 b0 Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Can be set to "000016" to "FFFF16" (n). T The counter divides the count source frequency by (n + 1) when counting down, or by (FFFF16 - n + 1) when counting up. Continue to Figure 8.4.3 on next page. Fig. 8.4.2 Initial setting example for registers relevant to event counter mode (1) 7721 Group User's Manual 8-21 TIMER A 8.4 Event counter mode From preceding Figure 8.4.2. Setting interrupt priority level b7 b0 Timer Aj interrupt control register (j = 2 to 4) (Addresses 7716 to 7916) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Setting port P5 direction register b7 b0 Port P5 direction register (Address D16) TA2OUT pin TA2IN pin TA3OUT pin TA3IN pin TA4OUT pin TA4IN pin Clear the bit corresponding to the TAjIN pin to "0." When selecting the TAjOUT pin's input signal as the up-down switching factor, set the bit corresponding to the TAjOUT pin to "0." When selecting the two-phase pulse signal processing function, set the bit corresponding to the TAjOUT pin to "0." Setting the count start bit to "1" b7 b0 Count start register (Address 4016) Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Count starts Fig. 8.4.3 Initial setting example for registers relevant to event counter mode (2) 8-22 7721 Group User's Manual TIMER A 8.4 Event counter mode 8.4.2 Operation in event counter mode When the count start bit is set to "1," the counter starts counting of the count source's valid edges. When a counter underflow or overflow occurs, the reload register's contents are reloaded, and counting continues. The timer Aj interrupt request bit is set to "1" at the underflow or overflow in . The interrupt request bit remains set to "1" until the interrupt request is accepted or the interrupt request bit is cleared to "0" by software. Figure 8.4.4 shows an example of operation in the event counter mode. n = Reload register's contents FFFF16 Starts counting. Counter contents (Hex.) n 000016 Time Set to "1" by software. Count start bit Set to "1" by software. Up-down bit Timer Aj interrupt request bit Cleared to "0" when interrupt request is accepted or cleared by software. Note: The above applies when the up-down bit's contents are selected as the up-down switching factor (i.e., up-down switching factor select bit = "0" ). Fig. 8.4.4 Example of operation in event counter mode (without pulse output and two-phase pulse signal processing functions) 7721 Group User's Manual 8-23 TIMER A 8.4 Event counter mode 8.4.3 Switching between countup and countdown The up-down register (address 4416) or the input signal from the TAjOUT pin is used to switch countup from and to countdown. This switching is performed by the up-down bit when the up-down switching factor select bit (bit 4 at addresses 5816 to 5A16) is "0," and by the input signal from the TAjOUT pin when the up-down switching factor select bit is "1." When the switching between countup and countdown is set while counting is in progress, this switching is actually performed when the count source's next valid edge is input. (1) Switching by up-down bit Countdown is performed when the up-down bit is "0," and countup is performed when the up-down bit is "1." Figure 8.4.5 shows the structure of the up-down register. (2) Switching by TAjOUT pin's input signal Countdown is performed when the TAjOUT pin's input signal is at "L" level, and countup is performed when the TAjOUT pin's input signal is at "H" level. When using the TAjOUT pin's input signal to switch countup from and to countdown, set the port P5 direction register's bit which corresponds to the TAjOUT pin for the input mode. b7 b6 b5 b4 b3 b2 b1 b0 00 Up-down register (Address 4416) Bit 0 1 2 3 4 5 Bit name Fix these bits to "0." Functions At reset RW RW RW RW RW RW WO 0 0 Timer A2 up-down bit Timer A3 up-down bit Timer A4 up-down bit 0 : Countdown 1 : Countup This function is valid when the contents of the up-down register is selected as the updown switching factor. 0 0 0 0 6 Timer A2 two-phase pulse signal 0 : Two-phase pulse signal processing function disabled processing select bit (Note) 1 : Two-phase pulse signal processing function enabled Timer A3 two-phase pulse signal processing select bit When not using the two-phase pulse signal processing function, set the bit Timer A4 two-phase pulse signal to "0." processing select bit (Note) The value is "0" at reading. (Note) 0 WO 7 0 WO Note: Use the LDM or STA instruction for writing to bits 5 to 7. Fig. 8.4.5 Structure of up-down register 8-24 7721 Group User's Manual TIMER A 8.4 Event counter mode 8.4.4 Selectable functions The following describes the selectable pulse output, and two-phase pulse signal processing functions. (1) Pulse output function The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses 5816 to 5A16) to "1." When this function is selected, the TAjOUT pin is forcibly set for the pulse output pin regardless of the corresponding bit of the port P5 direction register. The TAjOUT pin outputs pulses of which polarity is inverted each time a counter underflow or overflow occurs. (Refer to "Figure 8.3.6.") When the count start bit (address 4016) is "0" (count stopped), the TAjOUT pin outputs "L" level. 7721 Group User's Manual 8-25 TIMER A 8.4 Event counter mode (2) Two-phase pulse signal processing function The two-phase pulse signal processing function is selected by setting the two-phase pulse signal processing select bits (bits 5 to 7 at address 4416) to "1." (Refer to "Figure 8.4.5.") Figure 8.4.6 shows the timer Aj mode registers when the two-phase pulse signal processing function is selected. For timers with the two-phase pulse signal processing function selected, the timer counts two kinds of pulses of which phases differ by 90 degrees. There are two types of the two-phase pulse signal processing: normal processing and quadruple processing. In Timers A2 and A3, normal processing is performed; in timer A4, quadruple processing is performed. For some bits of the port P5 direction register correspond to pins used for two-phase pulse input, set these bits for the input mode. b7 b6 b5 b4 b3 b2 b1 b0 !!010001 ! : It may be either "0" or "1." Timer A2 mode register (Address 5816) Timer A3 mode register (Address 5916) Timer A4 mode register (Address 5A16) Fig. 8.4.6 Timer Aj mode registers when two-phase pulse signal processing function is selected qNormal processing Countup is performed at the rising edges input to the TAkIN pin when the phase has the relationship that the TAkIN pin's input signal level goes from "L" to "H" while the TAkOUT (k = 2 and 3) pin's input signal is at "H" level. Countdown is performed at the falling edges input to the TAkIN pin when the phase has the relationship that the TAkIN pin's input signal level goes from "H" to "L" while the TAkOUT pin's input signal is at "H" level. (Refer to "Figure 8.4.7.") TAkOUT TAkIN (k=2, 3) Counted Up up count Counted up Counted up Counted down Counted down Counted down +1 Fig. 8.4.7 Normal processing +1 +1 -1 -1 -1 8-26 7721 Group User's Manual TIMER A 8.4 Event counter mode qQuadruple processing Countup is performed at all rising and falling edges input to the TA4OUT and TA4IN pins when the phase has the relationship that the TA4IN pin's input signal level goes from "L" to "H" while the TA4OUT pin's input signal is at "H" level. Countdown is performed at all rising and falling edges input to the TA4OUT and TA4IN pins when the phase has the relationship that the TA4IN pin's input signal level goes from "H" to "L" while the TA4OUT pin's input signal is at "H" level. (Refer to "Figure 8.4.8.") Table 8.4.3 lists the relationship between the input signals to the TA4OUT and TA4IN pins and count operation when the quadruple processing is selected. TA4OUT Counted up at all edges +1 +1 +1 +1 +1 Counted down at all edges -1 -1 -1 -1 -1 TA4IN Counted up at all edges +1 Fig. 8.4.8 Quadruple processing Counted down at all edges -1 -1 -1 -1 -1 +1 +1 +1 +1 Table 8.4.3 Relationship between input signals to TA4OUT and TA4IN pins and count operation when quadruple processing is selected Input signal to TA4OUT pin Input signal to TA4IN pin Up-count "H" level "L" level Rising edge Falling edge "H" level "L" level Rising edge Falling edge Rising edge Falling edge "L" level "H" level Falling edge Rising edge "H" level "L" level Down-count 7721 Group User's Manual 8-27 TIMER A 8.4 Event counter mode [Precautions for event counter mode] 1. While counting is in progress, by reading the timer Aj register, the counter value can be read out at any timing. However, if the timer Aj register is read at the reload timing shown in Figure 8.4.9, the value "FFFF16" (at an underflow) or "000016" (at an overflow) is read out. If reading is performed in the period from when a value is set into the timer Aj register with the counter stopped until the counter starts counting, the set value is correctly read out. (1) For countdown Reload (2) For countup Reload Counter value (Hex.) 2 1 0 n n-1 Counter value (Hex.) FFFD FFFE FFFF n n+1 Read value (Hex.) 2 1 0 FFFF n - 1 Time Read value (Hex.) FFFD FFFE FFFF 0000 n + 1 Time n = Reload register's contents n = Reload register's contents Fig. 8.4.9 Reading timer Aj register 2. The TAjOUT pin is used for all functions listed below. Accordingly, only one of these functions can be selected for each timer. *Switching between countup and countdown by TAjOUT pin's input signal *Pulse output function *Two-phase pulse signal processing function 8-28 7721 Group User's Manual TIMER A 8.5 One-shot pulse mode 8.5 One-shot pulse mode In this mode, the timer outputs a pulse which has an arbitrary width once. (Refer to "Table 8.5.1.") Timers A2 to A4 can be used in this mode. When a trigger occurs, the timer outputs "H" level from the TAjOUT pin for an arbitrary time. Figure 8.5.1 shows the structures of the timer Aj mode register and timer Aj register in the one-shot pulse mode. Table 8.5.1 Specifications of one-shot pulse mode Item Count source Count operation Specifications f2, f16, f64, or f512 q Countdown q When the counter value becomes "000016," reload register's contents are reloaded, and counting stops. q If a trigger occurs during counting, reload register's contents are reloaded, and counting continues. n fi [S] n : Timer Aj register's set value Output pulse width ("H") Count start condition q When a trigger occurs. (Note) q Internal or external trigger can be selected by software. , q When the counter value becomes "000016 " Count stop condition q When the count start bit is cleared to "0" Interrupt request occurrence timing When counting stops. Programmable I/O port or trigger input TAjIN pin's function One-shot pulse output TAjOUT pin's function An undefined value is read out. Read from timer Aj register q While counting is stopped Write to timer Aj register When a value is written to the timer Aj register, it is written to both of the reload register and counter. q While counting is in progress When a value is written to the timer Aj register, it is written only to the reload register. (Transferred to the counter at the next reload time.) Note: The trigger is generated with the count start bit = "1." 7721 Group User's Manual 8-29 TIMER A 8.5 One-shot pulse mode b7 b6 b5 b4 b3 b2 b1 b0 0 110 Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) Bit 0 1@ 2 3 Bit name Operating mode select bits b1 b0 Functions 1 0 : One-shot pulse mode At reset RW RW RW RW RW 0 0 Fix this bit to "1" in one-shot pulse mode. Trigger select bits b4 b3 0 0 4 0 0 : Writing "1" to one-shot start register 0 1 : (TAjIN pin functions as a programmable I/O port.) 1 0 : Falling edge of TAjIN pin's input signal 1 1 : Rising edge of TAjIN pin's input signal 0 RW 5 6 7 Fix this bit to "0" in one-shot pulse mode. Count source select bits b7 b6 0 0 0 RW RW 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 RW (b15) b7 (b8) b0 b7 b0 Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Bit Functions At reset Undefined RW WO 15 to 0 These bits can be set to "000116" to "FFFF16." Assuming that the set value = n, the "H" level width of the one-shot pulse output from the TAjOUT pin is expressed as follows : n fi. fi: Frequency of count source (f2, f16, f64, or f512) Note: Use the LDM or STA instruction for writing to this register. Read from or write to this register in a unit of 16 bits. Fig. 8.5.1 Structures of timer Aj mode register and timer Aj register in one-shot pulse mode 8-30 7721 Group User's Manual TIMER A 8.5 One-shot pulse mode 8.5.1 Setting for one-shot pulse mode Figures 8.5.2 and 8.5.3 show an initial setting example for registers relevant to the one-shot pulse mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Selecting one-shot pulse mode and each function b7 b0 0 110 Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) Selection of one-shot pulse mode Trigger select bits b4 b3 00: Writing "1" to one-shot start bit: Internal trigger 01: 1 0 : Falling edge of TAjIN pin's input signal: External trigger 1 1 : Rising edge of TAjIN pin's input signal: External trigger Count source select bits b7 b6 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 Setting "H" level width of one-shot pulse (b15) b7 (b8) b0 b7 b0 Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Can be set to "000116" to "FFFF16" (n). Note. "H" level width = n fi fi: Frequency of count source Setting interrupt priority level b7 b0 Timer Aj interrupt control register (j = 2 to 4) (Addresses 7716 to 7916) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Continue to Figure 8.5.3. Fig. 8.5.2 Initial setting example for registers relevant to one-shot pulse mode (1) 7721 Group User's Manual 8-31 TIMER A 8.5 One-shot pulse mode From preceding Figure 8.5.2. When external trigger is selected Setting port P5 direction register b7 b0 When internal trigger is selected Setting count start bit to "1" b7 b0 Port P5 direction register (Address D16) TA2IN pin TA3IN pin TA4IN pin Count start register (Address 4016) Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Set the corresponding bit to "0." Setting count start bit to "1" b7 b0 Setting one-shot start bit to "1" b7 b0 Count start register (Address 4016) Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit 00 One-shot start register (Address 4216) Timer A2 one-shot start bit Timer A3 one-shot start bit Timer A4 one-shot start bit Trigger input to TAjIN pin Trigger generated Count starts Fig. 8.5.3 Initial setting example for registers relevant to one-shot pulse mode (2) 8-32 7721 Group User's Manual TIMER A 8.5 One-shot pulse mode 8.5.2 Count source In the one-shot pulse mode, the count source select bits (bits 6 and 7 at addresses 5816 to 5A16) select the count source. Table 8.5.2 lists the count source frequency. Table 8.5.2 Count source frequency Count source select bits b7 0 0 1 1 b6 0 1 0 1 f2 f16 f64 f512 Count source f(XIN) = 8 MHz 4 MHz 500 kHz 125 kHz 15625 Hz Count source frequency f(XIN) = 16 MHz 8 MHz 1 MHz 250 kHz 31250 Hz f(XIN) = 25 MHz 12.5 MHz 1.5625 MHz 390.625 kHz 48.8281 kHz 7721 Group User's Manual 8-33 TIMER A 8.5 One-shot pulse mode 8.5.3 Trigger The counter is enabled for counting when the count start bit (address 4016) is set to "1." The counter starts counting when a trigger is generated after counting has been enabled. An internal or external trigger can be selected as that trigger. An internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 5816 to 5A16) are "002" or "012"; an external trigger is selected when the bits are "102" or "112." If a trigger is generated during counting, the reload register's contents are reloaded and the counter continues counting. If generating a trigger during counting, make sure that a certain time which is equivalent to one cycle of the timer's count source or more has passed between the previously generated trigger and a new trigger. (1) When selecting internal trigger A trigger is generated when writing "1" to the one-shot start bit (bits 2 to 4 at address 4216). Figure 8.5.4 shows the structure of the one-shot start register. (2) When selecting external trigger A trigger is generated at the falling edge of the TAjIN pin's input signal when bit 3 at addresses 5816 to 5A16 is "0," or at its rising edge when bit 3 is "1." When using an external trigger, set the port P5 direction registers' bits which correspond to the TAjIN pins for the input mode. b7 b6 b5 b4 b3 b2 b1 b0 00 . One-shot start register (Address 4216) Bit 0 1 2 3 4 Bit name Functions At reset RW WO WO WO WO WO Fix these bits to "0." The value is "0" at reading. 0 0 Timer A2 one-shot start bit Timer A3 one-shot start bit Timer A4 one-shot start bit 1 : Start outputting one-shot pulse (valid when internal trigger is selected.) The value is "0" at reading. 0 0 0 Undefined 7 to 5 Nothing is assigned. - Fig. 8.5.4 Structure of one-shot start register 8-34 7721 Group User's Manual TIMER A 8.5 One-shot pulse mode 8.5.4 Operation in one-shot pulse mode When the one-shot pulse mode is selected with the operating mode select bits, the TAjOUT pin outputs "L" level. When the count start bit is set to "1," the counter is enabled for counting. After that, counting starts when a trigger is generated. When the counter starts counting, the TAjOUT pin outputs "H" level. When the counter value becomes "000016," the output from the TAjOUT pin becomes "L" level. Additionally, the reload register's contents are reloaded and the counter stops counting there. Simultaneously with , the timer Aj interrupt request bit is set to "1." This interrupt request bit remains set to "1" until the interrupt request is accepted or the interrupt request bit is cleared to "0" by software. Figure 8.5.5 shows an example of operation in the one-shot pulse mode. When a trigger is generated after above, the counter and TAjOUT pin perform the same operations beginning from again. Furthermore, if a trigger is generated during counting, the counter performs countdown once after this new trigger is generated, and it continues counting with the reload register's contents reloaded. If generating a trigger during counting, make sure that a certain time which is equivalent to one cycle of the timer's count source or more has passed between the previously generated trigger and a new trigger. The one-shot pulse output from the TAjOUT pin can be disabled by clearing the timer Aj mode register's bit 2 to "0." Accordingly, Timer Aj can be also used as an internal one-shot timer that does not perform the pulse output. In this case, the TAjOUT pin functions as a programmable I/O port. 7721 Group User's Manual 8-35 TIMER A 8.5 One-shot pulse mode FFFF16 n = Reload register's contents Starts counting. Counter contents (Hex.) Stops counting. Starts counting. Stops counting. n Reloaded Reloaded 000116 Time Set to "1" by software. Count start bit Trigger during counting TAjIN pin input signal 1 / fi ! (n) One-shot pulse output from TAjOUT pin 1 / fi ! (n+1) Timer Aj interrupt request bit fi = Frequency of count source (f2, f16, f64, or f512) Cleared to "0" when interrupt request is accepted or cleared by software. When the count start bit = "0" (counting stopped), the TAjOUT pin outputs "L" level. When a trigger is generated during counting, the counter counts the count source (n + 1) times after a new trigger is generated. Note: The above applies when an external trigger (rising of TAjIN pin's input signal) is selected. Fig. 8.5.5 Example of operation in one-shot pulse mode (selecting external trigger) 8-36 7721 Group User's Manual TIMER A 8.5 One-shot pulse mode [Precautions for one-shot pulse mode] 1. If the *The *The *The count start bit is cleared to "0" during counting, the counter becomes as follows: counter stops counting, and the reload register's contents are reloaded into the counter. TAjOUT pin's output level becomes "L." timer Aj interrupt request bit is set to "1." 2. A one-shot pulse is output synchronously with an internally generated count source. Accordingly, when selecting an external trigger, there will be a delay equivalent to one cycle of the count source at maximum from when a trigger is input to the TAjIN pin until a one-shot pulse is output. Trigger input TAjIN pin's input signal Count source One-shot pulse output from TAjOUT pin Starts outputting of one-shot pulse Note: The above applies when an external trigger (falling edge of TAjIN pin's input signal) is selected. Fig. 8.5.6 Output delay in one-shot pulse output 3. When the timer's operating mode is set by one of the following procedures, the timer Aj interrupt request bit is set to "1." qWhen the one-shot pulse mode is selected after reset qWhen the operating mode is switched from the timer mode to the one-shot pulse mode qWhen the operating mode is switched from the event counter mode to the one-shot pulse mode Accordingly, when using the timer Aj interrupt (interrupt request bit), be sure to clear the timer Aj interrupt request bit to "0" after the above setting. 4. Don not set "000016" to the timer Aj register. 7721 Group User's Manual 8-37 TIMER A 8.6 Pulse width modulation (PWM) mode 8.6 Pulse width modulation (PWM) mode In this mode, the timer continuously outputs pulses which have an arbitrary width. (Refer to "Table 8.6.1.") Timers A2 to A4 can be used in this mode. Figure 8.6.1 shows the structures of the timer Aj mode registers and timer Aj registers in the PWM mode. Table 8.6.1 Specifications of PWM mode Specifications Item f2, f16, f64, or f512 Count source q Countdown (operating as an 8-bit or 16-bit pulse width modulator) Count operation q Reload register's contents are reloaded at rising edge of PWM pulse, and counting continues. q A trigger generated during counting does not affect the counting. PWM period/"H" level width <16-bit pulse width modulator> (2 16-1) [s] Period = n : Timer Aj register's set value fi n [s] "H" level width = fi <8-bit pulse width modulator> m : Timer Aj register low-order 8 bits' (m + 1)(2 8-1) set value [s] Period = fi n : Timer Aj register high-order 8 n(m + 1) "H" level width = [s] bits' set value fi q When a trigger is generated. (Note) q Internal or external trigger can be selected by software. When the count start bit is cleared to "0." Count start condition Count stop condition Interrupt request occurrence timing At falling edge of PWM pulse Programmable I/O port or trigger input TAjIN pin's function TAjOUT pin's function Read from timer Aj register Write to timer Aj register PWM pulse output An undefined value is read out. q While counting is stopped When a value is written to the timer Aj register, it is written to both of the reload register and counter. q While counting is in progress When a value is written to the timer Aj register, it is written only to the reload register. (Transferred to the counter at the next reload time.) Note: The trigger is generated with the count start bit = "1." 8-38 7721 Group User's Manual TIMER A 8.6 Pulse width modulation (PWM) mode b7 b6 b5 b4 b3 b2 b1 b0 111 Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) Bit 0 1 2 3 Bit name Operating mode select bits b1 b0 Functions 1 1 : PWM mode At reset RW RW RW RW RW 0 0 Fix this bit to "1" in PWM mode. Trigger select bits b4 b3 0 0 0 : Writing "1" to count start register 0 1 : (TAj IN pin functions as a programmable I/O port.) 1 0 : Falling edge of TAjIN pin's input signal 1 1 : Rising edge of TAjIN pin's input signal 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator b7 b6 0 4 5 6 16/8-bit PWM mode select bit Count source select bits 0 RW 0 0 0 RW RW RW 7 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 (b15) b7 (b8) b0 b7 b0 Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Bit RW Functions At reset 15 to 0 These bits can be set to "000016" to "FFFE16." Undefined WO Assuming that the set value = n, the "H" level width of the PWM pulse output from the n TAjOUT pin is expressed as follows: fi n16 - 1 (PWM pulse period = fi fi: Frequency of count source (f2, f16, f64, or f512) Note: Use the LDM or STA instruction for writing to this register. Read from or write to this register in a unit of 16 bits. ) (b15) b7 (b8) b0 b7 b0 Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Bit Functions At reset Undefined RW WO 7 to 0 These bits can be set to "0016" to "FF16." Assuming that the set value = m, PWM pulse's period output from the TAjOUT pin is 8 expressed as follows: (m + 1)(2 - 1) fi 15 to 8 These bits can be set to "0016" to "FE16." Assuming that the set value = n, the "H" level width of the PWM pulse output from the TAjOUT pin is expressed as follows: n(m + 1) fi Undefined WO fi: Frequency of count source (f2, f16, f64, or f512) Note: Use the LDM or STA instruction for writing to this register. Read from or write to this register in a unit of 16 bits. Fig. 8.6.1 Structures of timer Aj mode registers and timer Aj registers in PWM mode 7721 Group User's Manual 8-39 TIMER A 8.6 Pulse width modulation (PWM) mode 8.6.1 Setting for PWM mode Figures 8.6.2 and 8.6.3 show an initial setting example for registers relevant to the PWM mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Selecting PWM mode and each function b7 b0 111 Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) Selection of PWM mode Trigger select bits b4 b3 00: 0 1 : Writing "1" to count start bit: Internal trigger 1 0 : Falling edge of TAjIN pin's input signal : External trigger 1 1 : Rising edge of TAjIN pin's input signal : External trigger 16/8-bit PWM mode select bit 0 : Operates as 16-bit pulse width modulator 1 : Operates as 8-bit pulse width modulator Count source select bits b7 b6 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 Setting PWM pulse's period and "H" level width q When operating as 16-bit pulse width modulator (b15) b7 (b8) b0 b7 b0 Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Can be set to "000016" to "FFFE16" (n) q When operating as 8-bit pulse width modulator (b15) b7 (b8) b0 b7 b0 Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Can be set to "0016" to "FF16" (m) Can be set to "0016" to "FE16" (n) Note: When operating as 8-bit pulse width modulator Period = (m+1) (28 -1 ) fi "H" level width = n(m+1) fi fi : Frequency of count source However, if n = "0016", the pulse width modulator does not operate and the TAjOUT pin outputs "L" level. At this time, no timer Aj interrupt request occurs. Note: When operating as 16-bit pulse width modulator Period = 216 - 1 fi n fi "H" level width = fi : Frequency of count source However, if n = "000016", the pulse width modulator does not operate and the TAjOUT pin outputs "L" level. At this time, no timer Aj interrupt request occurs. Continue to Figure 8.6.3. Fig. 8.6.2 Initial setting example for registers relevant to PWM mode (1) 8-40 7721 Group User's Manual TIMER A 8.6 Pulse width modulation (PWM) mode From preceding Figure 8.6.2. Setting interrupt priority level b7 b0 Timer Aj interrupt control register (j = 2 to 4) (Addresses 7716 to 7916) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. When external trigger is selected When internal trigger is selected Setting port P5 direction register b7 b0 Setting count start bit to "1" b7 b0 Port P5 direction register (Address D16) TA2IN pin TA3IN pin TA4IN pin Count start register (Address 4016) Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Clear the corresponding bit to "0." Setting count start bit to "1" b7 b0 Count start register (Address 4016) Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Trigger input to TAjIN pin Trigger generated Count tt Fig. 8.6.3 Initial setting example for registers relevant to PWM mode (2) 7721 Group User's Manual 8-41 TIMER A 8.6 Pulse width modulation (PWM) mode 8.6.2 Count source In the PWM mode, the count source select bits (bits 6 and 7 at addresses 5816 to 5A16) select the count source. Table 8.6.2 lists the count source frequency. Table 8.6.2 Count source frequency Count source select bits b7 0 0 1 1 b6 0 1 0 1 Count source f(XIN) = 8 MHz f2 f16 f64 f512 4 MHz 500 kHz 125 kHz 15625 Hz Count source frequency f(XIN) = 16 MHz 8 MHz 1 MHz 250 kHz 31250 Hz f(XIN) = 25 MHz 12.5 MHz 1.5625 MHz 390.625 kHz 48.8281 kHz 8.6.3 Trigger When a trigger is generated, the TAjOUT pin starts outputting PWM pulses. An internal or an external trigger can be selected as that trigger. An internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 5816 to 5A16) are "002" or "012"; an external trigger is selected when the bits are "102" or "112." A trigger generated during outputting of PWM pulses is invalid and it does not affect the pulse output operation. (1) When selecting internal trigger A trigger is generated when "1" is written to the count start bit (address 4016). (2) When selecting external trigger A trigger is generated at the falling edge of the TAjIN pin's input signal when bit 3 at addresses 5816 to 5A16 is "0," or at its rising edge when bit 3 is "1." However, the trigger input is accepted only when the count start bit is "1." When using an external trigger, set the port P5 direction registers' bits which correspond to the TAjIN pins for the input mode. 8-42 7721 Group User's Manual TIMER A 8.6 Pulse width modulation (PWM) mode 8.6.4 Operation in PWM mode When the PWM mode is selected with the operating mode select bits, the TAjOUT pin outputs "L" level. When a trigger is generated, the counter (pulse width modulator) starts counting and the TAjOUT pin outputs a PWM pulse (Notes 1 and 2). The timer Aj interrupt request bit is set to "1" each time the PWM pulse level goes from "H" to "L." The interrupt request bit remains set to "1" until the interrupt request is accepted or the interrupt request bit is cleared to "0" by software. Each time a PWM pulse has been output for one period, the reload register's contents are reloaded and the counter continues counting. The following explains operations of the pulse width modulator. (1) 16-bit pulse width modulator When the 16/8-bit PWM mode select bit is set to "0," the counter operates as a 16-bit pulse width modulator. Figures 8.6.4 and 8.6.5 show operation examples of the 16-bit pulse width modulator. (2) 8-bit pulse width modulator When the 16/8-bit PWM mode select bit is set to "1," the counter is divided into 8-bit halves. Then, the high-order 8 bits operate as an 8-bit pulse width modulator, and the low-order 8 bits operate as an 8-bit prescaler. Figures 8.6.6 and 8.6.7 show operation examples of the 8-bit pulse width modulator. Notes 1: If a value "000016" is set into the timer Aj register when the counter operates as a 16-bit pulse width modulator, the pulse width modulator does not operate and the output from the TAjOUT pin remains "L" level. The timer Aj interrupt request does not occur. Similarly, if a value "0016" is set into the high-order 8 bits of the timer Aj register when the counter operates as an 8-bit pulse width modulator, the same is performed. 2: When the counter operates as an 8-bit pulse width modulator, after a trigger is generated, the TAjOUT pin outputs "L" level which has the same width as "H" level width of the PWM pulse, which was set. After that, the PWM pulse output starts from the TAjOUT pin. 7721 Group User's Manual 8-43 TIMER A 8.6 Pulse width modulation (PWM) mode 1 / fi ! (216 - 1) Count source TAjIN pin's input signal Trigger is not generated by this signal. 1 / fi ! (n) PWM pulse output from TAjOUT pin Timer Aj interrupt request bit fi: Frequency of count source (f2, f16, f64, or f512) Cleared to "0" when interrupt request is accepted or cleared by software. Note: The above applies when reload register (n) = "000316" and an external trigger (rising edge of TAjIN pin's input signal) is selected. Fig. 8.6.4 Operation example of 16-bit pulse width modulator n = Reload register's contents (1 / fi) ! (216 -1) (1 / fi) ! (216 -1) (1 / fi) ! (2 16 -1) Counter contents (Hex.) FFFE16 200016 (216 -1) - n n 000116 Stops counting. TAjIN pin's input signal Restarts counting. Time PWM pulse output from TAjOUT pin fi: Frequency of count source (f2, f16, f64, or f512) "FFFE16" is set to timer Aj register. "000016" is set to timer Aj register. "200016" is set to timer Aj register. When an arbitrary value is set to the timer Aj register after setting "000016" to it, the timing at which the PWM pulse goes "H" depends on the timing at which the new value is set. Note: The above applies when an external trigger (rising edge of TAjIN pin's input signal) is selected. Fig. 8.6.5 Operation example of 16-bit pulse width modulator (when counter value is updated during pulse output) 8-44 7721 Group User's Manual TIMER A 8.6 Pulse width modulation (PWM) mode 1 / fi ! (m+1) ! (28 -1) Count source TAjIN pin's input signal 1 / fi ! (m+1) 8-bit prescaler's underflow signal 1 / fi ! (m+1) ! (n) PWM pulse output from TAjOUT pin Timer Aj interrupt request bit fi: Frequency of count source (f2, f16, f64, or f512) Cleared to "0" when interrupt request is accepted or cleared by software. The 8-bit prescaler counts the count source. The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note: The above applies when the reload register's high-order 8 bits (n) = "0216" and low-order 8 bits (m) = "0216" and an external trigger (falling edge of TAjIN pin input signal) is selected. Fig. 8.6.6 Operation example of 8-bit pulse width modulator 7721 Group User's Manual 8-45 Prescaler's contents (Hex.) Counter's contents (Hex.) 8-46 (1 / fi) ! (m+1) ! (28 -1) (1 / fi) ! (m+1) ! (28 -1) (1 / fi) ! (m + 1) ! (28 -1) Time TIMER A Count source TAjIN pin's input signal 0216 0016 8.6 Pulse width modulation (PWM) mode 0A16 0416 0116 Time Stops counting. Restarts counting. Fig. 8.6.7 Operation example of 8-bit pulse width modulator (when counter value is updated during pulse output) "040216" is set to timer Aj register. "000216" is set to timer Aj register. "0A0216" is set to timer Aj register. m: Contents of reload register's low-order 8 bits 7721 Group User's Manual PWM pulse output from TAjOUT pin fi: Frequency of count source (f2, f16, f64, or f512) When an arbitrary value is set to the timer Aj register after setting "0016" to it, the timing at which the PWM pulse level goes "H" depends on the timing at which the new value is set. Note: The above applies when an external trigger (falling edge of TAjIN pin's input signal) is selected. TIMER A 8.6 Pulse width modulation (PWM) mode [Precautions for PWM mode] 1. If the count start bit is cleared to "0" while outputting PWM pulses, the counter stops counting. When the TAjOUT pin was outputting "H" level at that time, the output level becomes "L" and the timer Aj interrupt request bit is set to "1." When the TAjOUT pin was outputting "L" level, the output level does not change and a timer Aj interrupt request does not occur. 2. When the timer's operating mode is set by one of the following procedures, the timer Aj interrupt request bit is set to "1." qWhen the PWM mode is selected after reset qWhen the operating mode is switched from the timer mode to the PWM mode qWhen the operating mode is switched from the event counter mode to the PWM mode Accordingly, when using the timer Aj interrupt (interrupt request bit), be sure to clear the timer Aj interrupt request bit to "0" after the above setting. 7721 Group User's Manual 8-47 TIMER A 8.6 Pulse width modulation (PWM) mode MEMORANDUM 8-48 7721 Group User's Manual CHAPTER 9 TIMER B 9.1 Overview 9.2 Block description 9.3 Timer mode [Precautions for timer mode] 9.4 Event counter mode [Precautions for event counter mode] 9.5 Pulse period/Pulse width measurement mode [Precautions for pulse period/pulse width measurement (PWM) mode] TIMER B 9.1 Overview 9.2 Block description 9.1 Overview Timer B consists of three counters, Timers B0 to B2, each equipped with a 16-bit reload function. Timers B0 to B2 operate independently of one another. Timer B has three operating modes listed below. Timers B0 and B1 have selective three operating modes listed below. Timer B2 operates only in the timer mode. (1) Timer mode (Timers B0 to B2) The timer counts an internally generated count source. (2) Event counter mode (Timers B0 and B1) The timer counts an external signal. (3) Pulse period/Pulse width measurement mode (Timers B0 and B1) The timer measures an external signal's pulse period or pulse width. In this chapter, Timer Bi (i = 0 to 2) indicates Timers B0 to B2. Timer Bj (j = 0, 1) indicates Timers B0 and B1; this is used when the timer B's input/output pins are used etc. (Hereafter, input/output pins are called I/O pins.) 9.2 Block description Figure 9.2.1 shows the block diagram of Timer B. Explanation of registers relevant to Timer B is described below. Count source select bits Data bus (odd) Data bus (even) (Low-order 8 bits) Timer Bi reload register (16) (High-order 8 bits) f2 f 16 f 64 f 512 Timer mode Pulse period/Pulse width measurement mode TBj IN Polarity switching and edge pulse generating circuit Event counter mode Timer Bi counter (16) Timer Bi interrupt request bit Timer Bj overflow flag (Valid in pulse period/pulse width measurement mode) Count start bit Counter reset circuit i = 0-2, j = 0, 1 Fig. 9.2.1 Block diagram of Timer B 9-2 7721 Group User's Manual TIMER B 9.2 Block description 9.2.1 Counter and reload register (timer Bi register) Each of timer Bi counter and reload register consists of 16 bits and has the following functions. (1) Functions in timer mode and event counter mode Countdown in the counter is performed each time the count source is input. The reload register is used to store the initial value of the counter. When a counter underflow occurs, the reload register's contents are reloaded into the counter. A value is set to the counter and reload register by writing the value to the timer Bi register. Table 9.2.1 lists the memory assignment of the timer Bi register. The value written into the timer Bi register when the counting is not in progress is set to the counter and reload register. The value written into the timer Bi register when the counting is in progress is set only to the reload register. In this case, the reload register's updated contents are transferred to the counter when the next underflow occurs. The counter value is read out by reading out the timer Bi register. Note: When reading from or writing to the timer Bi register, perform it in a unit of 16 bits. For more information about the value obtained by reading the timer Bi register, refer to "[Precautions for timer mode]" and "[Precautions for event counter mode]." (2) Functions in pulse period/pulse width measurement mode Countup in the counter is performed each time the count source is input. The reload register is used to retain the pulse period or pulse width measurement result. When a valid edge is input to the TBjIN pin, the counter value is transferred to the reload register. In this mode, the value obtained by reading the timer Bj register is the reload register's contents, so that the measurement result is obtained. Note: When reading from the timer Bj register, perform it in a unit of 16 bits. Table 9.2.1 Memory assignment of timer Bi registers Timer Bi register Timer B0 register Timer B1 register Timer B2 register High-order byte Address 5116 Address 5316 Address 5516 Low-order byte Address 5016 Address 5216 Address 5416 Note: At reset, the contents of the timer Bi register are undefined. 7721 Group User's Manual 9-3 TIMER B 9.2 Block description 9.2.2 Count start register This register is used to start and stop counting. Each bit of this register corresponds to each timer. Figure 9.2.2 shows the structure of the count start register. b7 b6 b5 b4 b3 b2 b1 b0 Count start register (Address 4016) Bit 0 1 2 3 4 5 6 7 Bit name Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit Functions 0 : Stop counting 1 : Start counting At reset RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 : Bits 0 to 4 are not used for Timer B. Fig. 9.2.2 Structure of count start register 9-4 7721 Group User's Manual TIMER B 9.2 Block description 9.2.3 Timer Bi mode register Figure 9.2.3 shows the structure of the timer Bi mode register. The operating mode select bits are used to select the operating mode of Timer Bi. Bits 2, 3, and bits 5 to 7 have different functions according to the operating mode. These bits are described in the paragraph of each operating mode. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Bit 0 Bit name Operating mode select bits b1 b0 Functions 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/Pulse width measurement mode 1 1 : Do not select. At reset RW RW 0 1 0 RW 2 3 4 5 6 7 These bits have different functions according to the operating mode. 0 0 RW RW Nothing is assigned. These bits have different functions according to the operating mode. Undefined Undefined - RO (Note) RW RW 0 0 Note: Bit 5 is invalid in the timer and event counter modes; its value is undefined at reading. Fig. 9.2.3 Structure of timer Bi mode register 7721 Group User's Manual 9-5 TIMER B 9.2 Block description 9.2.4 Timer Bi interrupt control register Figure 9.2.4 shows the structure of the timer Bi interrupt control register. For details about interrupts, refer to "CHAPTER 7. INTERRUPTS." b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C16) Bit 0 Bit name Interrupt priority level select bits b2 b1 b0 Functions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level 0 : No interrupt requested 1 : Interrupt requested At reset RW RW 0 1 0 RW 2 0 RW 3 7 to 4 Interrupt request bit Nothing is assigned. 0 Undefined RW - Fig. 9.2.4 Structure of timer Bi interrupt control register (1) Interrupt priority level select bits (bits 2 to 0) These bits select a timer Bi interrupt's priority level. When using timer Bi interrupts, select one of the priority levels (1 to 7). When a timer Bi interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable bit (I) = "0.") To disable timer Bi interrupts, set these bits to "0002" (level 0). (2) Interrupt request bit (bit 3) This bit is set to "1" when a timer Bi interrupt request occurs. This bit is automatically cleared to "0" when the timer Bi interrupt request is accepted. This bit can be set to "1" or cleared to "0" by software. 9-6 7721 Group User's Manual TIMER B 9.2 Block description 9.2.5 Port P5 direction register Input pins of Timer Bj are multiplexed with port P5. When using these pins as Timer Bj's input pins, set the corresponding bits of the port P5 direction register to "0" to set these port pins for the input mode. Figure 9.2.5 shows the relationship between port P5 direction register and the Timer Bj's input pins. b7 b6 b5 b4 b3 b2 b1 b0 Por t P5 direction register (Address D16) Bit 0 1 2 3 4 5 6 7 Corresponding pin name TA2OUT pin TA2IN pin TA3OUT pin TA3 IN pin TA4OUT pin TA4 IN pin Functions 0 : Input mode 1 : Output mode At reset 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW When using these pins as Timer Bj's input pins, set the corresponding bits to "0 . " TB0 IN pin TB1IN pin : Bits 0 to 5 are not used for Timer B. Fig. 9.2.5 Relationship between port P5 direction register and Timer Bj's input pins 7721 Group User's Manual 9-7 TIMER B 9.3 Timer mode 9.3 Timer mode In this mode, the timer counts an internally generated count source. (Refer to "Table 9.3.1.") Figure 9.3.1 shows the structures of the timer Bi mode register and timer Bi register in the timer mode. Table 9.3.1 Specifications of timer mode Item f2, f16, f64, or f512 Count source Count operation *Countdown *When a counter underflow occurs, reload register's contents are reloaded, and counting continues. 1 n : Timer Bi register's set value (n + 1) When the count start bit is set to "1." When the count start bit is cleared to "0." Programmable I/O port Counter value can be read out. q While counting is stopped When a value is written to the timer Bi register, it is written to both of the reload register and counter. q While counting is in progress When a value is written to the timer Bi register, it is written only to the reload register. (Transferred to the counter at the next reload time.) Specifications Division ratio Count start condition Count stop condition TBjIN pin's function Read from timer Bi register Write to timer Bi register Interrupt request occurrence timing When a counter underflow occurs. 9-8 7721 Group User's Manual TIMER B 9.3 Timer mode b7 b6 b5 b4 b3 b2 b1 b0 ! !!00 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Bit 0 1 2 3 4 5 6 7 Bit name Operating mode select bits b1 b0 Functions 0 0 : Timer mode At reset RW RW RW RW RW 0 0 These bits are invalid in timer mode. 0 0 Nothing is assigned. This bit is invalid in timer mode; its value is undefined at reading. Count source select bits b7 b6 Undefined Undefined - RO RW RW 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 0 0 (b15) b7 (b8) b0 b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) Bit Functions At reset RW 15 to 0 These bits can be set to "000016" to "FFFF16." Undefined RW Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Note: Read from or write to this register in a unit of 16 bits. Fig. 9.3.1 Structures of timer Bi mode register and timer Bi register in timer mode 7721 Group User's Manual 9-9 TIMER B 9.3 Timer mode 9.3.1 Setting for timer mode Figure 9.3.2 shows an initial setting example for registers relevant to the timer mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Selecting timer mode and count source b7 b0 ! !! 0 0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Selection of timer mode Count source select bits b7 b6 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 !: It may be either "0" or "1." Setting division ratio (b15) b7 (b8) b0 b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) Can be set to "000016" to "FFFF16" (n). Note: The counter divides the count source by (n + 1). Setting interrupt priority level b7 b0 Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C16) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Setting count start bit to "1" b7 b0 Count start register (Address 4016) Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit Count Starts Fig. 9.3.2 Initial setting example for registers relevant to timer mode 9-10 7721 Group User's Manual TIMER B 9.3 Timer mode 9.3.2 Count source In the timer mode, the count source select bits (bits 6 and 7 at addresses 5B16 to 5D16) select the count source. Table 9.3.2 lists the count source frequency. Table 9.3.2 Count source frequency Count source select bits b7 0 0 1 1 b6 0 1 0 1 Count source f(XIN) = 8 MHz f2 f16 f64 f512 4 MHz 500 kHz 125 kHz 15625 Hz Count source frequency f(XIN) = 16 MHz 8 MHz 1 MHz 250 kHz 31250 Hz f(XIN) = 25 MHz 12.5 MHz 1.5625 MHz 390.625 kHz 48.8281 kHz 7721 Group User's Manual 9-11 TIMER B 9.3 Timer mode 9.3.3 Operation in timer mode When the count start bit is set to "1," the counter starts counting of the count source. When a counter underflow occurs, the reload register's contents are reloaded, and counting continues. The timer Bi interrupt request bit is set to "1" at the underflow in . The interrupt request bit remains set to "1" until the interrupt request is accepted or the interrupt request bit is cleared to "0" by software. Figure 9.3.3 shows an example of operation in the timer mode. n = Reload register's contents FFFF16 Counter contents (Hex.) Starts counting. 1 / fi ! (n+1) Stops counting. n Restarts counting. 000016 Time Set to "1" by software. Cleared to "0" by software. Set to "1" by software. Count start bit Timer Bi interrupt request bit fi = frequency of count source (f2, f16, f64, f512) Cleared to "0" when interrupt request is accepted or cleared by software. Fig. 9.3.3 Example of operation in timer mode 9-12 7721 Group User's Manual TIMER B 9.3 Timer mode [Precautions for timer mode] While counting is in progress, by reading the timer Bi register, the counter value can be read out at any timing. However, if the timer Bi register is read at the reload timing shown in Figure 9.3.4, the value "FFFF16" is read out. If reading is performed in the period from when a value is set into the timer Bi register with the counter stopped until the counter starts counting, the set value is correctly read out. Reload Counter value (Hex.) 2 1 0 n n-1 Read value (Hex.) 2 1 0 FFFF n - 1 Time n = Reload register's contents Fig. 9.3.4 Reading timer Bi register 7721 Group User's Manual 9-13 TIMER B 9.4 Event counter mode 9.4 Event counter mode In this mode, the timer counts an external signal. (Refer to "Table 9.4.1.") Figure 9.4.1 shows the structures of the timer Bj mode register and the timer Bj register in the event counter mode. Table 9.4.1 Specifications of event counter mode Specifications Item *External signal input to the TBjIN pin Count source *The count source's valid edge can be selected from the falling edge, the rising edge, and both of the falling and rising edges by software. Count operation *Countdown *When a counter underflow occurs, reload register's contents are reloaded, and counting continues. Division ratio Count start condition Count stop condition 1 (n + 1) n : Timer Bj register's set value When the count start bit is set to "1." When the count start bit is cleared to "0." Interrupt request occurrence timing When a counter underflow occurs. Count source input TBjIN pin's function Read from timer Bj register Write to timer Bj register Counter value can be read out. q While counting is stopped When a value is written to the timer Bj register, it is written to both of the reload register and counter. q While counting is in progress When a value is written to the timer Bj register, it is written only to the reload register. (Transferred to the counter at the next reload time.) 9-14 7721 Group User's Manual TIMER B 9.4 Event counter mode b7 b6 b5 b4 b3 b2 b1 b0 !!! 01 Timer Bj mode register (j = 0, 1) (Addresses 5B16, 5C16) Bit 0 1 2 Bit name Operating mode select bits b1 b0 Functions 0 1 : Event counter mode At reset RW RW RW RW 0 0 Count polarity select bits b3 b2 0 3 0 0 : Count at falling edge of external signal 0 1 : Count at rising edge of external signal 1 0 : Counts at both falling and rising edges of external signal 1 1 : Do not select. Nothing is assigned. This bit is invalid in event counter mode; its value is undefined at reading. These bits are invalid in event counter mode. 0 RW 4 Undefined -- 5 6 7 Undefined RO RW RW 0 0 (b15) b7 (b8) b0 b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Bit Functions At reset Undefined RW RW 15 to 0 These bits can be set to "000016" to "FFFF16." Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Note: Read from or write to this register in a unit of 16 bits. Fig. 9.4.1 Structures of timer Bj mode register and timer Bj register in event counter mode 7721 Group User's Manual 9-15 TIMER B 9.4 Event counter mode 9.4.1 Setting for event counter mode Figure 9.4.2 shows an initial setting example for registers relevant to the event counter mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Selecting event counter mode and count polarity b7 b0 !!! 01 Timer Bj mode register (j = 0, 1) (Addresses 5B16, 5C16) Selection of event counter mode Count polarity select bits b3 b2 0 0 1 1 0 : Counts at falling edge of external signal. 1 : Counts at rising edge of external signal. 0 : Counts at both of falling and rising edges of external signal. 1 : Do not select. !: It may be "0" or "1." Setting division ratio (b15) b7 (b8) b0 b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Can be set to "000016" to "FFFF16" (n). Note: The counter divides the count source by (n + 1). Setting interrupt priority level b7 b0 Timer Bj interrupt control register (j = 0, 1) (Addresses 7A16, 7B16) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Setting port P5 direction register b7 b0 Port P5 direction register (Address D16) TB0IN pin TB1IN pin Clear the corresponding bit to "0." Setting count start bit to "1" b7 b0 Count start register (Address 4016) Count starts Timer B0 count start bit Timer B1 count start bit Fig. 9.4.2 Initial setting example for registers relevant to event counter mode 9-16 7721 Group User's Manual TIMER B 9.4 Event counter mode 9.4.2 Operation in event counter mode When the count start bit is set to "1," the counter starts counting of the count source's valid edges. When a counter underflow occurs, the reload register's contents are reloaded, and counting continues. The timer Bj interrupt request bit is set to "1" at the underflow in . The interrupt request bit remains set to "1" until the interrupt request is accepted or the interrupt request bit is cleared to "0" by software. Figure 9.4.3 shows an example of operation in the event counter mode. n = Reload register's contents FFFF16 Counter contents (Hex.) Starts counting. Stops counting. n Restarts counting . 000016 Time Set to "1" by software. Cleared to "0" by software. Set to "1" by software. Count start bit Timer Bj interrupt request bit Cleared to "0" when interrupt request is accepted or cleared by software. Fig. 9.4.3 Example of operation in event counter mode 7721 Group User's Manual 9-17 TIMER B 9.4 Event counter mode [Precautions for event counter mode] While counting is in progress, by reading the timer Bj register, the counter value can be read out at any timing. However, if the timer Bj register is read at the reload timing shown in Figure 9.4.4, the value "FFFF16" is read out. If reading is performed in the period from when a value is set into the timer Bj register with the counter stopped until the counter starts counting, the set value is correctly read out. Reload Counter value (Hex.) 2 1 0 n n-1 Read value (Hex.) 2 1 0 FFFF n - 1 Time n = Reload register's contents Fig. 9.4.4 Reading timer Bj register 9-18 7721 Group User's Manual TIMER B 9.5 Pulse period/Pulse width measurement mode 9.5 Pulse period/Pulse width measurement mode In this mode, the timer measures an external signal's pulse period or pulse width. (Refer to "Table 9.5.1.") Timers B0 and B1 can be used in this mode. Figure 9.5.1 shows the structures of the timer Bj mode register and timer Bj register in the pulse period/pulse width measurement mode. q Pulse period measurement The timer measures the pulse period of the external signal that is input to the TBjIN pin. q Pulse width measurement The timer measures the pulse width ("L" level and "H" level widths) of the external signal that is input to the TBjIN pin. Table 9.5.1 Specifications of pulse period/pulse width measurement mode Item Specifications Count source f2, f16, f64, or f512 Count operation q Countup q Counter value is transferred to the reload register at valid edge of measurement pulse, and counting continues after clearing the counter value to "000016." Count start condition When the count start bit is set to "1." Count stop condition When the count start bit is cleared to "0." Interrupt request occurrence timing q When valid edge of measurement pulse is input (Note 1). q When a counter overflow occurs (Timer Bj overflow flagV is set to "1" simultaneously.) Measurement pulse input The value obtained by reading timer Bj register is the reload register's contents (Measurement result) (Note 2). Invalid TBjIN pin's function Read from timer Bj register Write to timer Bj register Timer Bj overflow flagV: The bit used to identify the source of an interrupt request occurrence. Notes 1: No interrupt request occurs when the first valid edge is input after the counter starts counting. 2: The value read out from the timer Bj register is undefined after the counter starts counting until the second valid edge is input. 7721 Group User's Manual 9-19 TIMER B 9.5 Pulse period/Pulse width measurement mode b7 b6 b5 b4 b3 b2 b1 b0 10 Timer Bj mode register (j = 0, 1) (Addresses 5B16, 5C16) Bit 0 1 2 Bit name Operating mode select bits b1 b0 Functions 1 0 : Pulse period/Pulse width measurement mode b3 b2 At reset RW RW RW RW 0 0 0 Measurement mode select bits 3 0 0 : Pulse period measurement (Interval between falling edges of measurement pulse) 0 1 : Pulse period measurement (Interval between rising edges of measurement pulse) 1 0 : Pulse width measurement (Interval from a falling edge to a rising edge, and from a rising edge to a falling edge of measurement pulse) 1 1 : Do not select. 0 RW 4 5 6 7 Nothing is assigned. Timer Bj overflow flag (Note) Count source select bits 0 : No overflow 1 : Overflowed b7 b6 Undefined Undefined - RO RW RW 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 0 0 Note: The timer Bj overflow flag is cleared to "0" at the next count timing of the count source when a value is written to the timer Bj mode register with the count start bit = "1." (b15) b7 (b8) b0 b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Bit Functions At reset Undefined RW RO 15 to 0 The measurement result of pulse period or pulse width is read out. Note: Read from this register in a unit of 16 bits. Fig. 9.5.1 Structures of timer Bj mode register and timer Bj register in pulse period/pulse width measurement mode 9-20 7721 Group User's Manual TIMER B 9.5 Pulse period/Pulse width measurement mode 9.5.1 Setting for pulse period/pulse width measurement mode Figure 9.5.2 shows an initial setting example for registers relevant to the pulse period/pulse width measurement mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Selecting pulse period/pulse width measurement mode and each function b7 b0 10 Timer Bj mode register (i = 0, 1) (Addresses 5B16, 5C16) Selection of pulse period/pulse width measurement mode Measurement mode select bits b3 b2 0 0 : Pulse period measurement (Interval between falling edges of measurement pulse) 0 1 : Pulse period measurement (Interval between rising edges of measurement pulse) 1 0 : Pulse width measurement 1 1 : Do not select. Timer Bj overflow flag (Note) 0: No overflow 1: Overflowed Count source select bits b7 b6 0 0 1 1 0 : f2 1 : f16 0 : f64 1 : f512 Setting interrupt priority level b7 b0 Timer Bj interrupt control register (j = 0, 1) (Addresses 7A16, 7B16) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Setting port P5 direction register b7 b0 Port P5 direction register (Address D16) TB0IN pin TB1IN pin Clear the corresponding bit to "0." Setting count start bit to "1" b7 b0 Count start register (Address 4016) Timer B0 count start bit Timer B1 count start bit Count starts Note: The timer Bj overflow flag is a read-only bit. This bit is undefined after reset. When a value is written to the timer Bj mode register with the count start bit = "1," this bit is cleared to "0" at the next count timing of the count source. Fig. 9.5.2 Initial setting example for registers relevant to pulse period/pulse width measurement mode 7721 Group User's Manual 9-21 TIMER B 9.5 Pulse period/Pulse width measurement mode 9.5.2 Count source In the pulse period/pulse width measurement mode, the count source select bits (bits 6 and 7 at addresses 5B16 and 5C16) select the count source. Table 9.5.2 lists the count source frequency. Table 9.5.2 Count source frequency Count source select bits b7 0 0 1 1 b6 0 1 0 1 f2 f16 f64 f512 Count source f(XIN) = 8 MHz 4 MHz 500 kHz 125 kHz 15625 Hz Count source frequency f(XIN) = 16 MHz 8 MHz 1 MHz 250 kHz 31250 Hz f(XIN) = 25 MHz 12.5 MHz 1.5625 MHz 390.625 kHz 48.8281 kHz 9-22 7721 Group User's Manual TIMER B 9.5 Pulse period/Pulse width measurement mode 9.5.3 Operation in pulse period/pulse width measurement mode When the count start bit is set to "1," the counter starts counting of the count source. The counter value is transferred to the reload register when an valid edge of the measurement pulse is detected. (Refer to section "(1) Pulse period/Pulse width measurement.") The counter value is cleared to "000016" after the transfer in , and the counter continues counting. The timer Bj interrupt request bit is set to "1" when the counter value is cleared to "000016" in (Note). The interrupt request bit remains set to "1" until the interrupt request is accepted or the interrupt request bit is cleared to "0" by software. The timer repeats operations to above. Note: No timer Bj interrupt request occurs when the first valid edge is input after the counter starts counting. (1) Pulse period/Pulse width measurement The measurement mode select bits (bits 2 and 3 at addresses 5B16 and 5C16) specify whether the pulse period of an external signal is measured or its pulse width is done. Table 9.5.3 lists the relationship between the measurement mode select bits and the pulse period/pulse width measurements. Make sure that the measurement pulse interval from the falling edge to the rising edge, and vice versa are two cycles of the count source or more. Additionally, use software to identify whether the measurement result indicates the "H" level or the "L" level width. Table 9.5.3 Relationship between measurement mode select bits and pulse period/pulse width measurements b3 0 0 1 b2 0 1 0 Pulse period/Pulse width measurement Pulse period measurement Pulse width measurement Measurement interval (Valid edges) From falling edge to falling edge (Falling edges) From rising edge to rising edge (Rising edges) From falling edge to rising edge, and vice versa (Falling and rising edges) (2) Timer Bj overflow flag A timer Bj interrupt request occurs when a measurement pulse's valid edge is input or a counter overflow occurs. The timer Bj overflow flag is used to identify the cause of the interrupt request, that is, whether it is an overflow occurrence or a valid edge input. The timer Bj overflow flag is set to "1" by an overflow. Accordingly, the cause of the interrupt request occurrence is identified by checking the timer Bj overflow flag in the interrupt routine. When a value is written to the timer Bj mode register with the count start bit = "1," the timer Bj overflow flag is cleared to "0" at the next count timing of the count source The timer Bj overflow flag is a read-only bit. Use the timer Bi interrupt request bit to detect the overflow timing. Do not use the timer Bi overflow flag for this detection. Figure 9.5.3 shows the operation during pulse period measurement. Figure 9.5.4 shows the operation during pulse width measurement. 7721 Group User's Manual 9-23 TIMER B 9.5 Pulse period/Pulse width measurement mode Count source Measurement pulse Reload register Counter Transfer timing Timing at which counter is cleared to "000016" Transferred (undefined value) Transferred (measured value) Count start bit Timer Bj interrupt request bit Cleared to "0" when interrupt request is accepted or cleared by software. Timer Bj overflow flag Counter is initialized by completion of measurement. Counter overflow. Note: The above applies when measurement is performed for an interval from one falling edge to the next falling edge of the measurement pulse. Fig. 9.5.3 Operation during pulse period measurement Count source Measurement pulse Transferred (undefined value) Reload register Counter Transfer timing Timing at which counter is cleared to "000016" Transferred Transferred (measured (measured value) value) Transferred (measured value) Count start bit Timer Bj interrupt request bit Cleared to "0" when interrupt request is accepted or cleared by software. Timer Bj overflow flag Counter is initialized by completion of measurement. Counter overflow. Fig. 9.5.4 Operation during pulse width measurement 9-24 7721 Group User's Manual TIMER B 9.5 Pulse period/Pulse width measurement mode [Precautions for pulse period/pulse width measurement mode] 1. A timer Bj interrupt request is generated by the following sources: q Input of measured pulse's valid edge q Counter overflow When the overflow generates the interrupt request, the timer Bj overflow flag is set to "1." 2. After reset, the timer Bj overflow flag is undefined. When a value is written to the timer Bj mode register with the count start bit = "1," this flag is cleared to "0" at the next count timing of the count source. 3. An undefined value is transferred to the reload register when the first valid edge is input after the counter starts counting. In this case, no timer Bj interrupt request occurs. 4. The counter value at start of counting is undefined. Accordingly, a timer Bj interrupt request may be generated by an overflow immediately after the counter starts counting. 5. If the contents of the measurement mode select bits are changed after the counter starts counting, the timer Bj interrupt request bit is set to "1." When the same value which has been set in these bits are written again, the timer Bj interrupt request bit is not changed, that is, the bit retains the state. 6. If the input signal to the TBjIN pin is affected by noise, etc., the counter may not perform the exact measurement. We recommend to verify, by software, that the measurement values are within a constant range. 7721 Group User's Manual 9-25 TIMER B 9.5 Pulse period/Pulse width measurement mode MEMORANDUM 9-26 7721 Group User's Manual CHAPTER 10 REAL-TIME OUTPUT 10.1 10.2 10.3 10.4 Overview Block description Setting of real-time output Real-time output operation REAL-TIME OUTPUT 10.1 Overview 10.1 Overview The real-time output has the function of changing the output level of several pins simultaneously at every period of the timer. Figure 10.1.1 shows the block diagram of real-time output per bit. Real-time output has two operating modes described below. (1) Pulse mode 0 The 8-bit pulse output pins serve for two independent 4-bit outputs. Figure 10.1.2 shows the configuration of real-time output in the pulse mode 0. (2) Pulse mode 1 The 8-bit pulse output pins serve for a 2-bit and a 6-bit outputs. Figure 10.1.3 shows the configuration of real-time output in the pulse mode 1. Timer Aj underflow signal Pulse output data register j T D Q Flip-flop Bit i of port P6 direction register 1 P6i/RTP0k, P6i/RTP1k 0 Data bus Port P6i latch Waveform output select bit j * i = 0-7 * j = 0, 1 * k = 0-3 Fig. 10.1.1 Block diagram of real-time output per bit 10-2 7721 Group User's Manual REAL-TIME OUTPUT 10.1 Overview Pulse output data register 0 b7 b0 Timer A0 DTQ T DQ T DQ DTQ a a a a a P60/RTP00 P61/RTP01 P62/RTP02 P63/RTP03 Port P6i direction register 1 Port P6i latch (i = 0-7) 0 Data bus (even) Bit 0 of waveform output select bits Pulse output data register 1 b7 b0 Timer A1 T DQ DTQ T DQ T DQ a a a a P64/RTP10 P65/RTP11 P66/RTP12 P67/RTP13 Bit 1 of waveform output select bits Fig. 10.1.2 Configuration of real-time output in pulse mode 0 Pulse output data register 0 b7 b0 Timer A0 T DQ T DQ a a P60/RTP00 P61/RTP01 Bit 0 of waveform output select bits Data bus (even) Pulse output data register 1 b7 b0 Timer A1 a T DQ T DQ T DQ T DQ T DQ T DQ Port P6i direction register 1 Port P6i latch (i = 0-7) a a a a a a P62/RTP02 P63/RTP03 P64/RTP10 P65/RTP11 P66/RTP12 P67/RTP13 0 Bit 1 of waveform output select bits Fig. 10.1.3 Configuration of real-time output in pulse mode 1 7721 Group User's Manual 10-3 REAL-TIME OUTPUT 10.2 Block description 10.2 Block description Relevant registers to real-time output are described below. 10.2.1 Real-time output control register Figure 10.2.1 shows the structure of the real-time output control register. b7 b6 b5 b4 b3 b2 b1 b0 Real-time output control register (Address 6216) Bit 0 1 2 Bit name Waveform output select bits Functions See the following Table. At reset RW RW RW RW 0 0 Pulse output mode select bit 0 : Pulse mode 0 1 : Pulse mode 1 0 7 to 3 Nothing is assigned. The value is "0" at reading. Undefined - Note: When using the P60-P67 pins as the pulse output pins for real-time output, set the corresponding bits of the port P6 direction register (address 1016) to "1." b1 b0 00 P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 01 P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 10 P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 11 P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Port Port RTP RTP When pulse mode 0 is selected Port RTP Port RTP When pulse mode 1 is selected P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Port P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Port P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 RTP P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 RTP Port RTP Port RTP Port : This functions as a programmable I/O port. RTP : This functions as a pulse output pin. Fig. 10.2.1 Structure of real-time output control register 10-4 7721 Group User's Manual REAL-TIME OUTPUT 10.2 Block description 10.2.2 Pulse output data registers 0 and 1 Figure 10.2.2 shows the structure of the pulse output data registers 0 and 1. The bit position of the RTP02 and RTP03 pulse output data bits differs according to the pulse mode. Before setting the pulse output data registers 0 and 1, set of the pulse output mode select bit (bit 2 at address 6216). The data written into the pulse output data registers 0 and 1 is output from the corresponding pulse output pins every underflow of Timers A0 and A1. b7 b6 b5 b4 b3 b2 b1 b0 Pulse output data register 0 (Address 1A16) Bit 0 1 2 3 7 to 4 Bit name RTP00 pulse output data bit RTP01 pulse output data bit RTP02 pulse output data bit (Valid in pulse mode 0) RTP03 pulse output data bit (Valid in pulse mode 0) Nothing is assigned. Functions 0 : "L" level output 1 : "H" level output At reset Undefined Undefined Undefined RW WO WO WO WO Undefined Undefined Note: Use the LDM or STA instruction for writing to this register b7 b6 b5 b4 b3 b2 b1 b0 Pulse output data register 1 (Address 1C16) Bit 0, 1 2 3 4 5 6 7 Bit name Nothing is assigned. RTP02 pulse output data bit (Valid in pulse mode 1) RTP03 pulse output data bit (Valid in pulse mode 1) RTP10 pulse output data bit RTP11 pulse output data bit RTP12 pulse output data bit RTP13 pulse output data bit Functions At reset Undefined RW 0 : "L" level output 1 : "H" level output Undefined WO WO WO WO WO WO Undefined Undefined Undefined Undefined Undefined Note: Use the LDM or STA instruction for writing to this register. Fig. 10.2.2 Structure of pulse output data registers 0 and 1 7721 Group User's Manual 10-5 REAL-TIME OUTPUT 10.2 Block description 10.2.3 Port P6 direction register The pulse output pins are shared with port P6. When using these pins as pulse output pins of real-time output, set the corresponding bits of the port P6 direction register to "1" to set these ports for the output mode. Figure 10.2.3 shows the relationship between the port P6 direction register and the pulse output pins. b7 b6 b5 b4 b3 b2 b1 b0 Port P6 direction register (Address 1016) Bit 0 1 2 3 4 5 6 7 RTP00 pin RTP01 pin RTP02 pin RTP03 pin RTP10 pin RTP11 pin RTP12 pin RTP13 pin Bit name Functions 0 : Input mode 1 : Output mode When using these pins as pulse output pins, set the corresponding bits to "0." At reset RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Note: When setting these bits to "0," the corresponding pins serve as input port (floated) regardless of the state of the waveform output select bits (bits 0 and 1 at address 6216). Fig. 10.2.3 Relationship between port P6 direction register and pulse output pins After reset, the state of the port P6 pins are floated since these pins are in the input mode. The output levels of the pulse output pins are undefined until Timer A0 or A1 underflows first after the data for the timer is written. Because the pulse output data registers 0 and 1 are undefined after reset. When these conditions should be avoided, follow the procedure "Processing of avoiding undefined output before starting pulse output" in Figures 10.3.1 and 10.3.2. When reading the port P6 register (address E16), the output values of the real time output pins can be read out. 10.2.4 Timers A0 and A1 The data written into the pulse output registers 0 and 1 is output from the pulse output pins every underflow of Timer A0 or A1. Refer to section "8.3 Timer mode" for the setting of Timers A0 and A1. 10-6 7721 Group User's Manual REAL-TIME OUTPUT 10.3 Setting of real-time output 10.3 Setting of real-time output Figures 10.3.1 to 10.3.3 show an initial setting example for registers relevant to the real-time output. Note that when using interrupts, set up to enable the interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Processing of avoiding undefined output before starting pulse output (Note) b7 b0 Port P6 register (Address E16) RTP00 RTP01 RTP02 RTP03 RTP10 RTP11 RTP12 RTP13 Set to initial output level of real-time output 0 : "L" level 1 : "H" level Note: This processing can be neglected if the system is not affected by undefined output. Setting port P6 direction register b7 b0 Port P6 direction register (Address 1016) RTP00 RTP01 RTP02 RTP03 RTP10 RTP11 RTP12 RTP13 Set the bits corresponding to the selected pulse output pins to "1." Setting pulse output mode b7 b0 00 Real-time output control register (Address 6216) P60-P67 pins functions as the programmable I/O port. Pulse output mode select bit 0 : Pulse mode 0 1 : Pulse mode 1 When pulse mode 0 is selected When pulse mode 1 is selected Setting output data b7 b0 Setting output data b7 b0 Pulse output data register 0 (Address 1A16) RTP00 RTP01 RTP02 RTP03 b7 b0 ! ! 0 : "L" level 1 : "H" level b7 Pulse output data register 0 (Address 1A16) RTP00 0 : "L" level RTP01 1 : "H" level ! : It may be either "0" or "1." b0 ! ! Pulse output data register 1 (Address 1C16) RTP10 RTP11 RTP12 RTP13 Pulse output data register 1 (Address 1C16) RTP02 RTP03 RTP10 RTP11 RTP12 RTP13 0 : "L" level 1 : "H" level 0 : "L" level 1 : "H" level ! : It may be either "0" or "1." Continue to "Figure 10.3.2" Fig. 10.3.1 Initial setting example for registers relevant to real-time output (1) 7721 Group User's Manual 10-7 REAL-TIME OUTPUT 10.3 Setting of real-time output From preceding "Figure 10.3.1" Processing of avoiding undefined output before starting pulse output (Note) b7 b0 00 0 0 0 0 0 0 Timer A0 mode register (Address 5616) Timer A1 mode register (Address 5716) Select of count source f2 (b15) b7 (b8) b0 b7 b0 0016 0016 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Set to "000016" b7 b0 0 0 0 0 Timer A0 interrupt control register (Address 7516) Timer A1 interrupt control register (Address 7616) Interrupt disabled No interrupt request b7 b0 Count start register (Address 4016) Timer A0 count start bit Timer A1 count start bit V When Timer A0 or A1 underflows, the contents of the pulse output data register 0 or 1 are output from the flip-flop. b7 b0 1 : Start counting Count start register (Address 4016) Timer A0 count start bit Timer A1 count start bit Note: This processing can be neglected if the system is not affected by undefined output. 0 : Stop counting Setting Timers A0, A1 b7 b0 0 0 0 0 0 0 Timer A0 mode register (Address 5616) Timer A1 mode register (Address 5716) Count source select bits b7 b6 0 0 1 1 0 : f2 1 : f16 0 : f64 1 : f512 (b15) b7 (b8) b0 b7 b0 0016 0016 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Can be set to "000016"-"FFFF16" (n) b7 b0 0 Timer A0 interrupt control register (Address 7516) Timer A1 interrupt control register (Address 7616) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Continue to "Figure 10.3.3" Fig. 10.3.2 Initial setting example for registers relevant to real-time output (2) 10-8 7721 Group User's Manual REAL-TIME OUTPUT 10.3 Setting of real-time output Continue to "Figure 10.3.2" When pulse mode 0 is selected When pulse mode 1 is selected Setting real-time output port b7 b0 Setting real-time output port b7 b0 0 Real-time output control register (Address 6216) Waveform output select bits b1 b0 1 Real-time output control register (Address 6216) Waveform output select bits b1 b0 0 1 : RTP00-RTP03 1 0 : RTP10-RTP13 1 1 : RTP00-RTP03 and RTP10-RTP13 0 1 : RTP00, RTP01 1 0 : RTP02, RTP03 and RTP10-RTP13 1 1 : RTP00-RTP03 and RTP10-RTP13 Pulse mode 1 Pulse mode 0 Setting count start bit to "1" b7 b0 Count start register (Address 4016) Timer A0 count start bit Timer A1 count start bit Pulse output starts after overflow of Timer A0 or A1 Fig. 10.3.3 Initial setting example for registers relevant to real-time output (3) 7721 Group User's Manual 10-9 REAL-TIME OUTPUT 10.4 Real-time output operation 10.4 Real-time output operation When the timer Ai (i = 0, 1) count start bit is set to "1," the counter starts counting of the count source. The contents of pulse output data register i are output from the pulse output pins at every underflow of Timer Ai. The timer is reloaded with the contents of the reload register and continues counting. The timer Ai interrupt request bit is set to "1" when the counter underflows in . The interrupt request bit retains "1" until the interrupt request is accepted or it is cleared by software. Write the next output data into the pulse output data register i during the timer Ai interrupt routine or after the recognition of the timer Ai interrupt request occurrence. Figure 10.4.1 shows an example of real-time output operation. Counter contents (Hex.) Starts counting 000316 Starts pulse outputting 000016 V1 Undefined V1 V1 V1 V1 V1 Contents of bits 3-0 of pulse output data register 0 RTP03 output RTP02 output RTP01 output RTP00 output Timer A0 interrupt request bit 00112 V2 01102 11002 10012 00112 Undefined Undefined Undefined Undefined V2 V2 V2 V3 V3 V3 V3 V3 V1 : Written by software V2 : To avoid undefined output for these terms, follow the procedure "Processing of avoiding undefined output before starting pulse output" in Figures 10.3.1 and 10.3.2. V3 : Cleared to "0" when interrupt request is accepted or cleared by software. The above figure shows an example of he following conditions: *Pulse mode 0 selected *RTP00-RTP03 selected *Timer A0 register set value n = 000316 Fig. 10.4.1 Example of real-time output operation 10-10 7721 Group User's Manual CHAPTER 11 SERIAL I/O 11.1 Overview 11.2 Block description 11.3 Clock synchronous serial I/O mode [Precautions for clock synchronous serial I/O mode] 11.4 Clock asynchronous serial I/O (UART) mode SERIAL I/O 11.1 Overview 11.1 Overview Serial I/O consists of 2 channels: UART0 and UART1. They each have a transfer clock generating timer for the exclusive use of them and can operate independently. UART0 and UART1 have the same functions. UARTi (i = 0 and 1) has the following 2 operating modes: (1) Clock synchronous serial I/O mode Transmitter and receiver use the same clock as the transfer clock. Transfer data has a length of 8 bits. (2) Clock asynchronous serial I/O (UART) mode Transfer rate and transfer data format can arbitrarily be set. The user can select a transfer data length of 7 bits, 8 bits, or 9 bits. Figure 11.1.1 shows the transfer data formats in each operating mode. qClock synchronous serial I/O mode qUART mode Transfer data length of 8 bits Transfer data length of 7 bits Transfer data length of 8 bits Transfer data length of 9 bits Fig. 11.1.1 Transfer data formats in each operating mode 11-2 7721 Group User's Manual SERIAL I/O 11.2 Block description 11.2 Block description Figure 11.2.1 shows the block diagram of Serial I/O. Registers relevant to Serial I/O are described below. Data bus (odd) Data bus (even) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi receive buffer register RxDi UART Clock synchronous UARTi receive register BRG count source select bits f2 f16 f64 f512 1/16 Receive control circuit Transfer clock BRGi 1 / (n+1) 1/16 UART Clock synchronous Clock synchronous (internal clock selected) Transmit control circuit Transfer clock UARTi transmit register 1/2 Clock synchronous (internal clock selected) TxDi Clock synchronous (external clock selected) D8 D7 D6 D5 D4 D3 D2 D1 D0 CLKi UARTi transmit buffer register CTSi / RTSi n: Values set in UARTi baud rate register (BRGi) Data bus (odd) Data bus (even) Fig. 11.2.1 Block diagram of Serial I/O 7721 Group User's Manual 11-3 SERIAL I/O 11.2 Block description 11.2.1 UARTi transmit/receive mode register Figure 11.2.2 shows the structure of UARTi transmit/receive mode register. The serial I/O mode select bits are used to select a UARTi's operating mode. Bits 4 to 6 are described in section "11.4.2 Transfer data format," and bit 7 is done in section "11.4.8 Sleep mode." b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) Bit 0 Bit name Serial I/O mode select bits b2 b1 b0 Functions 0 0 0 : Serial I/O disabled (P8 functions as a programmable I/O port.) 0 0 1 : Clock synchronous serial I/O mode 0 1 0 : Do not select. 0 1 1 : Do not select. 1 0 0 : UART mode (Transfer data length = 7 bits) 1 0 1 : UART mode (Transfer data length = 8 bits) 1 1 0 : UART mode (Transfer data length = 9 bits) 1 1 1 : Do not select. 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode terminated (Invalid) 1 : Sleep mode selected At reset RW RW 0 1 0 RW 2 0 RW 3 4 5 Internal/External clock select bit Stop bit length select bit (Valid in UART mode) (Note) Odd/Even parity select bit (Valid in UART mode when parity enable bit is "1") (Note) Parity enable bit (Valid in UART mode) (Note) Sleep select bit (Valid in UART mode) (Note) 0 0 0 RW RW RW 6 7 0 0 RW RW Note: Bits 4 to 6 are invalid in the clock synchronous serial I/O mode. (They may be either "0" or "1.") Additionally, fix bit 7 to "0." Fig. 11.2.2 Structure of UARTi transmit/receive mode register 11-4 7721 Group User's Manual SERIAL I/O 11.2 Block description (1) Internal/External clock select bit (bit 3) s Clock synchronous serial I/O mode By clearing this bit to "0" in order to select an internal clock, the clock which is selected with the BRG count source select bits (bits 0 and 1 at addresses 3416, 3C16) becomes the count source of the BRGi (described later). The BRGi's output divided by 2 becomes the transfer clock. Additionally, the transfer clock is output from the CLKi pin. By setting this bit to "1" in order to select an external clock, the clock input to the CLKi pin becomes the transfer clock. s UART mode By clearing this bit to "0" in order to select an internal clock, the clock which is selected with the BRG count source select bits (bits 0 and 1 at addresses 3416, 3C16) becomes the count source of the BRGi (described later). Then, the CLKi pin functions as a programmable I/O port. By setting this bit to "1" in order to select an external clock, the clock input to the CLKi pin becomes the count source of BRGi. Always in the UART mode, the BRGi's output divided by 16 becomes the transfer clock. 7721 Group User's Manual 11-5 SERIAL I/O 11.2 Block description 11.2.2 UARTi transmit/receive control register 0 Figure 11.2.3 shows the structure of UARTi transmit/receive control register 0. For bits 0 and 1, refer to section "11.2.1 (1) Internal/External clock select bit (bit 3)." b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) Bit 0 Bit name BRG count source select bits b1 b0 Functions 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 0 : CTS function selected 1 : RTS function selected 0 : Data present in transmit register (During transmission) 1 : No data present in transmit register (Transmission completed) At reset RW RW RW RW RO 0 1 2 3 CTS/RTS select bit Transmit register empty flag 0 0 1 7 to 4 Nothing is assigned. Undefined - Fig. 11.2.3 Structure of UARTi transmit/receive control register 0 ____ ____ (1) CTS/RTS select bit (bit 2) ____ ____ By clearing this bit to "0" in order to select the CTS function, pins P80 and P84 function as CTS input pins, and the input signal of "L" level to these____ becomes one of the transmission conditions. pins ____ By setting this bit to "1" in order to select the RTS function, pins P80 and P84 become RTS output ____ pins. When the receive enable bit (bit 2 at addresses 3516, 3D16) is "0" (reception disabled), the RTS output pin outputs "H" level. ____ In the clock synchronous serial I/O mode, the output level of the RTS pin becomes "L" when reception conditions are satisfied, and it becomes "H" when reception starts. Note that, when an internal clock ____ is selected____ 3 at addresses 3016, 3816 = "0"), the RTS output is undefined. Accordingly, do not (bit select the RTS function. ____ In the clock asynchronous serial I/O mode, the output level of the RTS pin becomes "L" when the receive enable bit is set to "1." It becomes "H" when reception starts and it becomes "L" when reception is completed. (2) Transmit register empty flag (bit 3) This flag is cleared to "0" when the UARTi transmit buffer register's contents are transferred to the UARTi transmit register. When transmission is completed and the UARTi transmit register becomes empty, this flag is set to "1." 11-6 7721 Group User's Manual SERIAL I/O 11.2 Block description 11.2.3 UARTi transmit/receive control register 1 Figure 11.2.4 shows the structure of UARTi transmit/receive control register 1. For bits 4 to 7, refer to section "11.3.6 Processing on detecting overrun error" and "11.4.7 Processing on detecting error." b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) Bit 0 1 Bit name Transmit enable bit Transmit buffer empty flag Functions 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register (Note 1) 0 : No overrun error 1 : Overrun error detected At reset RW RW RO 0 1 2 Receive enable bit 0 0 RW RO 3 Receive complete flag 4 5 6 7 Overrun error flag 0 0 0 0 RO RO RO RO Framing error flag (Notes 1, 2) 0 : No framing error 1 : Framing error detected (Valid in UART mode) (Notes 1, 2) 0 : No parity error Parity error flag (Valid in UART mode) 1 : Parity error detected (Notes 1, 2) 0 : No error Error sum flag 1 : Error detected (Valid in UART mode) Notes 1: Bit 4 is cleared to "0" when the receive enable bit is cleared to "0" or when the serial I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) are cleared to "0002." Bits 5 and 6 are cleared to "0" when one of the following is performed: *Clearing the receive enable bit to "0" *Reading the low-order byte of the UARTi receive buffer register (addresses 3616, 3E16) out *Clearing the serial I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) to "0002" Bit 7 is cleared to "0" when all of bits 4 to 6 become "0." 2: Bits 5 to 7 are invalid in the clock synchronous serial I/O mode. Fig. 11.2.4 Structure of UARTi transmit/receive control register 1 7721 Group User's Manual 11-7 SERIAL I/O 11.2 Block description (1) Transmit enable bit (bit 0) By setting this bit to "1," UARTi enters the transmission enable state. By clearing this bit to "0" during transmission, UARTi enters the transmission disable state after the transmission which is in progress at that time is completed. (2) Transmit buffer empty flag (bit 1) This flag is set to "1" when data set in the UARTi transmit buffer register is transferred from the UARTi transmit buffer register to the UARTi transmit register. This flag is cleared to "0" when data is set in the UARTi transmit buffer register. (3) Receive enable bit (bit 2) By setting this bit to "1," UARTi enters the reception enable state. By clearing this bit to "0" during reception, UARTi quits the reception immediately and enters the reception disable state. (4) Receive complete flag (bit 3) This flag is set to "1" when data is ready in the UARTi receive register and that is transferred to the UARTi receive buffer register (i.e., when reception is completed). This flag is cleared to "0" when one of the following is performed: *Reading the low-order byte of the UARTi receive buffer register out *Clearing the receive enable bit (bit 2) to "0" *Clearing the serial I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) to "0002." 11-8 7721 Group User's Manual SERIAL I/O 11.2 Block description 11.2.4 UARTi transmit register and UARTi transmit buffer register Figure 11.2.5 shows the block diagram for the transmitter; Figure 11.2.6 shows the structure of UARTi transmit buffer register. Data bus (odd) Data bus (even) D8 SP : Stop bit PAR : Parity bit Parity enabled D7 8-bit UART 9-bit UART Clock sync. D6 D5 D4 D3 D2 D1 D0 UARTi transmit buffer register 9-bit UART UART 2SP SP SP 1SP PAR Parity disabled TxDi Clock sync. 7-bit UART 8-bit UART Clock sync. 7-bit UART UARTi transmit register "0" Fig. 11.2.5 Block diagram for transmitter (b15) b7 (b8) b0 b7 b0 UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16) Bit Functions At reset Undefined Undefined RW WO 8 to 0 Transmit data is set. 15 to 9 Nothing is assigned. - Note: Use the LDM or STA instruction for writing to this register. Fig. 11.2.6 Structure of UARTi transmit buffer register 7721 Group User's Manual 11-9 SERIAL I/O 11.2 Block description Transmit data is set into the UARTi transmit buffer register. Set the transmit data into the low-order byte of this register when the microcomputer operates in the clock synchronous serial I/O mode or when a 7bit or 8-bit length of transfer data is selected in the UART mode. When a 9-bit length of transfer data is selected in the UART mode, set the transmit data into the UARTi transmit buffer register as follows: *Bit 8 of the transmit data into bit 0 of high-order byte of this register. *Bits 7 to 0 of the transmit data into the low-order byte of this register. The transmit data which is set in the UARTi transmit buffer register is transferred to the UARTi transmit register when the transmission conditions are satisfied, and then it is output from the TxDi pin synchronously with the transfer clock. The UARTi transmit buffer register becomes empty when the data which is set in the UARTi transmit buffer register is transferred to the UARTi transmit register. Accordingly, the user can set the next transmit data. When quitting the transmission which is in progress and setting the UARTi transmit buffer register again, follow the procedure described bellow: Clear the serial I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) to "0002" (Serial I/O disabled). Set the serial I/O mode select bits again. Set the transmit enable bit (bit 0 at addresses 3516, 3D16) to "1" (transmission enabled) and set transmit data in the UARTi transmit buffer register. 11-10 7721 Group User's Manual SERIAL I/O 11.2 Block description 11.2.5 UARTi receive register and UARTi receive buffer register Figure 11.2.7 shows the block diagram for the receiver; Figure 11.2.8 shows the structure of UARTi receive buffer register. Data bus (odd) Data bus (even) 0 SP : Stop bit PAR : Parity bit 2SP 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi receive buffer register Parity enabled UART 9-bit UART 8-bit UART 9-bit UART Clock sync. RxDi SP 1SP SP PAR Parity disabled Clock sync. 7-bit UART 8-bit UART Clock sync. 7-bit UART UARTi receive register Fig. 11.2.7 Block diagram for receiver (b15) b7 (b8) b0 b7 b0 UART0 receive buffer register (Addresses 3716, 3616) UART1 receive buffer register (Addresses 3F16, 3E16) Bit Functions At reset Undefined RW RO 8 to 0 Receive data is read out from here. 15 to 9 Nothing is assigned. The value is "0" at reading. 0 - Fig. 11.2.8 Structure of UARTi receive buffer register 7721 Group User's Manual 11-11 SERIAL I/O 11.2 Block description The UARTi receive register is used to convert serial data which is input to the RxDi pin into parallel data. This register takes in the signal input to the RxDi pin in a unit of 1 bit synchronously with the transfer clock. The UARTi receive buffer register is used to read out receive data. When reception is completed, the receive data which is taken in the UARTi receive register is automatically transferred to the UARTi receive buffer register. Note that the contents of the UARTi receive buffer register is updated when the next data is ready in the UARTi receive register before the data which has been transferred to the UARTi receive buffer register is read out. (i.e., an overrun error occurs.) The UARTi receive buffer register is initialized by setting the receive enable bit (bit 2 at addresses 3516, 3D16) to "1" after clearing it to "0." Figure 11.2.9 shows the contents of the UARTi receive buffer register when reception is completed. High-order byte (addresses 3716, 3F16) b7 b0 Low-order byte (addresses 3616, 3E16) b7 b0 In UART mode (Transfer data length : 9 bits) In clock synchronous serial I/O mode In UART mode (Transfer data length : 8 bits) In UART mode (Transfer data length : 7 bits) 0 0 0 0 0 0 0 Receive data (9 bits) 0 0 0 0 0 0 0 Receive data (8 bits) Same value as bit 7 in low-order byte 0 0 0 0 0 0 0 Receive data (7 bits) Same value as bit 6 in low-order byte Fig. 11.2.9 Contents of UARTi receive buffer register when reception is completed 11-12 7721 Group User's Manual SERIAL I/O 11.2 Block description 11.2.6 UARTi baud rate register (BRGi) The UARTi baud rate register (BRGi) is an 8-bit timer exclusively used for UARTi to generate a transfer clock. It has a reload register. Assuming that the value set in the BRGi is "n" (n = "0016" to "FF16"), the BRGi divides the count source frequency by (n + 1). In the clock synchronous serial I/O mode, the BRGi is valid when an internal clock is selected, and the BRGi's output divided by 2 becomes the transfer clock. In the UART mode, the BRGi is always valid, and the BRGi's output divided by 16 becomes the transfer clock. The data which is written to the UARTi baud rate register (BRGi) is written to both the timer and the reload register whether transmission/reception is in progress or not. Accordingly, writing to these register must be performed while transmission/reception is stopped. Figure 11.2.10 shows the structure of the UARTi baud rate register (BRGi); Figure 11.2.11 shows the block diagram of transfer clock generating section. b7 b0 UART0 baud rate register (Address 3116) UART1 baud rate register (Address 3916) Bit Functions At reset Undefined RW WO 7 to 0 Can be set to "0016" to "FF16." Assuming that the set value = n, BRGi divides the count source frequency by (n + 1). Note: Writing to this register must be performed while the transmission/reception halts. Use the LDM or STA instruction for writing to this register. Fig. 11.2.10 Structure of UARTi baud rate register (BRGi) fi fEXT BRGi 1/2 Transmit control circuit Transfer clock for transmit operation Transfer clock for receive operation Receive control circuit fi fEXT 1/16 Transmit control circuit Transfer clock for transmit operation Transfer clock for receive operation BRGi 1/16 Receive control circuit fi : Clock selected by BRG count source select bits (f2, f16, f64, or f512) fEXT : Clock input to CLKi pin (external clock) Fig. 11.2.11 Block diagram of transfer clock generating section 7721 Group User's Manual 11-13 SERIAL I/O 11.2 Block description 11.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers When using UARTi, 2 types of interrupts, which are UARTi transmit and UARTi receive interrupts, can be used. Each interrupt has its corresponding interrupt control register. Figure 11.2.12 shows the structure of UARTi transmit interrupt control and UARTi receive interrupt control registers. For details about interrupts, refer to "CHAPTER 7. INTERRUPTS." b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit interrupt control register (Address 7116) UART0 receive interrupt control register (Address 7216) UART1 transmit interrupt control register (Address 7316) UART1 receive interrupt control register (Address 7416) Bit 0 Bit name Interrupt priority level select bits b2 b1 b0 Functions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level 0 : No interrupt requested 1 : Interrupt requested At reset RW RW 0 1 0 RW 2 0 RW 3 Interrupt request bit 0 Undefined RW 7 to 4 Nothing is assigned. - Fig. 11.2.12 Structure of UARTi transmit interrupt control and UARTi receive interrupt control registers (1) Interrupt priority level select bits (bits 0 to 2) These bits select a priority level of the UARTi transmit interrupt or UARTi receive interrupt. When using UARTi transmit/receive interrupts, select one of the priority levels (1 to 7). When a UARTi transmit/receive interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = "0.") To disable UARTi transmit/receive interrupts, set these bits to "0002" (level 0). (2) Interrupt request bit (bit 3) The UARTi transmit interrupt request bit is set to "1" when data is transferred from the UARTi transmit buffer register to the UARTi transmit register. The UARTi receive interrupt request bit is set to "1" when data is transferred from the UARTi receive register to the UARTi receive buffer register. (However, when an overrun error occurs, it does not change.) Each interrupt request bit is automatically cleared to "0" when its corresponding interrupt request is accepted. This bit can be set to "1" or "0" by software. 11-14 7721 Group User's Manual SERIAL I/O 11.2 Block description 11.2.8 Port P8 direction register I/O pins of UARTi are multiplexed with port P8. When using pins P82 and P86 as serial data input pins (RxDi), set the corresponding bits of the port P8 direction register to "0" to set these pins for the input ____ ____ mode. When using pins P80, P81, P83 to P85 and P87 as I/O pins (CTSi/RTSi, CLKi, TxDi) of UARTi, these pins are forcibly set as I/O pins of UARTi regardless of the port P8 direction register's contents. Figure 11.2.13 shows the relationship between the port P8 direction register and UARTi's I/O pins. For details, refer to the description of each operating mode. b7 b6 b5 b4 b3 b2 b1 b0 Port P8 direction register (Address 1416) Bit 0 1 2 3 4 5 6 7 Corresponding pin CTS0/RTS0 pin Functions 0 : Input mode 1 : Output mode When using pins P82 and P86 as serial data input pins (RxD0, RxD1), set the corresponding bits to "0." At reset RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 CLK0 pin RxD0 pin TxD0 pin CTS1/RTS1 pin CLK1 pin RxD1 pin TxD1 pin Fig. 11.2.13 Relationship between port P8 direction register and UARTi's I/O pins 7721 Group User's Manual 11-15 SERIAL I/O 11.3 Clock synchronous serial I/O mode 11.3 Clock synchronous serial I/O mode Table 11.3.1 lists the performance overview in the clock synchronous serial I/O mode, and Table 11.3.2 lists the functions of I/O pins in this mode. Table 11.3.1 Performance overview in clock synchronous serial I/O mode Item Transfer data format Transfer rate When selecting internal clock When selecting external clock Transmit/Receive control LSB first BRGi's output divided by 2 ____ Functions Transfer data has a length of 8 bits. Maximum 5 Mbps ____ CTS function or RTS function can be selected by software. Table 11.3.2 Functions of I/O pins in clock synchronous serial I/O mode Pin name TxDi (P83, P87) (Note) RxDi (P82, P86) CLKi (P81, P85) ___ ___ Functions Serial data output Serial data input Transfer clock output ____ ____ Method of selection (Dummy data is output when performing only reception.) Port P8 direction register U1's corresponding bit = "0" (Can be used as an I/O port when performing only transmission.) Internal/External clock select bitU2 = "0" ____ ____ Transfer clock input Internal/External clock select bit = "1" CTS/RTS select bitU3 = "0" CTSi/RTSi (P80, P84) CTS input RTS output U1 ____ ____ CTS/RTS select bit = "1" Port P8 direction register : address 1416 Internal/External clock select bitU2: bit 3 at addresses 3016, 3816 ____ ____ CTS/RTS select bitU3: bit 2 at addresses 3416, 3C16 Note: The TxDi pin outputs "H" level until transmission starts after UARTi's operating mode is selected. 11-16 7721 Group User's Manual SERIAL I/O 11.3 Clock synchronous serial I/O mode 11.3.1 Transfer clock (Synchronizing clock) Data transfer is performed synchronously with the transfer clock. For the transfer clock, the user can select whether to generate the transfer clock internally or to input it from the external. The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing only reception, set the transmit enable bit to "1," and set dummy data in the UARTi transmit buffer register in order to make the transmit control circuit active. (1) Internal generation of transfer clock The count source selected with the BRG count source select bits is divided by the BRGi, and the BRGi output is further divided by 2. This is the transfer clock. The transfer clock is output from the CLKi pin. [Setting for relevant registers] *Select an internal clock (bit 3 at addresses 3016, 3816 = "0"). *Select the BRGi's count source (bits 0 and 1 at addresses 3416, 3C16) *Set "division value - 1" (= n; 0016 to FF16) to the BRGi (addresses 3116, 3916). Transfer clock's frequency = fi 2 (n+1) fi: Frequency of BRGi's count source (f2, f16, f64 , f512) *Enable transmission (bit 0 at addresses 3516, 3D16 = "1"). *Set data to the UARTi transmit buffer register (addresses 3216, 3A16) [Pin's state] *A transfer clock is output from the CLKi pin. *Serial data is output from the TxDi pin. (Dummy data is output when performing only reception.) (2) Input of transfer clock from the external A clock input from the CLKi pin is the transfer clock. [Setting for relevant registers] *Select an external clock (bit 3 at addresses 3016, 3816 = "1"). *Enable transmission (bit 0 at addresses 3516, 3D16 = "1"). *Set data to the UARTi transmit buffer register (addresses 3216, 3A16). [Pin's state] *A transfer clock is input from the CLKi pin. *Serial data is output from the TxDi pin. (Dummy data is output when performing only reception.) 7721 Group User's Manual 11-17 SERIAL I/O 11.3 Clock synchronous serial I/O mode 11.3.2 Method of transmission Figure 11.3.1 shows an initial setting example for relevant registers when transmitting. Transmission is started when all of the following conditions ( to ) are satisfied. When an external clock is selected, satisfy conditions to with the following precondition satisfied. ____ ____ By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched. For details, refer to section "11.3.5 Receive operation." When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Figure 11.3.2 shows writing data after start of transmission, and Figure 11.3.3 shows detection of transmit completion. 11-18 7721 Group User's Manual SERIAL I/O 11.3 Clock synchronous serial I/O mode UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) b7 b0 0!!! 001 Clock synchronous serial I/O mode Internal/External clock select bit 0: Internal clock 1: External clock !: It may be "0" or "1." Transmit data is set. UART0 transmit buffer register (Address 3216) UART1 transmit buffer register (Address 3A16) b7 b0 UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 b0 UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 BRG count source select bits b1 b0 1 Transmit enable bit 1: Transmission enabled 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 CTS / RTS select bit 0: CTS function selected 1: RTS function selected (CTS function disabled) Transmission starts. UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) b7 b0 (In the case of selecting the CTS function, transmission starts when the CTSi pin's input level is "L.") Can be set to "0016" to "FF16." V Necessary only when internal clock is selected. UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) b7 b0 Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Fig. 11.3.1 Initial setting example for relevant registers when transmitting 7721 Group User's Manual 11-19 SERIAL I/O 11.3 Clock synchronous serial I/O mode [When not using interrupts] [When using interrupts] A UARTi transmit interrupt request occurs when the UARTi transmit buffer register becomes empty. Checking state of UARTi transmit buffer register UART0 transmit/receive control register 1 (Address 3516 ) UART1 transmit/receive control register 1 (Address 3D16 ) b7 b0 b0 UARTi transmit interrupt 1 Transmit buffer empty flag 0: Data present in transmit buffer register 1: No data present in transmit buffer register (Writing of next transmit data is possible.) Writing of next transmit data UART0 transmit buffer register (Address 3216) UART1 transmit buffer register (Address 3A16) b7 b0 Note : This figure shows the bits and registers required for processing. Refer to "Figures 11.3.5 and 11.3.6" for the change of flag state and the occurrence timing of an interrupt request. Set transmit data here. Fig. 11.3.2 Writing data after start of transmission [When not using interrupts] [When using interrupts] A UARTi transmit interrupt request occurs when the transmission starts. Checking start of transmission UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) b7 b0 UARTi transmit interrupt Interrupt request bit 0: No interrupt requested 1: Interrupt requested (Transmission has started.) Checking completion of transmission UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 b0 Note :This figure shows the bits and registers required for processing. Refer to "Figures 11.3.5 and 11.3.6" for the change of flag state and the occurrence timing of an interrupt request. Transmit register empty flag 0: During transmitting 1: Transmitting completed Processing at completion of transmission Fig. 11.3.3 Detection of transmit completion 11-20 7721 Group User's Manual SERIAL I/O 11.3 Clock synchronous serial I/O mode 11.3.3 Transmit operation When the transmit conditions described in section "11.3.2 Method of transmission" are satisfied in the case of selecting an internal clock, a transfer clock is generated and the following operations are automatically performed after 1 cycle of the transfer clock has passed. When the transmit conditions are satisfied and the external clock is input to the CLKi pin in the case of selecting an external clock, the following operations are automatically performed. *The UARTi transmit buffer register's contents are transferred to the UARTi transmit register. *The transmit buffer empty flag is set to "1." *The transmit register empty flag is cleared to "0." *8 transfer clocks are generated (when an internal clock is selected). *A UARTi transmit interrupt request occurs, and the interrupt request bit is set to "1." The transmit operations are described below: Data in the UARTi transmit register is transmitted from the TxDi pin synchronously with the falling edge of the transfer clock. This data is transmitted bit by bit sequentially beginning with the least significant bit. When 1-byte data has been transmitted, the transmit register empty flag is set to "1." This indicates the completion of transmission. Figure 11.3.4 shows the transmit operation. When an internal clock is selected, when the transmit conditions for the next data are satisfied at completion of the transmission, the transfer clock is generated continuously. Accordingly, when performing transmission continuously, set the next transmit data to the UARTi transmit buffer register during transmission (when the transmit register empty flag = "0"). When the transmit conditions for the next data are not satisfied, the transfer clock stops at "H" level. Figures 11.3.5 and 11.3.6 show examples of transmit timing. b7 b0 UARTi transmit buffer register MSB Transfer clock UARTi transmit register D7 D6 Transmit data LSB D5 D4 D3 D2 D1 D0 D1 D0 D1 D2 D7 D6 D5 D4 D3 D2 D7 D6 D5 D4 D3 D2 D3 D7 D6 D5 D4 *** *** D7 Fig. 11.3.4 Transmit operation 7721 Group User's Manual 11-21 SERIAL I/O 11.3 Clock synchronous serial I/O mode Tc Transfer clock Transmit enable bit Transmit buffer empty flag Data is set in UARTi transmit buffer register. UARTi transmit register CTSi UARTi transmit buffer register. TCLK Stopped because CTSi = "H." Stopped because transmit enable bit = "0." CLKi TENDi TxDi D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Transmit register empty flag UARTi transmit interrupt request bit Cleared to "0" when interrupt request is accepted or cleared by software. The above timing diagram applies when the following conditions are satisfied: q Internal clock selected q CTS function selected TENDi: Next transmit conditions are examined when this signal level is "H." (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc = TCLK = 2(n+1) /fi fi: BRGi count source frequency (f 2, f16, f64, f512) n: Value set in BRGi ____ Fig. 11.3.5 Example of transmit timing (when selecting internal clock, selecting CTS function) Tc Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register. Transmit buffer empty flag UARTi transmit register UARTi transmit buffer register. Stopped because transmit enable bit = "0." CLKi TCLK TENDi TxDi D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Transmit register empty flag UARTi transmit interrupt request bit Cleared to "0" when interrupt request is accepted or cleared by software. The above timing diagram applies when the following conditions are satisfied: q Internal clock selected q CTS function not selected TENDi: Next transmit conditions are examined when this signal level is "H." (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc = TCLK = 2(n+1) /fi fi: BRGi count source frequency (f 2, f16, f64, f512) n: Value set in BRGi ____ Fig. 11.3.6 Example of transmit timing (when selecting internal clock, not selecting CTS function) 11-22 7721 Group User's Manual SERIAL I/O 11.3 Clock synchronous serial I/O mode 11.3.4 Method of reception Figures 11.3.7 and 11.3.8 show initial setting examples for relevant registers when receiving. Reception is started when all of the following conditions ( to ) are satisfied. When an external clock is selected, satisfy conditions to with the following precondition satisfied. ____ ____ By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched. For details, refer to section "11.3.5 Receive operation." When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Figure 11.3.9 shows processing after receive completion. 7721 Group User's Manual 11-23 SERIAL I/O 11.3 Clock synchronous serial I/O mode UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) b7 b0 0! !! 001 Clock synchronous serial I/O mode Internal/External clock select bit 0: Internal clock 1: External clock !: It may be "0" or "1." UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 b0 BRG count source select bits b1 b0 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 CTS / RTS select bit 0: CTS function selected 1: RTS function selected UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) b7 b0 Can be set to 0016 to FF16 . V Necessary only when an internal clock is selected. Continued to Figure 11.3.8 on next page. Fig. 11.3.7 Initial setting example for relevant registers when receiving (1) 11-24 7721 Group User's Manual SERIAL I/O 11.3 Clock synchronous serial I/O mode From preceding Figure 11.3.7 Port P8 direction register (Address 1416) b7 b0 0 0 RXD0 pin RXD1 pin UART0 receive interrupt control register (Address 7216) UART1 receive interrupt control register (Address 7416) b7 b0 Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. UART0 transmit buffer register (Address 3216) UART1 transmit buffer register (Address 3A16) b7 b0 Set dummy data here. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 1 1 Transmit enable bit 1 : Transmission enabled Receive enable bit 1 : Reception enabled Note: Set the receive enable bit and the transmit enable bit to "1" simultaneously. Reception starts. Fig. 11.3.8 Initial setting example for relevant registers when receiving (2) 7721 Group User's Manual 11-25 SERIAL I/O 11.3 Clock synchronous serial I/O mode [When not using interrupts] [When using interrupts] A UARTi receive interrupt request occurs when reception is completed. Checking completion of reception UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 UARTi receive interrupt 1 1 Receive complete flag 0: Reception not completed 1: Reception completed Reading of receive data UART0 receive buffer register (Address 3616) UART1 receive buffer register (Address 3E16) b7 b0 Receive data is read out from here. Checking error UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 1 1 Overrun error flag 0: No overrun error 1: Overrun error detected Processing after reading out receive data Note : This figure shows the bits and registers required for processing. Refer to "Figure 11.3.12" for the change of flag state and the occurrence timing of an interrupt request. Fig. 11.3.9 Processing after receive completion 11-26 7721 Group User's Manual SERIAL I/O 11.3 Clock synchronous serial I/O mode 11.3.5 Receive operation In the case of selecting an internal clock, when the receive conditions described in section "11.3.4 Method of reception" are satisfied, a transfer clock is generated and the reception is started after 1 cycle of the transfer clock has passed. In the case of selecting an external clock, when the receive conditions are satisfied, the UARTi enters the receive enable state and reception is started by ____ of an external clock to the CLKi pin. input In the case of selecting an external clock and the RTS function, when the UARTi enters the receive enable ____ state, the RTSi pin's output level becomes "L" to inform the transmitter side that reception is enabled. When ____ ____ reception is started, the RTSi pin's output level becomes "H." Accordingly, by connecting the RTSi pin to ____ the CTSi pin of the transmitter side, the timing of transmission and that of reception can be matched. When ____ ____ an internal clock is selected, do not use the RTS function. It is because the RTS output becomes undefined. Figure 11.3.10 shows a connection example. The receive operations are described below: The input signal of the RxDi pin is taken into the most significant bit of the UARTi receive register synchronously with the rising edge of the transfer clock. The contents of the UARTi receive register are shifted by 1 bit to the right. Steps and are repeated at each rising edge of the transfer clock. When 1-byte data is prepared in the UARTi receive register, the contents of this register are transferred to the UARTi receive buffer register. Simultaneously with step , the receive complete flag is set to "1," and a UARTi receive interrupt request occurs and its interrupt request bit is set to "1." The receive complete flag is cleared to "0" when the low-order byte of the UARTi receive buffer register ____ is read out. The RTSi pin outputs "H" level until the receive conditions are next satisfied (when selecting ____ the RTS function). Figure 11.3.11 shows the receive operation, and Figure 11.3.12 shows an example of receive timing (when selecting an external clock). Transmitter side TxDi RxDi CLKi Receiver side TxDi RxDi CLKi CTSi RTSi Fig. 11.3.10 Connection example 7721 Group User's Manual 11-27 SERIAL I/O 11.3 Clock synchronous serial I/O mode MSB Transfer clock UARTi receive register D0 D1 D0 D2 D1 * * * D7 D6 b7 LSB D0 * * * D5 D4 D3 D2 D1 D0 b0 UARTi receive buffer register Fig. 11.3.11 Receive operation Receive data Receive enable bit Transmit enable bit Dummy data is set to UARTi transmit buffer register. Transmit buffer empty flag UARTi transmit register UARTi transmit buffer register RTSi 1/fEXT CLKi Received data taken in RxDi D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 UARTi receive register UARTi receive buffer register Receive complete flag UARTi receive buffer register is read out. UARTi receive interrupt request bit The above timing diagram applies when the following setting conditions are satisfied: q External clock selected q RTS function selected fEXT: Frequency of external clock Cleared to "0" when interrupt request is accepted or cleared by software. : When the CLKi pin's input level is "H," satisfy the following conditions: q Transmit enable bit "1" q Receive enable bit "1" q Writing of dummy data to UARTi transmit buffer register Fig. 11.3.12 Example of receive timing (when selecting external clock) 11-28 7721 Group User's Manual SERIAL I/O 11.3 Clock synchronous serial I/O mode 11.3.6 Processing on detecting overrun error In the clock synchronous serial I/O mode, an overrun error can be detected. An overrun error occurs when the next data is prepared in the UARTi receive register with the receive complete flag = "1" (data is present in the UARTi receive buffer register) and next data is transferred to the UARTi receive buffer register, in other words, when the next data is prepared before reading out the contents of the UARTi receive buffer register. When an overrun error occurs, the next receive data is written into the UARTi receive buffer register, and the UARTi receive interrupt request bit is not changed. An overrun error is detected when data is transferred from the UARTi receive register to the UARTi receive buffer register and the overrun error flag is set to "1." The overrun error flag is cleared to "0" by clearing the serial I/O mode select bits to "0002" or clearing the receive enable bit to "0." When an overrun error occurs during reception, initialize the overrun error flag and the UARTi receive buffer register before performing reception again. When it is necessary to perform retransmission owing to an overrun error which occurs in the receiver side, set the UARTi transmit buffer register again before starting transmission again. The method of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer register again are described below. (1) Method of initializing UARTi receive buffer register Clear the receive enable bit to "0" (Reception disabled). Set the receive enable bit to "1" again (Reception enabled). (2) Method of setting UARTi transmit buffer register again Clear the serial I/O mode select bits to "0002" (Serial I/O invalid). Set the serial I/O mode select bits to "0012" again. Set the transmit enable bit to "1" (Transmission enabled), and set the transmit data to the UARTi transmit buffer register. 7721 Group User's Manual 11-29 SERIAL I/O 11.3 Clock synchronous serial I/O mode [Precautions for clock synchronous serial I/O mode] 1. The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing only reception, transmit operation (setting for transmission) must be performed. In this case, dummy data is output from the TxDi pin. 2. When receiving, simultaneously set the receive enable bit and the transmit enable bit to "1." 3. When receiving data, write dummy data to the low-order byte of the UARTi transmit buffer register for each reception of 1-byte data. 4. When selecting an external clock, satisfy the following 3 conditions with the input to the CLKi pin = "H" level. 11-30 7721 Group User's Manual SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode 11.4 Clock asynchronous serial I/O (UART) mode Table 11.4.1 lists the performance overview in the UART mode, and Table 11.4.2 lists the functions of I/O pins in this mode. Table 11.4.1 Performance overview in UART mode Item Transfer data format Start bit Character bit (Transfer data) Parity bit Stop bit Transfer rate Error detection When selecting internal clock When selecting external clock 1 bit 7 bits, 8 bits, or 9 bits 0 bit or 1 bit (Odd or even can be selected.) 1 bit or 2 bits BRGi's output divided by 16 Maximum 312.5 kbps 4 types (Overrun, Framing, Parity, and Summing) Presence of error can be detected only by checking error sum flag. Functions Table 11.4.2 Functions of I/O pins in UART mode Functions Pin name TxDi (P83, P87) (Note 1) Serial data output Method of selection (Cannot be used as a programmable I/O port even when performing only reception.) RxDi (P82, P86) Serial data input Port P8 direction register U1's corresponding bit = "0" (Can be used as a programmable I/O port when performing only transmission.) CLKi (P81, P85) ____ ____ ____ ____ Programmable I/O port Internal/External clock select bit U2 = "0" Internal/External clock select bit = "1" BRGi's count source input ____ ____ CTS input RTS output ____ ____ CTSi/RTSi (P80, P84) (Note 2) CTS/RTS function select bit U3 = "0" CTS/RTS function select bit = "1" Port P8 direction register U1: address 1416 Internal/External clock select bitU2: bit 3 at addresses 3016, 3816 ____ ____ CTS/RTS select bitU3: bit 2 at addresses 3416, 3C16 Notes 1: The TxDi pin outputs "H" level while transmission is not performed after selecting UARTi's operating mode. ____ ____ 2: The CTSi/RTSi pin can be used as___ input port when performing only reception and not using an ___ the RTS function (when selecting CTS function). 7721 Group User's Manual 11-31 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode 11.4.1 Transfer rate (Frequency of transfer clock) The transfer rate is determined by the BRGi (addresses 3116, 3916). When setting "n" into BRGi, BRGi divides the count source frequency by (n + 1). The BRGi's output is further divided by 16, and the resultant clock becomes the transfer clock. Accordingly, "n" is expressed by the following formula. n= F 16 ! B --1 n: Value set in BRGi (0016 to FF16) F: BRGi's count source frequency (Hz) B: Transfer rate (bps) An internal clock or an external clock can be selected as the BRGi's count source with the internal/external clock select bit (bit 3 at addresses 3016, 3816). When an internal clock is selected, the clock selected with the BRG count source select bits (bits 0 and 1 at addresses 3416, 3C16) becomes the BRGi's count source. When an external clock is selected, the clock input to the CLKi pin becomes the BRGi's count source. Set the same transfer rate for both transmitter and receiver sides. Tables 11.4.3 and 11.4.4 list the setting examples of transfer rate. Table 11.4.3 Setting examples of transfer rate (1) f(XIN) = 24.576 MHz Transfer Actual time BRGi's set BRGi's rate (bps) (bps) value : n count source 300 600 1200 2400 4800 9600 14400 19200 31250 38400 f2 19 (1316) 38400.00 f64 f16 f16 f16 f2 f2 f2 f2 79 (4F16) 159 (9F16) 79 (4F16) 39 (2716) 159 (9F16) 79 (4F16) 52 (3416) 39 (2716) 300.00 600.00 1200.00 2400.00 4800.00 9600.00 14490.57 19200.00 BRGi's count source f64 f16 f16 f16 f2 f2 f2 f2 f2 f(XIN) = 25 MHz BRGi's set Actual time value : n (bps) 80 (5016) 301.41 162 (A216) 80 (5016) 40 (2816) 162 (A216) 80 (5016) 53 (3516) 40 (2816) 24 (1816) 599.12 1205.63 2381.86 4792.94 9645.06 14467.59 19054.58 31250.00 Table 11.4.4 Setting examples of transfer rate (2) Transfer rate (bps) 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 57600 115200 230400 11-32 f(XIN) = 22.1184 MHz Actual time BRGi's set value : n (bps) count source 300.00 71 (4716) f64 BRGi's f16 f16 f16 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 143 (8F16) 71 (4716) 35 (2316) 143 (8F16) 71 (4716) 47 (2F16) 35 (2316) 23 (1716) 21 (1516) 17 (1116) 11 (0B16) 5 (0516) 2 (0216) 600.00 1200.00 2400.00 4800.00 9600.00 14400.00 19200.00 28800.00 31418.18 38400.00 57600.00 115200.00 230400.00 7721 Group User's Manual SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode 11.4.2 Transfer data format The transfer data format can be selected from formats shown in Figure 11.4.1. Bits 4 to 6 at addresses 3016 and 3816 select the transfer data format. (Refer to "Figure 11.2.2.") Set the same transfer data format for both transmitter and receiver sides. Figure 11.4.2 shows an example of transfer data format. Table 11.4.5 lists each bit in transmit data. Transfer data length of 7 bits 1ST--7DATA 1SP 1ST--7DATA 2SP 1ST--7DATA--1PAR-- 1SP 1ST--7DATA--1PAR-- 2SP 1ST--8DATA 1SP 1ST--8DATA 2SP 1ST--8DATA--1PAR-- 1SP 1ST--8DATA--1PAR-- 2SP 1ST--9DATA 1SP 1ST--9DATA 2SP 1ST--9DATA--1PAR-- 1SP 1ST--9DATA--1PAR-- 2SP Transfer data length of 8 bits Transfer data length of 9 bits ST DATA PAR SP : Start bit : Character bit (Transfer data) : Parity bit : Stop bit Fig. 11.4.1 Transfer data format *For the case where 1ST-8DATA-1PAR-1SP Time Transmit/Receive data DATA (8 bits) ST LSB MSB PAR SP Next transmit/receive data (When continuously transferring) ST Fig. 11.4.2 Example of transfer data format Table 11.4.5 Each bit in transmit data Name ST Start bit DATA Character bit PAR Parity bit Functions "L" signal equivalent to 1 character bit which is added immediately before the character bits. It indicates start of data transmission. Transmit data which is set in the UARTi transmit buffer register. A signal that is added immediately after the character bits in order to improve data reliability. The level of this signal changes according to selection of odd/even parity in such a way that the sum of "1"s in this bit and character bits is always an odd or even number. "H" level signal equivalent to 1 or 2 character bits which is added immediately after the character bits (or parity bit when parity is enabled). It indicates finish of data transmission. SP Stop bit 7721 Group User's Manual 11-33 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode 11.4.3 Method of transmission Figure 11.4.3 shows an initial setting example for relevant registers when transmitting. The difference due to selection of transfer data length (7 bits, 8 bits, or 9 bits) is only that data length. When selecting a 7- or 8-bit data length, set the transmit data into the low-order byte of the UARTi transmit buffer register. When selecting a 9-bit data length, set the transmit data into the low-order byte and bit 0 of the high-order byte. Transmission is started when all of the following conditions ( to ) are satisfied: Transmit is enabled (transmit enable bit = "1"). Transmit data is present in the UARTi transmit buffer register (transmit buffer empty flag = "0"). ____ ____ The CTSi pin's input is at "L" level (when the CTS function selected). ____ Note: When the CTS function is not selected, condition is ignored. ____ ____ By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched. For details, refer to section "11.4.6 Receive operation." When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Figure 11.4.4 shows writing data after start of transmission, and Figure 11.4.5 shows detection of transmit completion. 11-34 7721 Group User's Manual SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) b7 b0 1 b2 b1 b0 UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916 b7 b0 1 0 0: UART mode (7 bits) 1 0 1: UART mode (8 bits) 1 1 0: UART mode (9 bits) Internal/External clock select bit 0: Internal clock 1: External clock Stop bit length select bit 0: 1 stop bit 1: 2 stop bits Odd/Even parity select bit 0: Odd parity 1: Even parity Parity enable bit 0: Parity disabled 1: Parity enabled Sleep select bit 0: Sleep mode terminated (Invalid) 1: Sleep mode selected Can be set to 0016 to FF16. UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) b7 b0 Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16) b15 b8 b7 b0 UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 b0 Set transmit data here. BRG count source select bits b1 b0 0 0 1 1 0: f2 1: f16 0: f64 1: f512 UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 1 Transmit enable bit 1: Transmission enabled CTS/RTS select bit 0: CTS function selected 1: RTS function selected (CTS function disabled) Transmission starts. (In the case of selecting the CTS function, transmission starts when the CTSi pin's input level is "L.") Fig. 11.4.3 Initial setting example for relevant registers when transmitting 7721 Group User's Manual 11-35 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode [When not using interrupts] [When using interrupts] A UARTi transmit interrupt request occurs when the UARTi transmit buffer register becomes empty. Checking state of UARTi transmit buffer register UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 b0 UARTi transmit interrupt 1 Transmit buffer empty flag 0: Data present in transmit buffer register 1: No data present in transmit buffer register (Writing of next transmit data is possible.) Writing of next transmit data UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16) b15 b8 b7 b0 Note : This figure shows the bits and registers required for processing. Refer to "Figures 11.4.6 to 11.4.8" for the change of flag state and the occurrence timing of an interrupt request. Set transmit data here. Fig. 11.4.4 Writing data after start of transmission 11-36 7721 Group User's Manual SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode [When not using interrupts] [When using interrupts] A UARTi transmit interrupt request occurs when transmission starts. Checking start of transmission UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) b7 b0 UARTi transmit interrupt Interrupt request bit 0: No interrupt requested 1: Interrupt requested (Transmission has started.) Checking completion of transmission. UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 b0 Note : This figure shows the bits and registers required for processing. Refer to "Figures 11.4.6 to 11.4.8" for the change of flag state and the occurrence timing of an interrupt request. Transmit register empty flag 0: During transmission 1: Transmission completed Processing at completion of transmission Fig. 11.4.5 Detection of transmit completion 7721 Group User's Manual 11-37 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode 11.4.4 Transmit operation When the receive conditions described in section "11.4.3 Method of transmission" are satisfied, a transfer clock is generated and the following operations are automatically performed after 1 cycle of the transfer clock has passed. *The UARTi transmit buffer register's contents are transferred to the UARTi transmit register. *The transmit buffer empty flag is set to "1." *The transmit register empty flag is cleared to "0." *A UARTi transmit interrupt request occurs and the interrupt request bit is set to "1." The transmit operations are described below: Data in the UARTi transmit register is transmitted from the TxDi pin. This data is transmitted bit by bit sequentially in order of STDATA (LSB)***DATA (MSB)PAR SP according to the transfer data format. The transmit register empty flag is set to "1" at the center of the stop bit (or the second stop bit when selecting 2-stop bits), indicating completion of transmission. Additionally, whether the transmit conditions for the next data are satisfied or not is examined. When the transmit conditions for the next data are satisfied in step , the start bit is generated following the stop bit, and the next data is transmitted. When performing transmission continuously, set the next transmit data in the UARTi transmit buffer register during transmission (when the transmit register empty flag = "0"). When the transmit conditions for the next data are not satisfied, the TxDi pin outputs "H" level and the transfer clock stops. Figures 11.4.6 and 11.4.7 show examples of transmit timing when the transfer data length = 8 bits, and Figure 11.4.8 shows an example of transmit timing when the transfer data length = 9 bits. 11-38 7721 Group User's Manual SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode Tc Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register. Transmit buffer empty flag UARTi transmit register UARTi transmit buffer register TENDi Stopped because transmit enable bit = "0" Start bit Parity bit Stop bit P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 TxDi Transmit register empty flag UARTi transmit interrupt request bit ST D0 D1 D2 D3 D4 D5 D6 D7 Cleared to "0" when interrupt request is accepted or cleared by software. The above timing diagram applies when the following conditions are satisfied: q Parity enabled q 1 stop bit q CTS function not selected TENDi: Next transmit conditions are examined when this signal level is "H." (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc: 16(n + 1)/fi or 16(n + 1)/fEXT fi: BRGi's count source frequency (f2, f16, f64, f512) fEXT: BRGi's count source frequency (external clock) n: Value set in BRGi Fig. 11.4.6 Example of transmit timing when ____ transfer data length = 8 bits (when parity enabled, selecting 1 stop bit, not selecting CTS function) Tc Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register. Transmit buffer empty flag UARTi transmit register UARTi transmit buffer register CTSi TENDi Start bit Parity Stop bit bit P SP Stopped because CTS = "H" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Stopped because transmit enable bit = "0" ST D0 D1 TxDi Transmit register empty flag ST D0 D1 D2 D3 D4 D5 D6 D7 UARTi transmit interrupt request bit Cleared to "0" when interrupt request is accepted or cleared by software. The above timing diagram applies when the following conditions are satisfied: q Parity enabled q 1 stop bit q CTS function selected TENDi: Next transmit conditions are examined when this signal level is "H." (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc = 16(n + 1)/fi or 16(n + 1)/fEXT fi: BRGi's count source frequency (f2, f16, f64, f512) fEXT: BRGi's count source frequency (external clock) n: Value set in BRGi Fig. 11.4.7 Example of transmit timing when transfer data length = 8 bits (when parity enabled, ____ selecting 1 stop bit, selecting CTS function) 7721 Group User's Manual 11-39 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode Tc Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register. Transmit buffer empty flag UARTi transmit register UARTi transmit buffer register Stopped because transmit enable bit = "0" ST D0 D1 TENDi Start bit Stop bit Stop bit TxDi Transmit register empty flag UARTi transmit interrupt request bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP Cleared to "0" when interrupt request is accepted or cleared by software. The above timing diagram applies when the following conditions are satisfied: q Parity disabled q 2 stop bits q CTS function disabled TENDi: Next transmit conditions are examined when this signal level is "H." (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc = 16(n + 1)/fi or 16(n + 1)/fEXT fi: BRGi count source frequency (f2, f16, f64, f512) fEXT: BRGi count source frequency (external clock) n: Value set in BRGi Fig. 11.4.8 Example of transmit timing when transfer data length = 9 bits (when parity disabled, ____ selecting 2 stop bits, not selecting CTS function) 11-40 7721 Group User's Manual SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode 11.4.5 Method of reception Figure 11.4.9 shows an initial setting example for relevant registers when receiving. Reception is started when all of the following conditions ( and ) are satisfied: Reception is enabled (receive enable bit = "1"). The start bit is detected. ____ ____ By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched. For details, refer to section "11.4.6 Receive operation." When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Figure 11.4.10 shows processing after receive completion. 7721 Group User's Manual 11-41 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) b7 b0 1 b2b1b0 UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) 1 0 0: UART mode (7 bits) 1 0 1: UART mode (8 bits) 1 1 0: UART mode (9 bits) Internal/External clock select bit 0: Internal clock 1: External clock Stop bit length select bit 0: 1 stop bit 1: 2 stop bits Odd/Even parity select bit 0: Odd parity 1: Even parity Parity enable bit 0: Parity disabled 1: Parity enabled Sleep select bit 0: Sleep mode terminated (Invalid) 1: Sleep mode selected Note: Set the transfer data format in the same way as set on the transmitter side. b7 b0 Can be set to 0016 to FF16. Port P8 direction register (Address 1416) b7 b0 0 0 RxD0 pin RxD1 pin UART0 receive interrupt control register (Address 7216) UART1 receive interrupt control register (Address 7416) b7 b0 UART0 transmit/receive control register 0 (Address 34 16 ) UART1 transmit/receive control register 0 (Address 3C16 ) b7 b0 Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. BRG count source select bits b1b0 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 CTS/RTS select bit UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 1 Receive enable bit 1: Reception enabled 0 : CTS function selected 1 : RTS function selected Reception starts when the start bit is detected. Fig. 11.4.9 Initial setting example for relevant registers when receiving 11-42 7721 Group User's Manual SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode [When not using interrupts] [When using interrupts] A UARTi receive interrupt request occurs when reception is completed. Checking completion of reception UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 UARTi receive interrupt 1 Receive complete flag 0 : Reception not completed 1 : Reception completed Checking error UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 1 Framing error flag Parity error flag Error sum flag 0 : No error 1 : Error detected Reading of receive data UART0 receive buffer register (Addresses 3716, 3616) UART1 receive buffer register (Addresses 3F16, 3E16) b15 b8 b7 b0 0000000 Read out receive data. Checking error UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 1 Overrun error flag 0 : No overrun error 1 : Overrun error detected Processing after reading out receive data Note : This figure shows the bits and registers required for processing. Refer to "Figure 11.4.12" for the change of flag state and the occurrence timing of an interrupt request. Fig. 11.4.10 Processing after receive completion 7721 Group User's Manual 11-43 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode 11.4.6 Receive operation When the receive enable bit is set to "1," the UARTi enters the receive enable state. After this, reception starts when ST is detected and a transfer clock is generated. ____ ____ In the case of selecting the RTS function, when the reception is enabled, the RTSi pin's output level ____ becomes "L" to inform the transmitter side that reception is enabled. When reception is started, the RTSi ____ ____ pin's output level becomes "H." Accordingly, by connecting the RTSi pin to the CTSi pin of the transmitter side, the timing of transmission and that of reception can be matched. Figure 11.4.11 shows an connection example. The receive operation is described below. The input signal of the RxDi pin is taken into the most significant bit of the UARTi receive register synchronously with the transfer clock's rising edge. The contents of the UARTi receive register are shifted by 1 bit to the right. Steps and are repeated at each rising edge of the transfer clock. When one set of data has been prepared, in other words, when the shift has been performed several times according to the selected data format, the UARTi receive register's contents are transferred to the UARTi receive buffer register. Simultaneously with step , the receive complete flag is set to "1." Additionally, a UARTi receive interrupt request occurs and its interrupt request bit is set to "1." The receive complete flag is cleared to "0" when the low-order byte of the UARTi receive buffer register ____ ____ is read out. The RTSi pin's output level becomes "L" simultaneously with step (when selecting the RTS function). Figure 11.4.12 shows an example of receive timing when the transfer data length = 8 bits. Transmitter side TxDi RxDi Receiver side TxDi RxDi CTSi RTSi Fig. 11.4.11 Connection example 11-44 7721 Group User's Manual SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode BRGi count source Receive enable bit Stop bit RxDi Start bit Sampled "L" Transfer clock Receive complete flag At falling edge of start bit, transfer clock is generated and reception started. D0 D1 D7 Received data taken in UARTi receive register UARTi receive buffer register RTSi UARTi receive interrupt request bit The above timing diagram applies when the following conditions are satisfied: q Parity disabled q 1 stop bit q RTS function selected Cleared to "0" when interrupt request is accepted or cleared by software. Fig. 11.4.12 Example of receive timing when transfer data length = 8 bits (when parity disabled, ____ selecting 1 stop bit, selecting RTS function) 7721 Group User's Manual 11-45 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode 11.4.7 Processing on detecting error In the UART mode, 3 types of errors can be detected. Each error can be detected when the data in the UARTi receive register is transferred to the UARTi receive buffer register, and the corresponding error flag is set to "1." When any error occurs, the error sum flag is set to "1." Accordingly, presence of errors can be judged by using the error sum flag. Table 11.4.6 lists conditions for setting each error flag to "1" and method for clearing it to "0." Table 11.4.6 Conditions set to "1" and method cleared to "0" for each error flag Conditions for being set to "1" Error flag Method for being cleared to "0" Overrun error flag When the next data is prepared in the *Clear the serial I/O mode select bits to UARTi receive register with the receive "0002." complete flag = "1" (i.e., data is present *Clear the receive enable bit to "0." in the UARTi receive buffer register). In other words, when the next data is prepared before the contents of the UARTi receive buffer register are read out. (Note) [UARTi receive interrupt request bit is not changed.] Framing error flag When the number of detected stop bits *Clear the serial I/O mode select bits to does not match the set number of stop "0002." bits. *Clear the receive enable bit to "0." [UARTi receive interrupt request bit is set *Read out the low-order byte of the UARTi to "1."] receive buffer register. When the sum of "1"s in the parity bit *Clear the serial I/O mode select bits to and character bits does not match the "0002." set number of "1"s. *Clear the receive enable bit to "0." [UARTi receive interrupt request bit is set *Read out the low-order byte of the UARTi to "1."] receive buffer register. When 1 or more errors listed above occur. *Clear the all error flags, which are overrun, framing and parity error flags. Note: The next data is written into the UARTi receive buffer register. When an error occurs during reception, initialize the error flag and the UARTi receive buffer register, and then perform reception again. When it is necessary to perform retransmission owing to an error which occurs in the receiver side during transmission, set the UARTi transmit buffer register again, and then restarts transmission. The method of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer register again are described below. (1) Method of initializing UARTi receive buffer register Clear the receive enable bit to "0" (reception disabled). Set the receive enable bit to "1" again (reception enabled). (2) Method of setting UARTi transmit buffer register again Clear the serial I/O mode select bits to "0002" (serial I/O invalid). Set the serial I/O mode select bits again. Set the transmit enable bit to "1" (transmission enabled), and set the transmit data to the UARTi transmit buffer register. Parity error flag Error sum flag 11-46 7721 Group User's Manual SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode 11.4.8 Sleep mode This mode is used to transfer data between the specified microcomputers, which are connected by using UARTi. The sleep mode is selected by setting the sleep select bit (bit 7 at addresses 3016, 3816) to "1" when receiving. In the sleep mode, receive operation is performed when the MSB (D8 when the transfer data is 9 bits length, D7 when it is 8 bits length, D6 when it is 7 bits length) of the receive data is "1." Receive operation is not performed when the MSB is "0." (The UARTi receive register's contents are not transferred to the UARTi receive buffer register. Additionally, the receive complete flag and error flags do not change and a UARTi receive interrupt request does not occur.) The following shows an usage example of the sleep mode when the transfer data is 8 bits length. Set the same transfer data format for the master and slave microcomputers. Select the sleep mode for the slave microcomputers. Transmit data, which has "1" in bit 7 and the address of the slave microcomputer to be communicated in bits 0 to 6, from the master microcomputer to all slave microcomputers. All slave microcomputers receive data of step . (At this time, a UARTi receive interrupt request occurs.) For all slave microcomputers, check in the interrupt routine whether bits 0 to 6 in the receive data match their own addresses. For the slave microcomputer of which address matches bits 0 to 6 in the receive data, terminate the sleep mode. (Do not terminate the sleep mode for the other slave microcomputers.) By performing steps to , " the microcomputer which performs transfer" is specified. Transmit data, which has "0" in bit 7, from the master microcomputer. (Only the microcomputer specified in steps to can receive this data. The other microcomputers do not receive this data.) By repeating step , transfer can be performed between two specific microcomputers continuously. When communicating with another microcomputer, perform steps to in order to specify the new slave microcomputer. Master Data is transferred between the master microcomputer and one specific slave microcomputer selected from multiple slave microcomputers. Slave A Slave B Slave C Slave D Fig. 11.4.13 Sleep mode 7721 Group User's Manual 11-47 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode MEMORANDUM 11-48 7721 Group User's Manual CHAPTER 12 A-D CONVERTER 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 Overview Block description A-D conversion method Absolute accuracy and differential non-linearity error One-shot mode Repeat mode Single sweep mode Repeat sweep mode Precautions for A-D converter A-D CONVERTER 12.1 Overview 12.1 Overview Table 12.1.1 lists the performance specifications of the A-D converter. Table 12.1.1 Performance specifications of A-D converter Item A-D conversion method Resolution Absolute accuracy Analog input pin Conversion rate per analog input pin 8 bits 3 LSB 8 pins (AN0 to AN7) (Note) 57 ADV cycles Performance specifications Successive approximation conversion method ADV: A-D converter's operation clock The A-D converter has the 4 operation modes listed below. *One-shot mode This mode is used to perform the operation once for a voltage input from one selected analog input pin. *Repeat mode This mode is used to perform the operation repeatedly for a voltage input from one selected analog input pin. *Single sweep mode This mode is used to perform the operation for voltages input from multiple selected analog input pins, one at a time. *Repeat sweep mode This mode is used to perform the operation repeatedly for voltages input from multiple selected analog input pins. 12-2 7721 Group User's Manual A-D CONVERTER 12.2 Block description 12.2 Block description Figure 12.2.1 shows the block diagram of the A-D converter. Registers relevant to the A-D converter are described below. AD f2 VREF AVSS Resistor ladder network Vref 1/2 1/2 Successive approximation register A-D sweep pin select register A-D control register A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 Decoder Data bus (even) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7/ADTRG Selector VIN Comparator Fig. 12.2.1 Block diagram of A-D converter 7721 Group User's Manual 12-3 A-D CONVERTER 12.2 Block description 12.2.1 A-D control register Figure 12.2.2 shows the structure of the A-D control register. The A-D operation mode select bit selects the operation mode of the A-D converter. The other bits are described below. b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (Address 1E16) Bit 0 Bit name Analog input select bits (Valid in one-shot and repeat modes) (Note 1) b2 b1 b0 Functions 0 0 0 : AN0 selected 0 0 1 : AN1 selected 0 1 0 : AN2 selected 0 1 1 : AN3 selected 1 0 0 : AN4 selected 1 0 1 : AN5 selected 1 1 0 : AN6 selected 1 1 1 : AN7 selected (Note 2) At reset Undefined RW RW 1 Undefined RW 2 Undefined RW 3 A-D operation mode select bits b4 b3 4 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode Trigger select bit A-D conversion start bit A-D conversion frequency ( AD) select bit 0 : Internal trigger 1 : External trigger 0 : Stop A-D conversion 1 : Start A-D conversion 0 : f2 divided by 4 1 : f2 divided by 2 0 RW 0 RW 5 6 7 0 0 0 RW RW RW Notes 1: These bits are ignored in the single sweep and repeat sweep mode. (They may be either "0" or "1.") 2: When an external trigger is selected, the AN7 pin cannot be used as an analog input pin. 3: Writing to each bit (except bit 6) of the A-D control register must be performed while the A-D converter halts. Fig. 12.2.2 Structure of A-D control register (1) Analog input select bits (bits 2 to 0) These bits are used to select an analog input pin in the one-shot mode and repeat mode. Pins which are not selected as analog input pins function as programmable I/O ports. These bits must be set again when the user switches the A-D operation mode to the one-shot mode or repeat mode after A-D conversion is performed in the single sweep mode or repeat sweep mode. 12-4 7721 Group User's Manual A-D CONVERTER 12.2 Block description (2) Trigger select bit (bit 5) This bit is used to select the source of trigger occurrence. (Refer to section "(3) A-D conversion start bit.") (3) A-D conversion start bit (bit 6) q When internal trigger is selected Setting this bit to "1" generates a trigger, causing the A-D converter to start operating. Clearing this bit to "0" causes the A-D converter to stop operating. In the one-shot mode or single sweep mode, this bit is cleared to "0" after the operation is completed. In the repeat mode or repeat sweep mode, the A-D converter continues operating until this bit is cleared to "0" by software. q When external trigger is selected ______ When the ADTRG pin level goes from "H" to "L" with this bit = "1," a trigger occurs, causing the A-D converter to start operating. The A-D converter stops when this bit is cleared to "0." In the one-shot mode or single sweep mode, this bit remains set to "1" even after the operation is completed. In the repeat mode or repeat sweep mode, the A-D converter continues operating until this bit is cleared to "0" by software. (4) A-D conversion frequency (AD) select bit (bit 7) As listed in Table 12.2.1, the conversion time of the A-D converter varies depending on the operating clock (AD) selected by this bit. Since the A-D converter's comparator consists of capacity coupling amplifiers, keep that AD 250 kHz during A-D conversion. Table 12.2.1 Conversion time per one analog input pin (unit: s) 0 A-D conversion frequency (AD) select bit f2/4 AD Conversion time f(XIN) = 8 MHz f(XIN) = 16 MHz f(XIN) = 25 MHz 57.0 28.5 18.24 1 f2/2 28.5 14.25 9.12 7721 Group User's Manual 12-5 A-D CONVERTER 12.2 Block description 12.2.2 A-D sweep pin select register Figure 12.2.3 shows the structure of the A-D sweep pin select register. b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select register (Address 1F16) Bit 0 1 Bit name A-D sweep pin select bits (Valid in single sweep and repeat sweep mode ) (Note 1) b1 b0 Functions 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) (Note 2) At reset RW RW RW 1 1 7 to 2 Nothing is assigned. Undefined - Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either "0" or "1.") 2: When selecting an external trigger, the AN7 pin cannot be used as an analog input pin. 3: Writing to each bit of the A-D sweep pin select register must be performed while the A-D converter halts. Fig. 12.2.3 Structure of A-D control register 1 (1) A-D sweep pin select bits (bits 1 and 0) These bits are used to select analog input pins in the single sweep mode or repeat sweep mode. In the single sweep mode and repeat sweep mode, pins which are not selected as analog input pins function as programmable I/O ports. 12-6 7721 Group User's Manual A-D CONVERTER 12.2 Block description 12.2.3 A-D register i (i = 0 to 7) Figure 12.2.4 shows the structure of the A-D register i. When the A-D conversion is completed, the conversion result (contents of the successive approximation register) is stored into this register. Each AD register i corresponds to an analog input pin (ANi). b7 b6 b5 b4 b3 b2 b1 b0 A-D register 0 (Addresses 2016) A-D register 1 (Addresses 2216) A-D register 2 (Addresses 2416) A-D register 3 (Addresses 2616) A-D register 4 (Addresses 2816) A-D register 5 (Addresses 2A16) A-D register 6 (Addresses 2C16) A-D register 7 (Addresses 2E16) Bit Functions At reset Undefined RW RO 7 to 0 Reads an A-D conversion result. Fig. 12.2.4 Structure of A-D register i 7721 Group User's Manual 12-7 A-D CONVERTER 12.2 Block description 12.2.4 A-D conversion interrupt control register Figure 12.2.5 shows the structure of the A-D conversion interrupt control register. For details about interrupts, refer to "CHAPTER 7. INTERRUPTS." b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion interrupt control register (Address 7016) Bit 0 Bit name Interrupt priority level select bits b2 b1 b0 Functions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level 0 : No interrupt requested 1 : Interrupt requested At reset RW RW 0 1 0 RW 2 0 RW 3 7 to 4 Interrupt request bit Nothing is assigned. 0 Undefined RW - Fig. 12.2.5 Structure of A-D conversion interrupt control register (1) Interrupt priority level select bits (bits 2 to 0) These bits select an A-D conversion interrupt's priority level. When using A-D conversion interrupts, select one of the priority levels (1 to 7). When an A-D conversion interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = "0.") To disable A-D conversion interrupts, set these bits to "0002" (level 0). (2) Interrupt request bit (bit 3) This bit is set to "1" when an A-D conversion interrupt request occurs. This bit is automatically cleared to "0" when the A-D conversion interrupt request is accepted. This bit can be set to "1" or cleared to "0" by software. 12-8 7721 Group User's Manual A-D CONVERTER 12.2 Block description 12.2.5 Port P7 direction register Input pins of the A-D converter are multiplexed with port P7. When using these pins as A-D converter's input pins, set the corresponding bits of the port P7 direction register to "0" to set these port pins for the input mode. Figure 12.2.6 shows the relationship between the port P7 direction register and A-D converter's input pins. b7 b6 b5 b4 b3 b2 b1 b0 Port P7 direction register (Address 1116) Bit 0 1 2 3 4 5 6 7 Corresponding pin AN0 pin AN1 pin AN2 pin AN3 pin AN4 pin AN5 pin AN6 pin AN7/ADTRG pin Functions 0 : Input mode 1 : Output mode When using these pins as A-D converter's input pins, set the corresponding bits to "0." At reset RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Fig. 12.2.6 Relationship between port P7 direction register and A-D converter's input pins 7721 Group User's Manual 12-9 A-D CONVERTER 12.3 A-D conversion method 12.3 A-D conversion method The A-D converter compares the comparison voltage (Vref), which is internally generated according to the contents of the successive approximation register, with the analog input voltage (VIN), which is input from the analog input pin (ANi). By reflecting the comparison result on the successive approximation register, VIN is converted into a digital value. When a trigger is generated, the A-D converter performs the following processing: Determining bit 7 of the successive approximation register The A-D converter compares Vref with VIN. At this time, the contents of the successive approximation register is "100000002" (initial value). Bit 7 of the successive approximation register changes according to the comparison result as follows: When Vref < VIN, bit 7 = "1" When Vref > VIN, bit 7 = "0" Determining bit 6 of the successive approximation register After setting bit 6 of the successive approximation register to "1," the A-D converter compares Vref with VIN. Bit 6 changes according to the comparison result as follows: When Vref < VIN, bit 6 = "1" When Vref > VIN, bit 6 = "0" Determining bits 5 to 0 of the successive approximation register Operations in are performed for bits 5 to 0. When bit 0 is determined, the contents (conversion result) of the successive approximation register is transferred to the A-D register i. The comparison voltage (Vref) is generated according to the latest contents of the successive approximation register. Table 12.3.1 lists the relationship between the successive approximation register's contents and Vref. Table 12.3.2 lists changes of the successive approximation register and Vref during the A-D conversion. Figure 12.3.1 shows the ideal A-D conversion characteristics. Table 12.3.1 Relationship between successive approximation register's contents and Vref Successive approximation register's contents: n Vref (V) 0 0 1 to 255 VREFV: Reference voltage VREFV 256 ! (n - 0.5) 12-10 7721 Group User's Manual A-D CONVERTER 12.3 A-D conversion method Table 12.3.2 Change in successive approximation register and Vref during A-D conversion Successive approximation register b7 A-D converter halt 1st comparison 2nd comparison 3rd comparison Change of Vref VREF [V] 2 VREF - VREF [V] 512 2 VREF VREF - VREF [V] 4 2 512 *n7=1 *n7=0 b0 10000000 10000000 n7 1 0 0 0 0 0 0 1st comparison result + VREF 4 - n7 n6 1 0 0 0 0 0 2nd comparison result VREF VREF VREF - VREF [V] 8 512 4 2 : : VREF 4 *n6=1 *n6=0 VREF 8 VREF -8 + : : : : 8th comparison Conversion complete n7 n6 n5 n4 n3 n2 n1 1 n7 n6 n5 n4 n3 n2 n1 n0 VREF VREF VREF ...... VREF - VREF [V] 4 8 256 512 2 A-D conversion result ldeal A-D conversion characteristics FF16 FE16 FD16 0316 0216 0116 0016 0 VREF 256 !0.5 VREF !1 256 VREF !2 256 VREF !3 256 VREF !253 256 VREF !254 256 VREF !255 256 VREF Analog input voltage Fig. 12.3.1 Ideal A-D conversion characteristics 7721 Group User's Manual 12-11 A-D CONVERTER 12.4 Absolute accuracy and differential non-linearity error 12.4 Absolute accuracy and differential non-linearity error The A-D converter's accuracy is described below. Refer to section "Appendix 12.3 A-D converter standard characteristics," also. 12.4.1 Absolute accuracy The absolute accuracy is the difference expressed in the LSB between the actual A-D conversion result and the output code of an A-D converter with ideal characteristics. The analog input voltage when measuring the accuracy is assumed to be the mid point of the input voltage width that outputs the same output code from an A-D converter with ideal characteristics. For example, when VREF = 5.12 V, 1 LSB width is 20 mV, and 0 mV, 20 mV, 40 mV, 60 mV, 80 mV, ... are selected as the analog input voltages. The absolute accuracy = 3 LSB indicates that when the analog input voltage is 100 mV, the output code expected from an ideal A-D conversion characteristics is "00516," however the actual A-D conversion result is between "00216" to "00816." The absolute accuracy includes the zero error and the full-scale error. The absolute accuracy is degraded when VREF is lowered. Any of the output codes for analog input voltages from VREF to AVCC is "FF16." Output code (A-D conversion result) 0B16 0A16 0916 0816 0716 0616 0516 0416 0316 0216 -3 LSB 0116 0016 0 20 40 60 80 100 120 140 160 180 200 220 +3 LSB Ideal A-D conversion characteristics Analog input voltage (mV) Fig. 12.4.1 Absolute accuracy of A-D converter 12-12 7721 Group User's Manual A-D CONVERTER 12.4 Absolute accuracy and differential non-linearity error 12.4.2 Differential non-linearity error The differential non-linearity error indicates the difference between the 1 LSB step width (the ideal analog input voltage width while the same output code is expected to output) of an A-D converter with ideal characteristics and the actual measured step width (the actual analog input voltage width while the same output code is output). For example, when VREF = 5.12 V, the 1 LSB width of an A-D converter with ideal characteristics is 20 mV, however when the differential non-linearity error is 1 LSB, the actual measured 1 LSB width is 0 to 40 mV. Output code (A-D conversion result) 0916 0816 0716 0616 0516 0416 0316 0216 0116 Differential non-linearity error 0016 0 20 40 60 80 100 120 140 160 180 1 LSB width with ideal A-D conversion characteristics Analog input voltage (mV) Fig. 12.4.2 Differential non-linearity error 7721 Group User's Manual 12-13 A-D CONVERTER 12.5 One-shot mode 12.5 One-shot mode In the one-shot mode, the operation for the input voltage from the one selected analog input pin is performed once, and the A-D conversion interrupt request occurs when the operation is completed. 12.5.1 Settings for one-shot mode Figure 12.5.1 shows an initial setting example for registers relevant to the one-shot mode. When using an interrupt, it is necessary to set the relevant registers to enable the interrupt. Refer to "CHAPTER 7. INTERRUPTS" for more descriptions. 12-14 7721 Group User's Manual A-D CONVERTER 12.5 One-shot mode qA-D control register b7 b0 0 00 A-D control register (address 1E16) Analog input select bits b2 b1 b0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : AN0 selected 1 : AN1 selected 0 : AN2 selected 1 : AN3 selected 0 : AN4 selected 1 : AN5 selected 0 : AN6 selected 1 : AN7 selected One-shot mode Trigger select bit 0 : Internal trigger 1 : External trigger A-D conversion start bit 0: Stop A-D conversion A-D conversion frequency ( select bit 0 : f2 divided by 4 1 : f2 divided by 2 AD) qInterrupt priority level b7 b0 A-D conversion interrupt control register (address 7016) Interrupt priority level select bits Set to a level between 1 to 7 when using this interrupt. Set to a level 0 when disabling this interrupt. qPort P7 direction register b7 b0 Port P7 direction register (address 1116) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 qSet A-D conversion start bit to "1" b7 b0 1 Set the bits corresponding to analog input pins to "0." Set bit 7 to "0" when selecting external trigger. A-D control register (address 1E16) A-D conversion start bit When external trigger is selected When internal trigger is selected Input falling edge to ADTRG pin Note : Writing to each bit (except bit 6) of the A-D control register must be performed while the A-D converter halts (before a trigger occurs). Trigger occur Operation start Fig. 12.5.1 Initial setting example for registers relevant to one-shot mode 7721 Group User's Manual 12-15 A-D CONVERTER 12.5 One-shot mode 12.5.2 One-shot mode operation description (1) When an internal trigger is selected The A-D converter starts operation when the A-D conversion start bit is set to "1." The A-D conversion is completed after 57 cycles of AD. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register i. At the same time as step , the A-D conversion interrupt request bit is set to "1." The A-D conversion start bit is cleared to "0" and the A-D converter stops operation. (2) When an external trigger is selected _____ The A-D converter starts operation when the input level to the ADTRG pin changes from "H" to "L" while the A-D conversion start bit is "1." The A-D conversion is completed after 57 cycles of AD. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register i. At the same time as step , the A-D conversion interrupt request bit is set to "1." The A-D conversion stops. The A-D conversion start bit remains set to "1" after the operation is completed. Accordingly, the _____ operation of the A-D converter can be performed again from step when the level of the ADTRG pin changes from "H" to "L." _____ When the level of the ADTRG pin changes from "H" to "L" during operation, the operation at that point is cancelled and is restarted from step . Figure 12.5.2 shows the conversion operation in the one-shot mode. Trigger occur Conversion result Convert input voltage from ANi pin A-D register i A-D conversion interrupt request occurs. A-D converter halt Fig. 12.5.2 Conversion operation in one-shot mode 12-16 7721 Group User's Manual A-D CONVERTER 12.6 Repeat mode 12.6 Repeat mode In the repeat mode, the operation for the input voltage from the one selected analog input pin is performed repeatedly. In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at address 1E16) remains set to "1" until it is cleared to "0" by software, and the operation is performed repeatedly while the A-D conversion start bit is "1." 12.6.1 Settings for repeat mode Figure 12.6.1 shows an initial setting example for registers relevant to the repeat mode. 7721 Group User's Manual 12-17 A-D CONVERTER 12.6 Repeat mode qA-D control register b7 b0 0 01 A-D control register (address 1E16) Analog input select bits b2 b1 b0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : AN0 selected 1 : AN1 selected 0 : AN2 selected 1 : AN3 selected 0 : AN4 selected 1 : AN5 selected 0 : AN6 selected 1 : AN7 selected Repeat mode Trigger select bit 0 : Internal trigger 1 : External triggeer A-D conversion start bit 0: Stop A-D conversion A-D conversion frequency ( select bit 0 : f2 divided by 4 1 : f2 divided by 2 AD) qPort P7 direction register b7 b0 Port P7 direction register (address 1116) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Set the bits corresponding to analog input pins to "0." Set bit 7 to "0" when selecting external trigger. qSet A-D conversion start bit to "1" b7 b0 1 A-D control register (address 1E16) A-D conversion start bit When external trigger is selected When internal trigger is selected Input falling edge to ADTRG pin Trigger occur Operation start Note : Writing to each bit (except bit 6) of the A-D control register must be performed while the A-D converter halts (before a trigger occurs). Fig. 12.6.1 Initial setting example for registers relevant to repeat mode 12-18 7721 Group User's Manual A-D CONVERTER 12.6 Repeat mode 12.6.2 Repeat mode operation description (1) When an internal trigger is selected The A-D converter starts operation when the A-D conversion start bit is set to "1." The first A-D conversion is completed after 57 cycles of AD. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register i. The A-D converter repeats operation until the A-D conversion start bit is cleared to "0" by software. The conversion result is transferred to the A-D register i each time the conversion is completed. (2) When an external trigger is selected ____ The A-D converter starts operation when the input level to the ADTRG pin changes from "H" to "L" while the A-D conversion start bit is "1." The first A-D conversion is completed after 57 cycles of AD. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register i. The A-D converter repeats operation until the A-D conversion start bit is cleared to "0" by software. The conversion result is transferred to the A-D register i each time the conversion is completed. _____ When the level of the ADTRG pin changes from "H" to "L" during operation, the operation at that point is cancelled and is restarted from step . Figure 12.6.2 shows the conversion operation in the repeat mode. Trigger occur Conversion result Convert input voltage from ANi pin A-D register i Fig. 12.6.2 Conversion operation in repeat mode 7721 Group User's Manual 12-19 A-D CONVERTER 12.7 Single sweep mode 12.7 Single sweep mode In the single sweep mode, the operation for the input voltage from multiple selected analog input pins is performed, one at a time. The A-D converter is operated in ascending sequence from the AN0 pin. The A-D conversion interrupt request occurs when the operation for all selected input pins are completed. 12.7.1 Settings for single sweep mode Figure 12.7.1 shows an initial setting example for registers relevant to the single sweep mode. When using an interrupt, it is necessary to set the relevant registers to enable the interrupt. Refer to "CHAPTER 7. INTERRUPTS" for more information. 12-20 7721 Group User's Manual A-D CONVERTER 12.7 Single sweep mode qA-D control register and A-D sweep pin select register b7 b0 b7 b0 0 1 0 ! ! ! A-D control register (address 1E16) Single sweep mode Trigger select bit 0 : Internal trigger 1 : External trigger A-D conversion start bit 0: Stop A-D conversion A-D conversion frequency ( select bit 0 : f2 divided by 4 1 : f2 divided by 2 AD) A-D sweep pin select register (address 1F16) A-D sweep pin select bits b1 b0 0 0 1 1 0 : AN0, AN1 (2 pins) 1 : AN0-AN3 (4 pins) 0 : AN0-AN5 (6 pins) 1 : AN0-AN7 (8 pins) ! : "0" or "1" qInterrupt priority level b7 b0 A-D conversion interrupt control register (address 7016) Interrupt priority level select bits Set to a level between 1 to 7 when using this interrupt. Set to a level 0 when disabling this interrupt. qPort P7 direction register b7 b0 Port P7 direction register (address 1116) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Set the bits corresponding to analog input pins to "0." Set bit 7 to "0" when selecting external trigger. qSet A-D conversion start bit to "1" b7 b0 1 A-D control register (address 1E16) A-D conversion start bit When external trigger is selected When internal trigger is selected Input falling edge to ADTRG pin Trigger occur Operation start Note : Writing to each bit (except bit 6) of the A-D control register and each bit of the A-D sweep pin select register must be performed while the A-D converter halts (before a trigger occurs). Fig. 12.7.1 Initial setting example for registers relevant to single sweep mode 7721 Group User's Manual 12-21 A-D CONVERTER 12.7 Single sweep mode 12.7.2 Single sweep mode operation description (1) When an internal trigger is selected The operation for the input voltage from the AN0 pin starts when the A-D conversion start bit is set to "1." The A-D conversion of the input voltage from the AN0 pin is completed after 57 cycles of AD. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. For all of the selected analog input pins, the A-D conversion is performed. The conversion result is transferred to the A-D register i each time each pin is converted. When step is completed, the A-D conversion interrupt request bit is set to "1." The A-D conversion start bit is cleared to "0" and the A-D converter stops operation. (2) When an external trigger is selected The_____converter starts operation for the input voltage from the AN0 pin when the input level to A-D the ADTRG pin changes from "H" to "L" while the A-D conversion start bit is "1." The A-D conversion of the input voltage from the AN0 pin is completed after 57 cycles of AD. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. For all of the selected analog input pins, the A-D conversion is performed. The conversion result is transferred to the A-D register i each time each pin is converted. When step is completed, the A-D conversion interrupt request bit is set to "1." The A-D conversion stops. The A-D conversion start bit remains set to "1" after the operation is completed. Accordingly, the _____ operation of the A-D converter can be performed again from step when the level of the ADTRG pin changes from "H" to "L." _____ When the level of the ADTRG pin changes from "H" to "L" during operation, the operation at that point is cancelled and is restarted from step . Figure 12.7.2 shows the conversion operation in the single sweep mode. 12-22 7721 Group User's Manual A-D CONVERTER 12.7 Single sweep mode Trigger occur Convert input voltage from Conversion result AN0 pin A-D register 0 Convert input voltage from Conversion result AN1 pin A-D register 1 Convert input voltage from Conversion result ANi pin A-D register i A-D conver ter interrupt request occur A-D converter halt Fig. 12.7.2 Conversion operation in single sweep mode 7721 Group User's Manual 12-23 A-D CONVERTER 12.8 Repeat sweep mode 12.8 Repeat sweep mode In the repeat sweep mode, the operation for the input voltages from the multiple selected analog input pins is performed repeatedly. The A-D converter is operated in ascending sequence from the AN0 pin. In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at address 1E16) remains set to "1" until it is cleared to "0" by software, and the operation is performed repeatedly while the A-D conversion start bit is "1." 12.8.1 Settings for repeat sweep mode Figure 12.8.1 shows an initial setting example for registers relevant to the repeat sweep mode. 12-24 7721 Group User's Manual A-D CONVERTER 12.8 Repeat sweep mode qA-D control register and A-D sweep pin select register b7 b0 b7 b0 0 1 1 ! ! ! A-D control register (address 1E16) Repeat sweep mode Trigger select bit 0 : Internal trigger 1 : External trigger A-D conversion start bit 0: Stop A-D conversion A-D conversion frequency ( select bit 0 : f2 divided by 4 1 : f2 divided by 2 AD) A-D sweep pin select register (address 1F16) A-D sweep pin select bits b1 b0 0 0 1 1 0 : AN0, AN1 (2 pins) 1 : AN0-AN3 (4 pins) 0 : AN0-AN5 (6 pins) 1 : AN0-AN7 (8 pins) ! : "0" or "1" qPort P7 direction register b7 b0 Port P7 direction register (address 1116) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Set the bits corresponding to analog input pins to "0." Set bit 7 to "0" when selecting external trigger. qSet A-D conversion start bit to "1" b7 b0 1 A-D control register (address 1E16) A-D conversion start bit When external trigger is selected When internal trigger is selected Input falling edge to ADTRG pin Trigger occur Operation start Note : Writing to each bit (except bit 6) of the A-D control register and each bit of the A-D sweep pin select register must be performed while the A-D converter halts (before a trigger occurs). Fig. 12.8.1 Initial setting example for registers relevant to repeat sweep mode 7721 Group User's Manual 12-25 A-D CONVERTER 12.8 Repeat sweep mode 12.8.2 Repeat sweep mode operation description (1) When an internal trigger is selected The operation for the input voltage from the AN0 pin starts when the A-D conversion start bit is set to "1." The A-D conversion of the input voltage from the AN0 pin is completed after 57 cycles of AD. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. For all of the selected analog input pins, the A-D conversion is performed. The conversion result is transferred to the A-D register i each time each pin is converted. For all of the selected analog input pins, the A-D conversion is performed again. The operation is performed repeatedly until the A-D conversion start bit is cleared to "0" by software. (2) When an external trigger is selected The A-D converter starts operation for the input voltage from the AN0 pin when the input level to ______ the ADTRG pin changes from "H" to "L" while the A-D conversion start bit is "1." The A-D conversion of the input voltage from the AN0 pin is completed after 57 cycles of AD. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. For all of the selected analog input pins, the A-D conversion is performed. The conversion result is transferred to the A-D register i each time each pin is converted. For all of the selected analog input pins, the A-D conversion is performed again. The operation is performed repeatedly until the A-D conversion start bit is cleared to "0" by software. ______ When the level of the ADTRG pin changes from "H" to "L" during operation, the operation at that point is cancelled and is restarted from step . Figure 12.8.2 shows the conversion operation in the repeat sweep mode. 12-26 7721 Group User's Manual A-D CONVERTER 12.8 Repeat sweep mode Trigger occur Conversion result Convert input voltage from AN0 pin Conversion result A-D register 0 Convert input voltage from AN1 pin A-D register 1 Convert input voltage from ANi pin Conversion result A-D register i Fig. 12.8.2 Conversion operation in repeat sweep mode 7721 Group User's Manual 12-27 A-D CONVERTER 12.9 Precautions for A-D converter 12.9 Precautions for A-D converter 1. Writing to the following must be performed before a trigger occurs (while the A-D converter halts). *Each bit (except bit 6) of the A-D control register *Each bit of the A-D sweep pin select register _____ 2. When an external trigger is selected, the AN7/ADTRG pin is disconnected from the comparator. Therefore, this pin cannot be used as an analog input pin. When the AN7 pin is selected as an analog input pin while an external trigger is selected, the A-D converter operates, however, an undefined value is stored into the A-D register 7. 3. Refer to "Appendix. 8 Countermeasure against noise" when using the A-D converter. 12-28 7721 Group User's Manual CHAPTER 13 DMA CONTROLLER 13.1 Overview 13.2 Block description [Precautions for DMAC] 13.3 Control 13.4 Operation [Precautions for 2-bus cycle transfer] [Precautions for 1-bus cycle transfer] [Precautions for burst transfer mode] [Precautions for cycle-steal transfer mode] 13.5 Single transfer mode 13.6 Repeat transfer mode 13.7 Array chain transfer mode [Precautions for array chain transfer mode] 13.8 Link array chain transfer mode [Precautions for link array chain transfer mode] 13.9 DMA transfer time DMA CONTROLLER 13.1 Overview 13.1 Overview The DMA controller (hereafter called DMAC) transfers data using the bus and bypassing the CPU. DMAC of the M37721 provides four independent channels of DMA0-DMA3, which have the same function each. In this chapter, the source and destination of each DMA transfer are represented as follows. q Memory A device which needs its own address to be specified Examples: Internal RAM and SFRs, external memory, and memory-mapped I/Os q I/O A device which does not need its own address to be specified Example: External I/O devices 13.1.1 Performance overview Table 13.1.1 lists the performance overview. Table 13.1.1 DMAC performance overview Item Number of channels 4 channels Transfer space 16 Mbytes (between arbitrary spaces) Number of transfer Maximum of 16 Mbytes bytes DMA request source Internal 14 sources and External 1 source Channel priority Transfer rate Data transfer method Transfer unit Fixed or Rotating Maximum of 12.5 Mbytes/sec (at f(XIN) = 25 MHz, 1-bus cycle transfer) Maximum of 6.25 Mbytes/sec (at f(XIN) = 25 MHz, 2-bus cycle transfer) 1-bus cycle or 2-bus cycle transfer Performance specifications 8 or 16 bits Address direction of Fixed, Forward, or Backward transfer (Directions of source and destination are independently selectable.) Transfer mode Burst transfer or Cycle-steal transfer mode Continuous transfer Single transfer, Repeat transfer, Array chain transfer, or Link array chain transfer mode mode 13-2 7721 Group User's Manual DMA CONTROLLER 13.1 Overview 13.1.2 Bus use priority levels The bus use priority levels are fixed by hardware as follows: DRAMC > Hold function > DMAC > CPU (DRAM refresh) Because DMAC has the third priority, it actually operates as follows: * When DRAM refresh request or Hold request is generated during DMA transfer After the transfer of one transfer unit (8-bit or 16-bit data), which is being performed at that time, is complete, DMAC relinquishes the bus to a DRAM refresh or a Hold function. When DMAC regains the right to use bus after the DRAM refresh ends or the Hold state is removed, DMA transfer is restarted at the following address. * When DMA request is generated during DRAM refresh or in Hold state DMAC gains the right to use bus after the DRAM refresh ends or the Hold state is removed. * When DMA request is generated while CPU uses bus Upon end of the bus cycle, DMAC gains the right to use bus if any DRAM refresh request or Hold request is not generated at that time. If a DRAM refresh request or a Hold request is generated when the bus cycle ends, DMAC gains the right to use bus after the DRAM refresh ends or the Hold state is removed. For details, refer to section "13.2.1 Bus access control circuit" and bus request sampling signals in timing diagrams. 13.1.3 Modes DMAC has the following transfer methods and modes. Because these methods and modes are independent each other, any combination between them is selectable. (1) Data transfer method s 2-bus cycle transfer This is a method used to transfer data between memories. A DMA transfer consumes 2 cycles: a read and a write cycle of data. For details, refer to section "13.4.1 2-bus cycle transfer." s 1-bus cycle transfer This is a method used to transfer data between a memory and an I/O. A read and write of data is carried out at the same time (in 1-bus cycle), so that high-speed transfer can be accomplished. For details, refer to section "13.4.2 1-bus cycle transfer." (2) Transfer unit s 8-bit transfer A minimum unit of DMA transfer is 8 bits; that is, an 8-bit data is transferred for one DMA request in the cycle-steal transfer mode. In the burst transfer mode, if a DRAM refresh request or a Hold request is generated during DMA ___ transfer, or if TC input is driven from "H" to "L" to force DMA transfer into termination, DMAC relinquishes the bus after completion of 8-bit data transfer which is being performed at that time. s 16-bit transfer A minimum unit of DMA transfer is 16 bits; that is, a 16-bit data is transferred for one DMA request in the cycle-steal transfer mode. In the burst transfer mode, if a DRAM refresh request or a Hold request is generated during DMA ___ transfer, or if TC input is driven from "H" to "L" to force DMA transfer into termination, DMAC relinquishes the bus after completion of 16-bit data transfer which is being performed at that time. 7721 Group User's Manual 13-3 DMA CONTROLLER 13.1 Overview (3) Transfer modes s Burst transfer mode When once a DMA request is accepted in this mode, an entire batch of data is transferred. Neither is the right to use bus returned to the CPU, nor the DMA request of the channel with the higher ________ priority is accepted until the transfer is complete. However, if an external source (DMAREQi) is selected as a DMA request source with the level sense selected, DMA transfer is performed when _________ the DMAREQi pin's input level is "L," and the right to use bus is returned to the CPU when the _________ DMAREQi pin's input level is "H." Even in this case, any DMA request of the other channels is not accepted until the entire batch of data has been transferred. For details, refer to section "13.4.3 Burst transfer mode." s Cycle-steal transfer mode For each DMA request, 1 transfer unit of data is transferred. (Hereafter, transferring 1-transfer-unit data, which is 8-bit or 16-bit data in the M37721, is called "1-unit transfer.") When 1-unit transfer is complete and another DMA request (including that of other channels) is not generated, the DMAC relinquishes the right to use bus to the CPU. In the cycle-steal transfer mode, all of the DMA request sources are available. For details, refer to section "13.4.4 Cycle-steal transfer mode." Figure 13.1.1 shows the outline of the DMA transfer modes. s Burst transfer mode (Edge sense) DMAi request is accepted. Right to use bus CPU DMAi (Transfer of entire batch of data) CPU s Burst transfer mode (External source (DMAREQi), level sense) DMAREQi input Right to use bus CPU DMAi CPU DMAi s Cycle-steal transfer mode DMA0 request is accepted. DMA0 request is accepted. DMA1 request is accepted. Right to use bus CPU DMA0 (One transfer unit) CPU DMA0 DMA1 (One transfer unit) (One transfer unit) CPU Fig. 13.1.1 Outline of DMA transfer modes 13-4 7721 Group User's Manual DMA CONTROLLER 13.1 Overview (4) Continuous transfer mode s Single transfer mode 1 block of data is transferred once. For details, refer to section "13.5 Single transfer mode." s Repeat transfer mode 1 block of data is transferred repeatedly. For details, refer to section "13.6 Repeat transfer mode." s Array chain transfer mode Several blocks of data are transferred. The transfer parameters (transfer source and destination addresses, the number of transfer bytes) of each block must be located on the memory in series. For details, refer to section "13.7 Array chain transfer mode." s Link array chain transfer mode Several blocks of data are transferred. Transfer parameters for each block can be located on the memory in separate, in a unit of 1block's parameters. For details, refer to section "13.8 Link array chain transfer mode." 7721 Group User's Manual 13-5 DMA CONTROLLER 13.2 Block description 13.2 Block description Figures 13.2.1 and 13.2.2 show the DMAC block diagrams, and relevant registers are described below. Address bus Incrementer/Decrementer Source address register 0 (SAR0) Destination address register 0 (DAR0) Source address register 1 (SAR1) Decrementer Transfer counter register 0 (TCR0) Transfer counter register 1 (TCR1) Transfer counter register 2 (TCR2) Transfer counter register 3 (TCR3) Destination address register 1 (DAR1) Source address register 2 (SAR2) Destination address register 2 (DAR2) Source address register 3 (SAR3) Destination address register 3 (DAR3) DMA latch high-order DMA latch low-order Data bus (Even) Data bus (Odd) : Microcomputer's internal bus : DMAC's internal bus Fig. 13.2.1 DMAC block diagram (1) DRAMC f16 Refresh timer DRAM refresh request BUS REQUEST (DRAMC) BIU CPU wait request Hold function HOLD Hold request BUS REQUEST (Hold) DMAC Array state Channel 0 Channel priority level determination Request source selection DMAREQ0 Software Timer A0 TImer A1 Request Enable Bus access control circuit ST0 ST1 BUS REQUEST (DMAC) Acknowledge signal generation Channel 1 Channel 2 Channel 3 DMAACK0 DMAACK1 DMAACK2 DMAACK3 Fig. 13.2.2 DMAC block diagram (2) 13-6 7721 Group User's Manual DMA CONTROLLER 13.2 Block description 13.2.1 Bus access control circuit In the M37721, the bus is used by DRAMC, Hold function, DMAC, and CPU. When each request of DRAM refresh, Hold, and DMA is generated, each of DRAMC, Hold function, and DMAC issues its bus request to the bus access control circuit in DMAC. (Refer to "Figure 13.2.2.") Table 13.2.1 lists the bus request generating sources. Table 13.2.1 Bus request generating sources Bus request BUS REQUEST (DRAMC) BUS REQUEST (Hold) BUS REQUEST (DMAC) DRAM refresh request (Generated by an underflow of the refresh timer.) Hold request _____ Bus request generating source (Generated by "L"-level input to the HOLD pin.) DMA request (Generated by a DMA request source.) The bus access control circuit relinquishes the right to use bus to the function with the highest priority among functions, which issue bus requests when the BUS REQUEST signal is sampled. This is the bus request acceptance. If any bus request is not generated at bus request sampling, the CPU gains the right to use bus. The bus use priority levels are fixed by hardware, and the bus status is reported by status signal outputs ST0 and ST1. Table 13.2.2 lists the relationship between the bus use priority level, bus status, and status signals. Table 13.2.2 Relationship between bus use priority level, bus status, and status signals Bus use priority level 1 (Highest) 2 3 4 (Lowest) DRAM refresh Hold DMAC CPU (Including the term while the CPU does not use the bus; for example, the term when the CPU is calculating and does not use the bus) Bus status Status signals ST1 0 0 1 1 ST0 0 1 0 1 7721 Group User's Manual 13-7 DMA CONTROLLER 13.2 Block description The BUS REQUEST signal is sampled at a break in bus use. Table 13.2.3 and Figure 13.2.3 shows the timings of bus request sampling. Also, bus request sampling signals are shown in them. Table 13.2.3 Bus request sampling timing Bus user DRAM refresh Hold DMAC Bus request sampling timing After completion of a DRAM refresh cycle Every 1 cycle of All except the following S/R (Note 1) At the end of each block Array/ All except the following Link At the end of each block (Note 1) (except the last block) After completion of 1-unit transfer After 1-unit transfer and terminate-processing (3 cycles of ) etc. are performed sequentially After completion of 1-unit transfer s During transfer in burst transfer mode After the last 1-unit transfer of 1 block, the subsequent 3 cycles of , and a read of the first 2 bytes in the array state of the next block are performed sequentially s During transfer in cycle-steal transfer mode After the last 1-unit transfer of 1 block and the subsequent 3 cycles of are performed sequentially At the end of the last block At an array state CPU When an instruction is After 1-unit transfer and terminate-processing (3 cycles of ) are performed sequentially After a read of 2 bytes of a transfer parameter After completion of 1 bus cycle fetched into queue buffer At a read from or a write into After completion of 1 bus cycle, or after completion of the second bus cycle if a 16-bit data is accessed in a memory unit of 8 bits (Note 2). While CPU does not use bus Every 1 cycle of Notes 1: S = Single transfer mode, R = Repeat transfer mode, Array = Array chain transfer mode, Link = Link array chain transfer mode 2: This applies when the data bus width is 8 bits or when memory is accessed starting at an odd address. If a DRAM refresh request or a Hold request is generated during a data transfer in the burst transfer mode, the request is accepted at the above-mentioned bus request sampling. Another DMA request (including that of other channels) cannot be accepted until the DMA transfer which is in progress normally terminates or is forced into termination. If a DRAM refresh request, a Hold request or another DMA request (including that of other channels) is generated during a data transfer in the cycle-steal transfer mode, the bus request with the highest priority is accepted at the above-mentioned bus request sampling. (If only several DMA requests are generated, the request of the channel whose priority is highest is accepted.) If any bus request is not generated at the above-mentioned bus sampling, the right to use bus is relinquished to the CPU. Note that no DMA request is accepted in array states. 13-8 7721 Group User's Manual DMA CONTROLLER 13.2 Block description s DRAM refresh This is the term in which the bus is not used so that sampi ng is performed every 1 cycle of . Sampling is performed after completion of a refresh cycle. Sampling is performed after completion of 1 bus cycle. E Refresh request BUS REQUEST(DRAMC) Bus request sampling ST1, ST0 H (1, 1) (0, 0) (1, 1) (0, 0) (1, 1) Refresh Transition of right to use bus Transition of right to use bus Refresh Bus used by CPU Transition of right to use bus Transition of right to use bus s Hold E HOLD BUS REQUEST (Hold) Bus request sampling ST1, ST0 H This is the term in which the bus is not used so that sampling is performed every 1 cycle of . This is at Holol state so that sampling is performed every 1 cycle of . Sampling is performed after completion of 1 bus cycle. (1, 1) (0, 1) (1, 1) (1, 1) (0, 1) (1, 1) Hold state Transition of right to use bus Transition of right to use bus Bus used by CPU Transition of right to use bus Hold state Transition of right to use bus s DMA transfer H E DMAREQi DMAi request bit BUS REQUEST (DMAC) Bus request sampling ST1, ST0 (1, 1) (1, 0) (1, 1) (1, 1) (1, 0) (1, 1) This is the term in which the bus is not used so that sampling is performed every 1 cycle of . Sampling is performed after completion of 1-unit transfer. Sampling is performed after completion of 1 bus cycle. DMA transfer Transition of right to use bus Transition of right to use bus DMA transfer Bus used by CPU Transition of right Transition of right to use bus to use bus The above applies on the following conditions: *Cycle-steal transfer mode *DMA request source = external request (DMAREQi) *1-bus cycle transfer *No Wait s CPU This is the term in which the bus is not used so that sampling is performed every 1 cycle of . Sampling is performed after completion of 1 bus cycle. 16-bit data is accessed in a unit of 8 bits, so that sampling is performed after completion of the second bus cycle. E Bus request sampling ST1, ST0 (1, 1) Bus used by CPU When access When 16-bit data is accessed is complete in in a unit of 8 bits 1 bus cycle Fig. 13.2.3 Timing of bus request sampling 7721 Group User's Manual 13-9 DMA CONTROLLER 13.2 Block description 13.2.2 DMAC control register L Figure 13.2.4 shows the structure of DMAC control register L. Bit 0 is described in section "13.3.3 Channel priority levels," and bits 4-7 are also in section "13.3.2 DMA requests." ___ (1) TC pin validity bit (Bit 1) ___ ___ When this bit is set to "1," port P103 functions as the TC pin. The TC pin is of an N-channel opendrain type and provides the following functions: q Terminal count signal output When the transfer of an entire batch of data is normally terminated, the pin outputs "L" for 1 cycle of . (Refer to section "13.3.5 (1) Normal termination.") q Forced termination signal input ___ When the TC pin's input level goes from "H" to "L" during DMA transfer, this DMA transfer is forced into termination. (Refer to section "13.3.5 (2) Forced termination.") b7 b6 b5 b4 b3 b2 b1 b0 DMAC control register L (Address 6816) Bit 0 1 Bit name Priority select bit TC pin validity bit 0 : Fixed 1 : Rotating Functions At reset RW RW RW 0 0 0 : Invalid (P103 pin functions as a programmable I/O port (CMOS).) 1 : Valid (P103 pin functions as TC pin (Nchannel open-drain).) 3, 2 4 5 6 7 Nothing is assigned. DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit 0 : No request 1 : Requested (Note 1) Undefined 0 0 0 0 - RW RW RW RW Notes 1: The state of bits 4 to 7 is not changed when writing "1" to these bits. 2: * When writing to this register while any of DMAi enable bits (bits 4 to 7 at address 6916) is "1," use the LDM or STA instruction in m flag = "1." When DMAi request bit (bits 4 to 7 at address 6816) must not be changed, set DMAi request bit to "1." * When writing to this register while all of DMAi enable bits (bits 4 to 7 at address 6916) are "0," m flag may be "0" or "1." Use the LDM or STA instruction for writing to this register. When DMAi request bit (bits 4 to 7 at address 6816) must not be changed, set DMAi request bit to "1." Fig. 13.2.4 Structure of DMAC control register L 13-10 7721 Group User's Manual DMA CONTROLLER 13.2 Block description 13.2.3 DMAC control register H Figure 13.2.5 shows the structure of DMAC control register H. Each of bits 0-3 is a software DMAi (i = 0 to 3) request bit, which corresponds to each channel. When a software DMA source is selected as a DMA request source, each of these bits is valid. (Refer to "13.3.2 DMA requests.") Bits 4-7 are described in section "13.3.1 DMA enabling." b7 b6 b5 b4 b3 b2 b1 b0 DMAC control register H (Address 6916) Bit 0 1 Bit name Software DMA0 request bit Functions 1 : DMA request (Valid when software DMA source is selected.) The value is "0" at reading. At reset RW WO WO 0 Software DMA1 request bit Software DMA2 request bit Software DMA3 request bit DMA0 enable bit DMA1 enable bit DMA2 enable bit DMA3 enable bit 0 2 3 4 5 6 7 0 0 0 : Disabled 1 : Enabled WO WO RW RW 0 0 0 0 RW RW Note: When any of bits 4 to 7 is set to "1," use the CLB or SEB instruction for writing to this register. Fig. 13.2.5 Structure of DMAC control register H 7721 Group User's Manual 13-11 DMA CONTROLLER 13.2 Block description 13.2.4 Source address register i (SARi) Source address register i (hereafter called SARi) is a 24-bit register with a latch. SARi indicates the transfer source address of the data to be transferred next. The SARi latch has the following functions: * Maintains the value written to the address of SARi (in the single transfer and repeat transfer modes). * Indicates the start address of the transfer parameter memory of the next block (in the array chain transfer and link array chain transfer modes). When a value is written into the address of SARi, the same value is written into SARi and the SARi latch. When writing a value to the address of SARi, all 24 bits must be written. The contents of SARi can be read by reading the address of SARi; however, the value of the SARi latch cannot be read. (Refer to "Tables 13.2.4 and 13.2.5.") 13.2.5 Destination address register i (DARi) Destination address register i (hereafter called DARi) is a 24-bit register with a latch. DARi indicates the transfer destination address of the data to be transferred next. The DARi latch maintains the value written to the address of DARi. When a value is written into the address of DARi, the same value is written into DARi and the DARi latch. When writing a value to the address of DARi, all 24 bits must be written. The contents of DARi can be read by reading the address of DARi; however, the value of the DARi latch cannot be read. (Refer to "Tables 13.2.4 and 13.2.5.") 13.2.6 Transfer counter register i (TCRi) Transfer counter register i (hereafter called TCRi) is a 24-bit register with a latch. TCRi indicates the number of remaining bytes of the block under transfer. The TCRi latch has the following functions: * Maintains the value written to the address of TCRi (in the single transfer and repeat transfer modes). * Indicates the number of remaining blocks (in the array chain transfer mode). When a value is written into the address of TCRi, the same value is written into TCRi and the TCRi latch. When writing a value to the address of TCRi, all 24 bits must be written. The contents of TCRi can be read by reading the address of TCRi; however, the value of the TCRi latch cannot be read. (Refer to "Tables 13.2.4 and 13.2.5.") Table 13.2.4 Addresses of SARi, DARi, and TCRi Channel 0 1 2 3 Source address register i (SARi) 1FC216-1FC016 1FD216-1FD016 1FE216-1FE016 1FF216-1FF016 Destination address register i (DARi) 1FC616-1FC416 1FD616-1FD416 1FE616-1FE416 1FF616-1FF416 Transfer counter register i (TCRi) 1FCA16-1FC816 1FDA16-1FD816 1FEA16-1FE816 1FFA16-1FF816 13-12 7721 Group User's Manual DMA CONTROLLER 13.2 Block description Table 13.2.5 Functions of SARi, DARi, and TCRi Register SARi Mode Single transfer mode Repeat transfer mode Array chain transfer mode SARi Link array chain transfer mode Indicates the transfer source address of the data to be transferred next. SARi latch Maintains the transfer start address of the Indicates the start address of the transfer source. parameter memory of the next block. DARi DARi Indicates the transfer destination address of the data next to be transferred (Not used) (Not used) DARi latch Maintains the transfer start address of the destination. TCRi TCRi Indicates the number of remaining bytes of the block under transfer. TCRi latch Maintains the byte number of the transfer Indicates the number (Not used) (Note) of remaining blocks. data. Note: Any value other than 0 (00000116-FFFFFF16) must be written before DAM transfer. 13.2.7 Incrementer/Decrementer The incrementer/decrementer is a 24-bit register. After every 1-unit transfer, that increments (adds) or decrements (subtract) the contents of SARi and DARi. Table 13.2.6 lists the increment/decrement values. Table 13.2.6 Increment/Decrement values Address directions Transfer unit Forward Backward 8 bits 16 bits +1 +2 -1 -2 13.2.8 Decrementer The decrementer is a 24-bit register. After every 1-unit transfer, that decrements the contents of TCRi by 1 when the transfer unit is 8 bits, and by 2 when 16 bits. In the array chain transfer mode, every time a transfer parameter is read, the contents of the TCRi latch are also decremented by 1. 13.2.9 DMA latch The DMA latch is a 16-bit latch. In 2-bus cycle transfer mode, the DMA latch maintains the value read from the transfer source memory with a read cycle until this value is written into the transfer destination memory. In 1-bus cycle transfer mode, the DMA latch is used to copy data. For copy, refer to section "13.4.2 1-bus cycle transfer." 7721 Group User's Manual 13-13 DMA CONTROLLER 13.2 Block description 13.2.10 DMAi mode register L Figure 13.2.6 shows the structure of DMAi mode register L. For bit 0, refer to section "13.1.3 (2) Transfer unit." For bit 1, refer to section "13.4.1 2-bus cycle transfer" and section "13.4.2 1-bus cycle transfer"; for bit 2, refer to section "13.4.3 Burst transfer mode" and section "13.4.4 Cycle-steal transfer mode." (1) Transfer source address direction select bits (bits 4 and 5) and Transfer destination address direction select bits (bits 6 and 7) Address direction means an order of accessing memory in DMA transfer and is defined as follows: * Fixed direction: an address does not move. * Forward direction: an address moves upward from the specified start address. * Backward direction: an address moves downward from the specified start address. For details, refer to section "13.4.1 (3) Address directions in 2-bus cycle transfer" and section "13.4.2 (3) Address directions in 1-bus cycle transfer." b7 b6 b5 b4 b3 b2 b1 b0 0 DMA0 mode register L (Address 1FCC16) DMA1 mode register L (Address 1FDC16) DMA2 mode register L (Address 1FEC16) DMA3 mode register L (Address 1FFC16) Bit 0 1 2 3 4 5 6 7 Transfer destination address direction select bits Bit name Number-of-unit-transfer-bits select bit (Note) Transfer method select bit Transfer mode select bit Fix this bit to "0." Transfer source address direction select bits b5b4 Functions 0 : 16 bits 1 : 8 bits 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer 0 : Burst transfer mode 1 : Cycle-steal transfer mode At reset RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. b7b6 0 0 0 0 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. Note: When the external data bus has a width of 8 bits and 1-bus cycle transfer is selected, set bit 0 to "1." Fig. 13.2.6 Structure of DMAi mode register L 13-14 7721 Group User's Manual DMA CONTROLLER 13.2 Block description 13.2.11 DMAi mode register H Figure 13.2.7 shows the structure of DMAi mode register H. Bits 0 and 1 are used in 1-bus cycle transfer. For details, refer to section "13.4.2 1-bus cycle transfer." Bits 6 and 7 are the bits for selecting the continuous transfer mode. For details, refer to section "13.5 Single transfer mode" through section "13.8 Link array chain transfer mode." (1) Transfer source wait bit and Transfer destination wait bit (bits 4 and 5) When each of these bits is set to "1," 1-bus cycle in a DMA transfer consumes 3 cycles of , and when cleared to "0," 2 cycles of . These bits are valid for the internal and external areas. In the DRAM area, however, 1-bus cycle consumes 3 cycles of regardless of the states of these bits. (Refer to "CHAPTER 14. DRAM CONTROLLER.") The wait bit (bit 2 at address 5E16) is invalid in DMA transfer. However, Ready function is still valid in DMA transfer. b7 b6 b5 b4 b3 b2 b1 b0 00 DMA0 mode register H (Address 1FCD16) DMA1 mode register H (Address 1FDD16) DMA2 mode register H (Address 1FED16) DMA3 mode register H (Address 1FFD16) Bit 0 1 2 3 4 5 6 7 Bit name Transfer direction select bit I/O connection select bit (Valid in 1-bus cycle transfer) Fix these bits to "0." Functions 0 : From memory to I/O At reset RW RW RW 0 0 0 0 (Used in 1-bus cycle transfer)(Note 1) 1 : From I/O to memory Refer to below. RW RW RW RW RW RW Transfer source wait bit (Note 2) 0 : Wait 1 : No Wait Transfer destination wait bit (Note 2) 0 0 0 0 Continuous transfer mode select bits b7b6 0 0 : Single transfer 0 1 : Repeat transfer 1 0 : Array chain transfer 1 1 : Link array chain transfer Notes 1: Set bit 0 to "0" in 2-bus cycle transfer. 2: Bits 4 and 5 are valid to the external and internal areas. However, DRAM area is always handled with "Wait" regardless of the contents of these bits. The wait bit (bit 2 at address 5E16) is invalid in DMA transfer. Setting for I/O connection select bit Transfer method 2-bus cycle transfer 1-bus cycle transfer 8 bits 16 bits D0-D7 D0-D15 (16-bit I/0 ! 1 or 8-bit I/O ! 2) D0-D7 (8-bit I/O) D8-D15 (8-bit I/O) External data bus width I/O connection Setting for I/O connection select bit It may be either "0" or "1." 0 0 0 1 Fig. 13.2.7 Structure of DMAi mode register H 7721 Group User's Manual 13-15 DMA CONTROLLER 13.2 Block description 13.2.12 DMAi control register Figure 13.2.8 shows the structure of the DMAi control register. For bits 0-4, refer to section "13.3.2 (1) DMA request sources." _________ (1) DMAACKi validity bit (bit 5) _________ When this bit is set to "1," the corresponding pin of port P9 serves as the DMAACKi pin and outputs "L" during a DMA transfer. For details, refer to each timing diagram of section "13.5 Single transfer mode" through section "13.8 Link array chain transfer mode." b7 b6 b5 b4 b3 b2 b1 b0 DMA0 control register (Address 1FCE16) DMA1 control register (Address 1FDE16) DMA2 control register (Address 1FEE16) DMA3 control register (Address 1FFE16) Bit 0 Bit name DMA request source select bits (Note) b3b2b1b0 Functions 0 0 0 0 : Do not select. 0 0 0 1 : External source (DMAREQi) 0 0 1 0 : Software DMA source 0 0 1 1 : Timer A0 0 1 0 0 : Timer A1 0 1 0 1 : Timer A2 0 1 1 0 : Timer A3 0 1 1 1 : Timer A4 1 0 0 0 : Timer B0 1 0 0 1 : Timer B1 1 0 1 0 : Timer B2 1 0 1 1 : UART0 receive 1 1 0 0 : UART0 transmit 1 1 0 1 : UART1 receive 1 1 1 0 : UART1 transmit 1 1 1 1 : A-D conversion 0 : Edge sense (Falling edge) 1 : Level sense ("L" level) At reset RW RW 0 1 0 RW 2 0 RW 3 0 RW 4 Edge sense/Level sense select bit (Used when external source and burst transfer mode are selected) (Note) DMAACKi validity bit 0 RW 5 0 : Invalid (The pin functions as a programmable I/O port.) 1 : Valid (The pin functions as DMAACKi.) 0 RW 7, 6 Nothing is assigned. Undefined - Note: When a certain source other than an external source is selected by bits 0 to 3 or when the cycle-steal transfer mode is selected, set bit 4 to "0." Level sense can be selected only when both of the external source and the burst transfer mode are selected. Fig. 13.2.8 Structure of DMAi control register 13-16 7721 Group User's Manual DMA CONTROLLER 13.2 Block description 13.2.13 DMAi interrupt control register Figure 13.2.9 shows the structure of the DMAi interrupt control register. For details about interrupts, refer to "CHAPTER 7. INTERRUPTS." b7 b6 b5 b4 b3 b2 b1 b0 DMAi interrupt control register (i = 0 to 3) (Addresses 6C16 to 6F16) Bit 0 Bit name Interrupt priority level select bits b2 b1 b0 Functions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 High level 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested At reset RW RW 0 1 0 RW 2 0 RW 3 Interrupt request bit 0 Undefined RW 7 to 4 Nothing is assigned. - Fig. 13.2.9 Structure of DMAi interrupt control register (1) Interrupt priority level select bits (bits 2 to 0) These bits select a DMAi interrupt's priority level. When using DMAi interrupts, select one of the priority levels (1 to 7). When a DMAi interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = "0.") To disable DMAi interrupts, set these bits to "0002" (level 0). (2) Interrupt request bit (bit 3) This bit is set to "1" when a DMAi interrupt request occurs after the DMA transfer is complete. This bit is automatically cleared to "0" when the DMAi interrupt request is accepted. This bit can be set to "1" or cleared to "0" by software. 7721 Group User's Manual 13-17 DMA CONTROLLER 13.2 Block description 13.2.14 Port P9 direction register _________ I/O pins of DMAi are multiplexed with port P9. When using these pins as the DMAREQi input pins, set the corresponding bits of the _________ port P9 direction register to "0" to set these port pins for the input mode. When _________ using these pins as the DMAACKi output pins, these pins are forcibly set to the DMAACKi output pins regardless of the direction register's contents. Figure 13.2.10 shows the relationship between the port P9 direction register and DMAi's I/O pins. b7 b6 b5 b4 b3 b2 b1 b0 Port P9 direction register (Address 1516) Bit 0 1 2 3 4 5 6 7 Corresponding pin DMAACK0 pin DMAREQ0 pin DMAACK1 pin DMAREQ1 pin DMAACK2 pin DMAREQ2 pin DMAACK3 pin DMAREQ3 pin Functions 0 : Input mode 1 : Output mode When using pins P91, P93, P95 and P97 as DMAREQi input pins,set the corresponding bits to "0." At reset RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Fig. 13.2.10 Relationship between port P9 direction register and DMAi's I/O pins [Precautions for DMAC] Do not access the registers relevant to DMAC by using DMA transfers; the address of the accessing register collides with that of the accessed one on the DMAC internal bus. 13-18 7721 Group User's Manual DMA CONTROLLER 13.3 Control 13.3 Control The conditions for performing DMA transfer of DMAi (i = 0-3) are as follows: * Neither a DRAM refresh request nor a Hold request is generated. * A request of the channel with a higher priority than that of DMAi is not generated; or the request is disabled though it has been generated. * DMAi is enabled (DMAi enable bit = "1"). * A DMAi request is generated (DMAi request bit = "1"). The control method for each channel is described below. 13.3.1 DMA enabling Each of DMA channels 0-3 has a DMAi enable bit (bits 4-7 at address 6916). Table 13.3.1 lists the conditions for changing each DMAi enable bit. Table 13.3.1 Conditions for changing DMAi enable bit DMAi enable bit Is set to "1." Is cleared to "0." Conditions for bit change A write of "1" to the DMAi enable bit * A write of "0" to the DMAi enable bit * Transfer of an entire batch of data is complete (normal termination). * A change of TC input level from "H" to "L" during a DMA transfer of DMAi (Note) ___ ___ (Forced termination, when TC pin is valid.) Note: In the burst transfer mode (level sense), however, the term from the DMA transfer start until the transfer completion of an entire batch of data is applied. (It is also valid while the CPU has the right to use bus.) 7721 Group User's Manual 13-19 DMA CONTROLLER 13.3 Control 13.3.2 DMA requests (1) DMA request sources DMA request sources are specified by the DMA request source select bits and the edge sense/level sense select bit. (Refer to "Figure 13.2.8.") Table 13.3.2 lists the conditions for generating a DMA request. Table 13.3.2 Conditions for generating DMA request DMA request sources Condition for generating DMA request _________ External source ________ DMAREQi Level sense "L"-level input to the DMAREQi pin (only in the burst transfer mode) _________ Edge sense Change of the DMAREQi input pin's level from "H" to "L" A write of "1" to the software DMAi request bit (each of bits 0-3 at address 6916; refer to "Figure 13.2.5.") When the interrupt request bit of each peripheral is set to "1" by the activity of peripherals (If "1" is written to any of these interrupt request bits by software, the DMAi request bit does not change. Also, whatever value within 0-7 an interrupt priority level takes, this does not affect DMA requests.) Software DMAi request Timers A0-A4, Timers B0-B2, UART0, UART1, A-D converter (2) Change of DMAi request bit A read of the DMAi request bits (each of bits 4-7 at address 6816) indicates whether the corresponding channel (0-3) is generating its DMA request or not. The DMAi request bit changes synchronized with the falling edge of 1. Table 13.3.3 lists the conditions for changing the DMAi request bit. For the timing of changing the DMAi request bit, refer to "Figures 13.3.2 and 13.3.3." Table 13.3.3 Conditions for changing DMAi request bit DMAi Mode Burst transfer mode Edge sense Level sense Cycle-steal transfer mode Generation of DMAi request (Refer to "Table 13.3.2.") * Start of 1-unit transfer ___ request bit Is set to "1." Generation of DMAi request Generation of DMAi request (Refer to "Table 13.3.2.") (Note) ("L"-level input to the _________ DMAREQi pin) Is cleared to "0." * Normal termination * "H"-level input to the ___ * Change of the TC pin's input _________ DMAREQi pin ___ level from "H "to "L" during ___ * Change of the TC pin's input DMA transfer (when the TC level from "H" to "L" (when ___ pin is valid) the TC pin is valid) * Change of the TC pin's input level from "H" to "L" during ___ DMA transfer (when the TC pin is valid) * A write of "0" to the DMAi * A write of "0" to the DMAi request bit request bit * A write of "0" to the DMAi * A write of "0" to the DMAi enable bit enable bit Note: While the DMAi enable bit is "0," the DMAi request bit is not set to "1" even if a DMA request is generated. When the DMAi enable bit is cleared to "0," also the DMAi request bit is cleared to "0." However, the DMA request generated while the DMAi enable bit = "0" is maintained; and when the DMAi enable bit is set to "1," the DMAi request bit is also set to "1," except for the burst transfer mode (level sense). 13-20 7721 Group User's Manual DMA CONTROLLER 13.3 Control 13.3.3 Channel priority levels When the DMA enable bits of several channels are "1" and their DMA request bits are set to "1," the request of the channel with the highest priority is accepted first. The fixed or rotating channel priority can be selected by the priority select bit (bit 0 at address 6816). The priority levels themselves cannot be specified arbitrary. The channel priority levels are determined after the DMA requests are determined. (1) Fixed priority The fixed priority is selected when the priority select bit (bit 0 at address 6816) = "0." In the fixed priority, the channel priority levels are as follows: channel 0 > channel 1 > channel 2 > channel 3. (2) Rotating priority The rotating priority is selected when the priority select bit = "1." After reset, the priority levels are the same descending order as in the fixed priority: channel 0 > channel 1 > channel 2 > channel 3. Then, after every normal termination of a DMA transfer, the priority levels rotate in such a way that the lowest priority is given to the channel having been performed. When DMA transfer is forced into termination, the channel priority levels does not rotate. Figure 13.3.1 shows an example of determining the channel priority levels. 7721 Group User's Manual 13-21 DMA CONTROLLER 13.3 Control q Priority level: Fixed priority Bus request sampling DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit Channel priority level :0>1>2>3 DMA transfer execution channel 1 2 0 1 3 (Nothing) 0 2 1 1 0 3 q Priority level: Rotating priority Bus request sampling DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit Channel priority level 3>0>1>2 0>1>2>3 3>0>1>2 0>1>2>3 0>1>2>3 DMA transfer execution channel 0>1>2>3 0>1>2>3 0>1>2>3 2>3>0>1 2>3>0>1 1>2>3>0 2>3>0>1 1 2 3 1 3 (Nothing) 0 2 3 1 3 3 The above timing diagram applies on the following conditions: * No DRAM refresh request, no Hold request * All of DMAi enable bits are "1." Fig. 13.3.1 Example of determining channel priority levels 13-22 7721 Group User's Manual DMA CONTROLLER 13.3 Control 13.3.4 Processing from DMA request until DMA transfer execution DMA requests are sampled at every falling edge of 1; when requested, the DMAi request bit is set to "1." Then, the channel priority levels and bus use priority levels are determined, and BUS REQUEST (DMAC) goes "1" if any DRAM refresh request or Hold request is not generated (Note). BUS REQUEST (DMAC) signal is sampled while the bus request sampling signal is "1" and is accepted (DMA request acceptance). Figure 13.3.2 shows an example of timing from the determination of a DMA request until the DMA transfer execution. Refer to section "13.9 DMA transfer time" for the time from DMA request generation until the CPU's regaining the right to use bus via DMA transfer. Note: In the following cases, BUS REQUEST (DMAC) does not go "1." However, the DMAi request bit remains set to "1." Accordingly, after completion of each state, the channel priority levels and bus use priority levels are determined, and BUS REQUEST (DMAC) goes "1" if any DRAM refresh request or Hold request is not generated. q When a DMA request is generated during a burst transfer or in an array state (However, if a DRAM refresh request or Hold request is generated during this term, its BUS REQUEST goes "1.") q When a DMA request is not accepted with a DRAM refresh request or Hold request generated 7721 Group User's Manual 13-23 DMA CONTROLLER 13.3 Control When DMAi request is sampled at this point Transition of right to use bus 1-unit transfer Write cycle V: Channel priority level determination and bus use priority level determination (1.5 cycles of ) V 1 ALE E R/W Address Address/Data 1 Read cycle PC PC,PG SAR SAR Data DAR DAR Data DMAi enable bit DMAREQi DMAi request bit When Burst transfer mode (edge sense) selected When Burst transfer mode (level sense) selected When Cycle-steal transfer mode selected BUS REQUEST(DMAC) Bus request sampling DMAACKi TC ST1 ST0 DMAi interrupt request bit 0 H The above timing diagram applies on the following conditions: * Single transfer mode, or Repeat transfer mode * 2-bus cycle transfer * No Wait * DMAACKi valid, TC valid * External source (DMAREQi) * After DMAi request occurs ("L" is input to the DMAREQi pin.), the right to use bus is relinquished to DMAC at the shortest time. Fig. 13.3.2 Example of timing from determination of DMA request until DMA transfer execution 13-24 7721 Group User's Manual DMA CONTROLLER 13.3 Control 13.3.5 Termination of DMA transfer As the methods of terminating DMA transfer, normal and forced termination are used. (1) Normal termination All of the DMAi transfers terminate and DMAC stops. This method is used in the single transfer, array chain transfer, and link array chain transfer modes. In the repeat transfer mode, however, normal termination cannot be applied to terminating transfer; then, forced termination must be used. (Refer to "(2) Forced termination" of this section.) Table 13.3.4 lists the states of DMAC at normal termination. Table 13.3.4 States of DMAC at normal termination Item DMAi interrupt request bit DMAi request bit 1 In the burst transfer mode (edge sense): 0 In the burst transfer mode (level sense): not changed In the cycle-steal transfer mode: not changed (Note) DMAi enable bit ___ State 0 ___ TC output Outputs "L" (when the TC pin is valid) Rotating (when the rotating priority is selected) Channel priority levels Note: In the cycle-steal transfer mode, the DMAi request bit is cleared to "0" when a DMA request is accepted. This bit is does not change at normal termination. At normal termination, the CPU regains the right to use bus after the terminate processing (3 cycles of ) via the transition of the right to use bus (1 cycle of ). Figure 13.3.3 shows a timing example at normal termination. 7721 Group User's Manual 13-25 DMA CONTROLLER 13.3 Control Transition of right to use bus Terminate processing 1 ALE E R/W Address Address/Data DMAi enable bit DMAi request bit L SAR 1 SAR 1 0 BUS REQUEST (DMAC) When Burst transfer mode (edge sense) selected When Burst transfer mode (level sense) selected When Cycle-steal transfer mode selected 0 Bus request sampling DMAACKi TC ST1 ST0 DMAi interrupt request bit The above timing diagram applies on the following conditions: * DMAACKi valid, TC valid * External source (DMAREQi) Fig. 13.3.3 Timing example at normal termination 13-26 7721 Group User's Manual DMA CONTROLLER 13.3 Control (2) Forced termination The methods of terminating DMAC other than normal termination are as follows: ___ ___ * Drives the TC pin's input level from "H" to "L" during a DMA transfer (when the TC pin is valid). * Writes "0" to the DMAi enable bit. Table 13.3.5 lists the states of DMAC at forced termination. Table 13.3.5 States of DMAC at forced termination Item DMAi interrupt request bit DMAi request bit DMAi enable bit ___ State Not changed. 0 0 Not changed. Not changed. ___ TC output Channel priority levels ___ When the TC pin is used for forced termination, select "TC pin valid" (bit 1 at address 6816 = "1"). ___ Forced termination by the TC input is valid in the following cases: * During a DMA transfer in the burst transfer mode (edge sense) * During the term from the DMA transfer start until the transfer completion of an entire batch of data in the burst transfer mode with the level sense selected. (It is also valid while the CPU has the right to use bus). ___ * During a DMA transfer in the cycle-steal transfer mode (Forced termination by the TC input is invalid while the CPU has the right to use bus.) The TC pin's input is determined at the falling edge of 1, and DMAC will relinquish the right to use bus to the CPU upon completion of the 1-unit transfer under execution at that time. _ ___ At the forced termination by the DMAi enable bit, "0" is written to this bit at the rising edge of E of a write cycle to the DMAi enable bit. Accordingly, DMAi is disabled after this write. 7721 Group User's Manual 13-27 DMA CONTROLLER 13.3 Control 13.3.6 DMA transfer restart after termination (1) Restarting the same DMA transfer as the previous one from the beginning At normal and forced termination, the latches of SARi, DARi, and TCRi maintain their values written before the transfer start. (Refer to "Figure 13.3.4-a.") Therefore, DMA transfer must be restarted according to the following procedures: q In single or repeat transfer mode Set the DMAi enable bit to "1." It is not necessary to re-set the values of SARi, DARi, and TCRi by software. (Refer to "Figure 13.3.4-b.") q In array chain or link array chain transfer mode Re-set the values of SARi and TCRi. Set the DMAi enable bit to "1." (2) Restarting transfer of data subsequent to one which has been transferred just before forced termination When reading values at the addresses of SARi, DARi, and TCRi after forced termination, the values of these registers (counters) can be read. These read values are the transfer source address, the transfer destination address which were to be transferred subsequently, and the number of remaining bytes. When writing these read values to the addresses of SARi, DARi, and TCRi respectively, the same values are also written to their latches. When setting the DMAi enable bit to "1" under this condition, transfer of data subsequent to one which has been transferred just before forced termination is restarted. (Refer to "Figure 13.3.4-c.") q In single transfer mode The remaining data can be transferred by the following procedure: Read the values at addresses of SARi, DARi and TCRi. Then, rewrite these values into these addresses. Set the DMAi enable bit to "1." q In repeat transfer, array chain transfer, and link array chain transfer modes The remaining data of the block that was interrupted by forced termination can be transferred by the following procedure: Switch over the current mode to the single transfer mode. Read the values at addresses of SARi, DARi and TCRi. Then, rewrite these values into these addresses. Set the DMAi enable bit to "1." (Refer to "Figure 13.3.4-c.") In order to transfer the next block, switch over the current mode to the previous mode after the above-mentioned transfer is normally terminated. Then, re-set the values of SARi, DARi, and TCRi. In the array chain or the link array chain transfer mode, information such as the next transfer parameters etc. cannot be read from each latch. 13-28 7721 Group User's Manual DMA CONTROLLER 13.3 Control a. State at forced termination Latch Previously written values Register Addresses which were to be transferred subsequently or the number of remaining bytes b. When setting DMAi enable bit to "1" without rewriting values at addresses of SARi, DARi, and TCRi A value read from each latch is used by hardware only at the first 1-unit transfer. The contents updated by the incrementer/decrementer and the decrementer are loaded in each register. Values are used by reading them from registers at the second and the following 1-unit transfers. Latch Previously written values Register Addresses which were to be transferred subsequently or the number of remaining bytes Transfer source/destination address is specified. Contents are updated by incrementer/decrementer and decrementer. Updated contents are written. c. When reading values at addresses of SARi, DARi, and TCRi after forced termination and rewriting them Latch Previously written values Written by software Register Addresses which were to be transferred subsequently or the number of remaining bytes Addresses which were to be transferred subsequently or the number of remaining bytes Read by software Fig.13.3.4 States of SARi, DARi, TCRi after forced termination 7721 Group User's Manual 13-29 DMA CONTROLLER 13.4 Operation 13.4 Operation Operation of 1-unit transfer varies according to the data transfer method (2-bus cycle or 1-bus cycle transfer). In addition, how many units of transfer data are transferred for a DMA request varies according to the transfer mode (burst transfer or cycle-steal transfer mode). These data transfer methods and modes are described below. 13.4.1 2-bus cycle transfer When the transfer method select bit (Refer to "Figure 13.2.6.") = "0," 2-bus cycle transfer is selected. 2bus cycle transfer is the method used to transfer data between memories. Since this method has a read and a write cycle, it consumes a minimum of 2 bus cycles for 1-unit transfer. Figure 13.4.1 shows an example of connecting external memories in 2-bus cycle transfer. M37721 Address bus Data bus D8-D15 Data bus D0-D7 Transfer destination memory (Even address) Transfer destination memory (Odd address) Transfer source memory (Even address) Transfer source memory (Odd address) E BHE BLE R/W Note. The external circuit such as an address latch is disregarded. Fig. 13.4.1 Example of connecting external memories in 2-bus cycle transfer 13-30 7721 Group User's Manual DMA CONTROLLER 13.4 Operation (1) Register operation in 2-bus cycle transfer Figure 13.4.2 shows a basic operation of registers for 1-unit transfer in 2-bus cycle transfer. For register values to be specified, refer to section "13.5 Single transfer mode" through section "13.8 Link array chain transfer mode." It is because that these values vary according to continuous transfer modes. In 2-bus cycle transfer, the data read at a read cycle is maintained temporarily in the DMA latch, and the contents of this latch are written to a memory at a write cycle. (1) Read cycle DMAC SARi SARi latch Incrementer/ Decrementer Memory Transfer source address is specified by SARi (Note). Contents of TCRi are updated by decrementer (Note) ; when value read from TCRi is "0," transfer of 1 data block is terminated. Contents of SARi are updated by incrementer/ decrementer. Data is read from memory and maintained in DMA latch. DARi DARi latch TCRi TCRi latch DMA latch Decrementer (Transfer source) (Transfer destination) (2) Write cycle DMAC SARi SARi latch Incrementer/ Decrementer Memory Transfer destination address is specified by DARi (Note). Contents of DARi are updated by incrementer/ decrementer. Contents of DMA latch are written to memory. DARi DARi latch TCRi TCRi latch DMA latch Decrementer (Transfer source) (Transfer destination) V When the transfer unit is 16 bits * When an even address is accessed with 16-bit external data bus width, data can be read or written at 1-bus cycle. Accordingly, the incrementer/decrementer and the decrementer increment or decrement by 2, and sequences through are performed once. * When an odd address is accessed with 16-bit external data bus width or when 8 bits is used as external data bus width, data is read or written at 2-bus cycles, and sequences through or through are repeated twice. The incrementer/decrementer and the decrementer increment or decrement by 1 every time sequences through or through are performed once. Note: In the single transfer mode and repeat transfer mode, only at the first transfer of the block, the values read from SARi latch, DARi latch, and TCRi latch are used. (The results obtained by increment or decrement are written to SARi, DARi, and TCRi. Except for the first transfer of the block, the values read from SARi, DARi, and TCRi are used.) Fig. 13.4.2 Basic operation of registers for 1-unit transfer in 2-bus cycle transfer 7721 Group User's Manual 13-31 DMA CONTROLLER 13.4 Operation (2) Bus operation in 2-bus cycle transfer The time required for 1-unit transfer in 2-bus cycle transfer is given by the following formula: Transfer time per 1-unit transfer = (Read cycle) + (Write cycle) Since any area can be specified as a transfer source or a transfer destination, a read cycle varies with the conditions of a transfer source, and a write cycle with that of a transfer destination. Table 13.4.1 lists the time required for a read or write cycle per 1-unit transfer in 2-bus cycle transfer, and Figure 13.4.3 shows the bus-cycle operation waveforms in 2-bus cycle transfer. Table 13.4.1 Time required for a read or write cycle per External Transfer Address directions Data's start bus width unit address 16 bits 16 bits Fixed/Forward Even (including Odd internal Backward Even bus) Odd 8 bits 8 bits 16 bits 8 bits Fixed/Forward/ Backward Fixed/Forward/ Backward Even/Odd Even/Odd 1-unit transfer in 2-bus cycle transfer Read/Write cycle (Unit: cycle) Formula 1+i 2 + 2i 2 + 2i 2+i 1+i 2 + 2i No Wait 2 (a) 4 (c) 4 (c) 3 (b) 2 (a) 4 (c) With Wait DRAM 3 (d) 6 (f) 6 (f) 4 (e) 4 (e) 3 (d) 6 (f) (Note) area 3 (d) F i x e d / F o r w a r d / Even/Odd 2 (a) 1+i Backward Address directions: Refer to section "13.4.1 (3) Address directions in 2-bus cycle transfer." _ i: A term of E = "L" in 1-bus cycle; i = 1 at "No Wait", and i = 2 at "With Wait" or "DRAM area". When Ready function is used (Refer to section "3.3 Ready function."), the number of cycles extended by Ready must be added. ( ): Indicates the corresponding waveform in Figure 13.4.3. Note: When a transfer destination applies to this condition, 2-bus cycle transfer cannot be performed. When a transfer source applies to this condition and a transfer destination is in the DRAM area, 2-bus cycle transfer cannot also be performed. 13-32 7721 Group User's Manual DMA CONTROLLER 13.4 Operation Internal clock A/D E ALE A D (a) A/D E ALE A A-1 D (b) A/D (c) E ALE A D A1 D A/D E ALE A D (d) A/D (e) E ALE A A-1 D A/D (f) E ALE A D A1 D A: Address, D : Data : Read or write term per 1-unit transfer Fig. 13.4.3 Bus-cycle operation waveforms in 2-bus cycle transfer 7721 Group User's Manual 13-33 DMA CONTROLLER 13.4 Operation (3) Address directions in 2-bus cycle transfer In 2-bus cycle transfer, the address direction of a transfer source and that of a transfer destination each can be selected independently. (Refer to "Figure 13.2.6.") Addresses move in the specified direction by the transfer unit. Tables 13.4.2 through 13.4.4 list address directions in 2-bus cycle transfer and examples of transfer result. Tables 13.4.2 Address directions in 2-bus cycle transfer and examples of transfer result (1) External data bus width : 16 bits or 8 bits Address direction Transfer unit : 16 bits Transfer unit : 8 bits Data arrangement Data arrangement on Data arrangement Data arrangement on Transfer Transfer on transfer source Transfer on transfer source Transfer transfer destination transfer destination source destination sequence sequence memory memory memory (transfer result) memory (transfer result) Fixed Fixed V Low order Data High order Low order V Data High order V Data Data V Fixed Forward V Low order Data High order Low order V Data High order Low order Data High order Low order Data High order V Data Data Data Data Data Data Data V Fixed Backward V Low order Data High order Low order Data High order Low order Data High order Low order Data High order V V Data Data Data Data V Data Data Data V : Transfer start address 13-34 7721 Group User's Manual DMA CONTROLLER 13.4 Operation Tables 13.4.3 Address directions in 2-bus cycle transfer and examples of transfer result (2) External data bus width : 16 bits or 8 bits Address direction Transfer unit : 16 bits Transfer unit : 8 bits Data arrangement Data arrangement on Data arrangement Data arrangement on Transfer Transfer on transfer source Transfer on transfer source Transfer transfer destination transfer destination source destination sequence sequence memory memory memory (transfer result) memory (transfer result) Forward Fixed V Low order Data 1 High order Low order Data 2 High order Low order Data 3 High order Low order V Data 1-3 High order V Data 1 Data 2 Data 3 Data 1-6 Data 4 Data 5 Data 6 V Forward Forward V Low order Data 1 High order Low order Data 2 High order Low order Data 3 High order Low order V Data 1 High order Low order Data 2 High order Low order Data 3 High order V Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 V Forward Backward V Low order Data 1 High order Low order Data 2 High order Low order Data 3 High order Low order Data 3 High order Low order Data 2 High order Low order Data 1 High order V V Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 V Note: The position relationship between loworder byte and high-order byte is not reversed. V : Transfer start address 7721 Group User's Manual 13-35 DMA CONTROLLER 13.4 Operation Tables 13.4.4 Address directions in 2-bus cycle transfer and examples of transfer result (3) External data bus width : 16 bits or 8 bits Address direction Transfer unit : 16 bits Transfer unit : 8 bits Data arrangement Data arrangement on Data arrangement Data arrangement on Transfer Transfer on transfer source Transfer on transfer source Transfer transfer destination transfer destination source destination sequence sequence memory memory memory (transfer result) memory (transfer result) Backward Fixed Low order V Data 1-3 High order Low order Data 3 High order Low order Data 2 High order Low order Data 1 High order Data 6 Data 5 Data 4 Data 3 Data 2 V Data 1 Data 1-6 V V Backward Forward Low order Data 3 High order Low order Data 2 High order Low order Data 1 High order Low order Data 1 High order Low order Data 2 High order Low order Data 3 High order V Data 6 Data 5 Data 4 Data 3 Data 2 V Data 1 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 V V Backward Backward Low order Data 3 High order Low order Data 2 High order Low order Data 1 High order Low order Data 3 High order Low order Data 2 High order Low order Data 1 High order V Data 6 Data 5 Data 4 Data 3 Data 2 V Data 1 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 V V V : Transfer start address 13-36 7721 Group User's Manual DMA CONTROLLER 13.4 Operation [Precautions for 2-bus cycle transfer] When the 16-bit external data bus width = 16 bits and the transfer unit = 16 bits under the following conditions, 2-bus cycle transfer cannot be performed. (Refer to "Table 13.4.1.") * Conditions for transfer destination Transfer destination = DRAM area, Address direction = Backward, Data's start address = Odd address * Conditions for transfer source and destination Transfer source = DRAM area, Address direction = Backward, Data's start address = Odd address Transfer destination = DRAM area 7721 Group User's Manual 13-37 DMA CONTROLLER 13.4 Operation 13.4.2 1-bus cycle transfer When the transfer method select bit (Refer to "Figure 13.2.6.") = "1," 1-bus cycle transfer is selected. 1-bus cycle transfer is the method used to transfer data between a memory and an I/O. In this method, a read and write of 1-tansfer-unit data are simultaneously performed during 1-bus cycle. The address bus, ____ ____ __ BHE, BLE, and R/W indicate the states of memory. Figure 13.4.4 shows an example of connecting external memories and I/Os in 1-bus cycle transfer. M37721 Address bus Data bus (D8-D15) Data bus (D0-D7) Memory (Even address) Memory (Odd address) I/O I/O E BHE BLE R/W DMAACKi DMAREQi Note. The external circuit such as an address latch is disregarded. Fig. 13.4.4 Example of connecting external memories and I/Os in 1-bus cycle transfer 13-38 7721 Group User's Manual DMA CONTROLLER 13.4 Operation In 1-bus cycle transfer, the following considerations must be taken in designing the system: * Achieve the condition that 1-transfer-unit data can be accessed in 1-bus cycle. (Refer to "Table 13.4.5.") * Specify the transfer address direction and I/O connections. (Refer to "Figure 13.2.7.") * Compose the read and write signal generating circuit externally. (These signals are for I/Os.) The M37721 outputs signals to the memory. Accordingly, make sure to compose the circuit which generates write signals for I/Os when the M37721 outputs read signals; which generates read signals for I/Os when the M37721 outputs write signals. Figure 13.4.5 shows an example of the circuit generating a write signal and a read signal for I/Os. M37721 Generating circuit for read and write signals to I/Os I/O R/W DMAACKi Read Write DMA acknowledge DMAREQi DMA request E Fig. 13.4.5 Example of circuit generating write signal and read signal for I/Os 7721 Group User's Manual 13-39 DMA CONTROLLER 13.4 Operation (1) Register operation in 1-bus cycle transfer Figure 13.4.6 shows a basic operation of registers for 1-unit transfer in 1-bus cycle transfer. For register values to be specified, refer to section "13.5 Single transfer mode" through section "13.8 Link array chain transfer mode." It is because these values vary depending on each continuous transfer mode. In 1-bus cycle transfer, a read and write of 1-transfer-unit data are simultaneously performed during 1-bus cycle. qWhen transferring from memory to I/O DMAC SARi SARi latch Incrementer/ Decrementer Memory Transfer source address is specified by SARi (Note). Contents of TCRi are updated by decrementer (Note); when value read from TCRi is "0," transfer of 1 data block is terminated. Contents of SARi are updated by incrementer/ decrementer. I/O is specified by DMAACKi. Data is output from memory and is written to I/O simultaneously (R/W = H level). DARi DARi latch TCRi TCRi latch DMA latch Decrementer (Transfer source) I/O DMAACKi (Transfer destination) qWhen transferring from I/O to memory DMAC SARi SARi latch Incrementer/ Decrementer Memory Transfer source address is specified by DARi (Note). Contents of TCRi are updated by decrementer (Note); when value read from TCRi is "0," transfer of 1 data block is terminated. Contents of DARi are updated by incrementer/ decrementer. I/O is specified by DMAACKi. Data is output from I/O and is written to memory simultaneously (R/W = L level). DARi DARi latch TCRi TCRi latch DMA latch Decrementer (Transfer destination) I/O DMAACKi (Transfer source) V When the transfer unit is 16 bits, the incrementer/decrementer and the decrementer increment or decrement by 2. Note: In the single transfer mode and repeat transfer mode, only at the first transfer of the block, the values read from SARi latch, DARi latch, and TCRi latch are used. (The results obtained by increment or decrement are written to SARi, DARi, and TCRi. Except for the first transfer of the block, the values read from SARi, DARi, and TCRi are used.) Fig. 13.4.6 Basic operation of registers for 1-unit transfer in 1-bus cycle transfer 13-40 7721 Group User's Manual DMA CONTROLLER 13.4 Operation (2) Bus operation in 1-bus cycle transfer The time required for 1-unit transfer in 1-bus cycle transfer is given by the following formulas: * Transfer from memory to I/O: Transfer time per 1-unit transfer = (Read cycle of memory) * Transfer from I/O to memory: Transfer time per 1-unit transfer = (Write cycle of memory) In 1-bus cycle transfer, 1-transfer-unit data is accessed in 1-bus cycle, so that limitations are imposed on the transfer conditions to be applied. Table 13.4.5 lists the conditions of 1-bus cycle transfer and the transfer time per 1-unit transfer, and Figure 13.4.7 shows the bus-cycle operation waveforms in 1-bus cycle transfer. Table 13.4.5 Conditions of 1-bus cycle transfer and Transfer time per 1-unit transfer Address directions External Transfer Read/Write cycle (Unit: cycle) Data's start bus width unit address No Wait With Wait DRAM Formula 3 (c) 16 bits 16 bits Fixed/Forward 2 (a) 1+i Even (including internal bus) 8 bits 8 bits 16 bits 8 bits Odd Backward Fixed/Forward/ Backward Fixed/Forward/ Backward Even Odd Even/Odd Even/Odd 2+i 1+i 3 (b) 2 (a) 4 (d) 3 (c) area 3 (c) F i x e d / F o r w a r d / Even/Odd 2 (a) 1+i Backward Address directions: Refer to section "13.4.2 (3) Address directions in 1-bus cycle transfer." There is no address direction on the I/O side. _ i: A term of E = `L" in 1-bus cycle; i = 1 at "No Wait", and i = 2 at "With Wait" or "DRAM area". When Ready function is used (Refer to section "3.3 Ready function."), the number of cycles extended by Ready must be added. ( ): Indicates the corresponding waveform in Figure 13.4.7. /: 1-bus cycle transfer cannot be performed. When the external data bus width = 16 bits and the transfer unit = 8 bits are selected, the data bus which the memory uses and the data bus to which I/O is connected may be different. In such a case, data is copied from the data bus of a transfer source to that of a transfer destination by using the DMA latch. For the combination that data copy may occur, data copy delay time td(data) must be taken into consideration. Table 13.4.6 lists the data flows on the data bus in 1-bus cycle transfer, and Table 13.4.7 lists the outputs of the address bus, the data bus, and the bus control signals in 1-bus cycle transfer. 7721 Group User's Manual 13-41 DMA CONTROLLER 13.4 Operation Internal clock A/D E (a) ALE A D A/D (b) E ALE A A-1 D A/D (c) E ALE A D A/D (d) E ALE A A-1 D A : Address, D : Data : Transfer term per 1-unit transfer Fig. 13.4.7 Bus-cycle operation waveforms in 1-bus cycle transfer 13-42 7721 Group User's Manual DMA CONTROLLER 13.4 Operation Table 13.4.6 Data flows on data bus in 1-bus cycle transfer External data Transfer I/O bus width unit connection Read/Write address of memory M37721 Data flow 16 bits Data bus D0-D7 and D8-D15 16 bits Even address and Odd address Memory Memory I/O I/O Data bus D8-D15 Data bus D0-D7 M37721 Even address Memory Memory I/O Data bus D8-D15 Data bus D0-D7 16 bits Data bus D0-D7 8 bits M37721 Data bus D8-D15 (Note) Data bus D0-D7 Memory Memory I/O Odd address Note: Data is copied from data bus D0-D7 to D8-D15 or from data bus D8-D15 to D0-D7 in the M37721's DMAC. Note the data copy delay time td(data). M37721 Data bus D8-D15 (Note) Data bus D0-D7 Memory Memory I/O Even address 16 bits Data bus D8-D15 Note: Data is copied from data bus D0-D7 to D8-D15 or from data bus D8-D15 to D0-D7 in the M37721's DMAC. Note the data copy delay time td(data). 8 bits M37721 Odd address Memory Memory I/O Data bus D8-D15 Data bus D0-D7 M37721 8 bits Data bus D0-D7 8 bits Even address and Odd address Memory I/O Data bus D0-D7 Note: When the memory is the internal memory or SFR, the above case for external data bus width = 16 bits applies. 7721 Group User's Manual 13-43 DMA CONTROLLER 13.4 Operation Table 13.4.7 Outputs of address bus, data bus, and bus control signals in 1-bus cycle transfer Output of address bus, data bus, and bus control signals External data bus width I/O Transfer connection unit Read/Write address of memory Transferred from memory to I/O E R/W H Transferred from I/O to memory L A8/D8-A15/D15 Transfer source address Transfer source address Odd address data Even address data Transfer destination address Transfer destination address 16 bits Data bus D0-D7 and D8-D15 16 bits Even address and Odd address A16/D0-A23/D7 BHE BLE L L L L Transfer source address Transfer source address Invalid data Even address data Transfer destination address Transfer destination address A8/D8-A15/D15 Invalid data Even address A16/D0-A23/D7 H H BHE BLE 16 bits Data bus D0-D7 L L Transfer source address Transfer source address Copy Transfer destination address Transfer destination address 8 bits A8/D8-A15/D15 I/O data Odd address A16/D0-A23/D7 BHE BLE L H Odd address data Copy L H A8/D8-A15/D15 A16/D0-A23/D7 Transfer source address Transfer source address Even address data Copy Transfer destination address Transfer destination address Copy I/O data Even address Data bus D8-D15 H H BHE BLE L L Transfer source address Transfer source address Odd address data Invalid data Transfer destination address Transfer destination address 16 bits 8 bits A8/D8-A15/D15 Odd address A16/D0-A23/D7 BHE BLE L H Invalid data L H 8 bits Data bus D0-D7 8 bits Even address and Odd address A8-A15 A16/D0-A23/D7 Transfer source address Transfer source address Transfer destination address Data Transfer destination address : When the memory is the internal memory or SFR, data is output. When the memory is the external memory, it enters a floating state. 13-44 7721 Group User's Manual DMA CONTROLLER 13.4 Operation (3) Address directions in 1-bus cycle transfer In 1-bus cycle transfer, the transfer source and destination address directions of memory are selectable. (Refer to "Figure 13.2.6.") Addresses move in the specified direction by the transfer unit. Tables 13.4.8 and 13.4.9 list address directions in 1-bus cycle transfer and examples of transfer results. Table 13.4.8 Address directions in 1-bus cycle transfer and examples of transfer results (1) External data bus width : 16 bits Address direction Transfer unit : 16 bits Transfer unit : 8 bits Transfer Transfer Data arrangement Data arrangement Transfer source destination on transfer source Transfer Transfer destination on transfer source sequence Transfer destination I/O I/O sequence memory memory memory I/O Fixed -- V Low order Data High order Low order Data High order V Data Data External data bus width : 16 bits or 8 bits Forward -- V Low order Data 1 High order Low order Data 2 High order Low order Data 3 High order Low order Data 1-3 High order V Data 1 Data 2 Data 3 Data 1-6 Data 4 Data 5 Data 6 Backward -- Low order Data 3 High order Low order Data 2 High order Low order Data 1 High order Low order Data 1-3 High order Data 6 Data 5 Data 4 Data 1-6 Data 3 Data 2 V Data 1 V V : Transfer start dd 7721 Group User's Manual 13-45 DMA CONTROLLER 13.4 Operation Table 13.4.9 Address directions in 1-bus cycle transfer and examples of transfer results (2) External data bus width : 16 bits Address direction Transfer unit : 16 bits Transfer Transfer source destination I/O memory -- Fixed Low order Data High order Low order V Data High order V Data Data V Transfer source I/O Data arrangement on Transfer transfer destination sequence memory (transfer result) Transfer unit : 8 bits Transfer source I/O Data arrangement on Transfer transfer destination sequence memory (transfer result) External data bus width : 16 bits or 8 bits -- Forward Low order Data High order Low order V Data High order Low order Data High order Low order Data High order Data Data Data Data Data Data Data V -- Backward Low order Data High order Low order Data High order Low order Data High order Low order Data High order V Data Data Data Data Data Data Data V V : Transfer start dd 13-46 7721 Group User's Manual DMA CONTROLLER 13.4 Operation [Precautions for 1-bus cycle transfer] 1. The area that overlaps with internal RAM and SFRs must not be assigned to an external memory. When the contents in the overlapped area are read, the data of internal RAM or SFRs and that of external memory are simultaneously placed on the data bus; and they collide with each other. 2. For the system that transfers data with 16-bit external data bus width from an external memory to an 8-bit I/O, the external memory must be composed to be read in a unit of 8 bits. If the external memory cannot be read in a unit of 8 bits, the data read from the external memory at data copy collides with the copied data on the data bus. 3. Under the following conditions, 1-bus cycle transfer cannot be performed. (Refer to "Table 13.4.5."): q External data bus width = 16 bits, Transfer unit = 16 bits, Address direction of memory = Fixed or Forward, Data's start address of memory = Odd q External data bus width = 16 bits, Transfer unit = 16 bits, Address direction of memory = Backward, Data's start address of memory = Even q External data bus width = 16 bits, Transfer unit = 16 bits, Target memory of DMA transfer = DRAM area, Address direction of memory = Backward, Data's start address of memory = Odd q External data bus width = 8 bits, Transfer unit = 16 bits 7721 Group User's Manual 13-47 DMA CONTROLLER 13.4 Operation 13.4.3 Burst transfer mode The burst transfer mode can operate in either edge sense or level sense mode. (1) Burst transfer mode (edge sense) When the transfer mode select bit = "0" and the edge sense/level sense select bit = "0," this mode is selected. (Refer to "Figures 13.2.6 and 13.2.8.") In this mode, all of the DMA request sources are available. Figure 13.4.8 shows a transfer example in the burst transfer mode (edge sense). When once a DMA request is accepted in this mode, an entire batch of data is transferred: the right to use bus is not returned to the CPU until the transfer is complete. During a burst transfer, any DMA request (including that of other channels) cannot be accepted. However, the BUS REQUEST signal is sampled basically at every completion of 1-unit transfer. (Refer to "Table 13.2.3.") When a DRAM refresh request or Hold request is generated at this time, the right to use bus is not returned to the CPU, and the request is accepted. When the transfer of an entire batch of data is complete, the DMAC relinquishes the right to use bus to the CPU. When the next DMA request is generated, the right is once returned to the CPU to sample the DMA request. (2) Burst transfer mode (level sense) When the transfer mode select bit = "0" and the edge sense/level sense select bit = "1 ," this mode is selected. (Refer to "Figures 13.2.6 and 13.2.8.") In this mode, only the external source is used as a DMA request source. Set the DMA request source select bits to "00012." (Refer to "Figure 13.2.8.") Figure 13.4.9 shows a transfer example in the burst transfer mode (level sense). _________ When the DMAREQi pin's input level = "L," the DMAi request bit is cleared to "0"; when this pin's input level = "L," the DMAi request bit is set to "1." _________ Therefore, when _________ the DMAREQi pin's input level is "L" with the DMAi enable bit = "1," a DMA transfer starts. When the DMAREQi pin's input level goes from "L" to "H," the right to use bus will be returned _________ to the CPU at completion of 1-unit transfer under execution at that time. When the DMAREQi pin's input level goes "L" again, the DMA transfer restarts at the next address. Once a DMAi transfer starts, any DMA request (including that of other channels) cannot be accepted, _________ even if the DMAREQi pin's input level is "H," until the transfer is terminated normally or forcibly. However, the BUS REQUEST signal is sampled basically at every completion of 1-unit transfer. (Refer to "Table 13.2.3.") When a DRAM refresh request or Hold request is generated at this time, the right to use bus is not returned to the CPU, and the request is accepted. When the transfer of an entire batch of data is complete, the DMAC relinquishes the right to the CPU. If the next DMA request is generated, the right is once returned to the CPU to sample the DMA request. 13-48 7721 Group User's Manual DMA CONTROLLER 13.4 Operation DMAREQ0 DMA0 request bit DMA0 enable bit DMAREQ1 DMA1 request bit DMA1 enable bit DRAM refresh request Right to use bus CPU DMA1 DRAM refresh DMA1 CPU DMA0 CPU Channel 1 Entire data transfer Channel 0 Entire data transfer This example applies on the following conditions: * Both of DMA0 and DMA1 request sources are external sources. * Channel priority level: Fixed (Channel 0 > Channel 1) Fig. 13.4.8 Transfer example in the burst transfer mode (edge sense) DMAREQ0 DMA0 request bit DMA0 enable bit DMAREQ1 DMA1 request bit DMA1 enable bit DRAM refresh request Right to use bus CPU DMA1 DRAM refresh CPU DMA1 CPU DMA0 CPU Channel 1 Entire data transfer Channel 0 Entire data transfer This example applies on the following conditions: * Channel priority level: Fixed (Channel 0 > Channel 1) Fig. 13.4.9 Transfer example in the burst transfer mode (level sense) 7721 Group User's Manual 13-49 DMA CONTROLLER 13.4 Operation [Precautions for burst transfer mode] 1. In the burst transfer mode (edge sense), the DMAi request bit is cleared to "0" when the transfer of an entire batch of data is complete or the transfer is forced into termination. Therefore, another DMA request of the same channel i is invalid if generated during DMAi transfer. 1-unit transfer Termination processing Transition of right to use bus (from DMAC to CPU) E DMAi request bit is set to "0." Fig. 13.4.10 Timing when clearing DMAi request bit to "0" in burst transfer mode 2. Because interrupt priority levels are determined while the CPU fetches an operation code, interrupt requests are not accepted during a DMA transfer. In the burst transfer mode (edge sense), therefore, interrupt requests cannot be accepted until the transfer of an entire batch of data is complete or the transfer is forced into termination. 13-50 7721 Group User's Manual DMA CONTROLLER 13.4 Operation 13.4.4 Cycle-steal transfer mode When the transfer mode select bit = "1" and the edge sense/level sense select bit = "0," this mode is selected. (Refer to "Figures 13.2.6 and 13.2.8.") In this mode, all of the DMA request sources are available. Figure 13.4.11 shows a transfer example in the cycle-steal transfer mode 1-transfer-unit data is transferred for each DMA request. The BUS REQUEST signal is sampled basically at every completion of 1-unit transfer. (Refer to "Table 13.2.3.") When a DRAM refresh request or Hold request is generated at this time, the right to use bus is not returned to the CPU, and the request is accepted. When several DMA requests are generated, the request of the channel which has the highest priority among them is accepted, and DMA transfer is performed without returning the right to use bus to the CPU. When any request is not generated, the CPU gains the right. DMAREQ0 DMA0 request bit DMA0 enable bit DMAREQ1 DMA1 request bit DMA1 enable bit DRAM refresh request Right to use bus CPU DMA1 DMA0 CPU DMA1 DMA1 DMA0 DRAM refresh DMA1 CPU This example applies on the following conditions: * Both of DMA0 and DMA1 request sources are external sources * Channel priority level: Fixed (Channel 0 > Channel 1) Fig. 13.4.11 Transfer example in cycle-steal transfer mode 7721 Group User's Manual 13-51 DMA CONTROLLER 13.4 Operation [Precautions for cycle-steal transfer mode] 1. When DMA transfers of the same channel are continuously performed In the cycle-steal transfer mode, the DMAi request bit is cleared to "0" in every 1-unit transfer. Also, it takes 1.5 cycles of from the generation of a DMA request until that of a BUS REQUEST (DMAC). Therefore, if another DMA request of the same channel i is generated during a DMAi transfer in the cyclesteal transfer mode, any one of the following three cases occurs depending on the timing of request generation: * The DMA request becomes invalid. * The DMA transfer continues without returning the right to use bus. * After returning the right to use bus to the CPU, the DMAC regains the right and restarts the DMA transfer. 1-unit transfer E (V) Bus request sampling DMAi request bit is cleared to "0" during this term. DMAi request is invalid even when DMAi request bit becomes "1." DMA transfers are continuously performed if DMAi request bit becomes "1" during this term (on condition that DMAi request bit becomes "1" at the timing satisfying tsu(DRQ - 1)). After returning the right to use bus to CPU, DMAC regains the right and restarts DMA transfer if DMAi request bit becomes "1" during this term. When a DMAi request is generated at the following timings, it is not in time to the next bus request sampling (V). Therefore, DMAC returns the right to use bus to the CPU. Then, DMAC regains the right and restarts the DMA transfer. * Except for the last 1-unit transfer, 1-bus cycle transfer is selected without Wait. * Except for the last 1-unit transfer, 1-bus cycle transfer is selected with Wait. In addition, a time of 0.5 cycle of is less than tsu(DRQ - 1). Fig. 13.4.12 Conditions for performing DMA transfers of the same channel continuously 13-52 7721 Group User's Manual DMA CONTROLLER 13.4 Operation 2. When a DMA transfer of another channel is subsequently performed In the cycle-steal transfer mode, it takes 1.5 cycles of from the generation of a DMA request until that of a BUS REQUEST (DMAC). Therefore, if a DMA request of another channel is generated during a DMAi transfer in the cycle-steal mode, either one of the following two cases occurs depending on its timing of request generation: * The DMAC performs the DMA transfer subsequently without returning the right to use bus. * After returning the right to use bus to the CPU once, the DMAC regains the right and performs the DMA transfer. 1-unit transfer E (V) Bus request sampling DMA transfer is subsequently performed if DMAi request bit of another channel becomes "1" during this term (on condition that DMAi request bit of another channel becomes "1" at the timing satisfying tsu(DRQ - 1)). After returning the right to use bus to CPU once, DMAC regains the right and restarts DMA transfer if DMAi request bit of another channel becomes "1" during this term. When a DMA request is generated at the following timing, it is not in time to the next bus request sampling (V). Therefore, DMAC returns the right to use bus to the CPU. Then, the DMAC regains the right and restarts DMA transfer. * Except for the last 1-unit transfer is selected without Wait. In addition, a time of 0.5 cycle of is less than tsu(DRQ - 1). Fig. 13.4.13 Conditions for performing DMA transfers of another channel subsequently 7721 Group User's Manual 13-53 DMA CONTROLLER 13.5 Single transfer mode 13.5 Single transfer mode This mode is used to transfer a block of data once. Table 13.5.1 lists the specifications of the single transfer mode, and Figure 13.5.1 shows the register structures of SARi, DARi, and TCRi in this mode. Table 13.5.1 Specifications of single transfer mode Item Transfer parameter memory Condition of normal termination Conditions of forced termination Not required. TCRi = 0 q Falling edge of the TC pin's input from "H" to "L" ___ ___ Performance specifications (when the TC pin validity bit ="1") q Write "0" to the DMAi enable bit Interrupt request generation timing At normal termination Functions of registers SARi latch: Indicates the transfer start address of data block at the transfer source. SARi: Indicates the address of the next transfer source. DARi latch: Indicates the transfer start address of data block at the transfer destination. DARi: Indicates the address of the next transfer destination. TCRi latch: Indicates the number of transfer bytes. TCRi: Indicates the number of remaining transfer bytes. ___ TC pin validity bit: Bit 1 at address 6816 13-54 7721 Group User's Manual DMA CONTROLLER 13.5 Single transfer mode b23 b16 b15 b8 b7 b0 Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0) Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1) Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2) Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the transfer start address of the source. These bits can be set to "00000016" to "FFFFFF16." [Read] The read value indicates the source address of data which is next transferred. Note: When writing to this register, write to all 24 bits. b23 b16 b15 b8 b7 b0 Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0) Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1) Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2) Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the transfer start address of the destination. These bits can be set to "00000016" to "FFFFFF16." [Read] The read value indicates the destination address of data which is next transferred. Note: When writing to this register, write to all 24 bits. b23 b16 b15 b8 b7 b0 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the byte number of the transfer data. These bits can be set to "00000116" to "FFFFFF16." [Read] The read value indicates remaining byte number of the transfer data. Note: When writing to this register, write to all 24 bits. Do not set this register to "00000016." Fig. 13.5.1 Register structures of SARi, DARi, and TCRi in single transfer mode 7721 Group User's Manual 13-55 DMA CONTROLLER 13.5 Single transfer mode 13.5.1 Setting of single transfer mode Figures 13.5.2 through 13.5.4 show an initial setting example for registers relevant to the single transfer mode. In addition, when timer A, timer B, UART, or the A-D converter is selected as a DMA request source, the setting for the peripheral is required. For details of the setting, refer to the chapter of each peripheral function. When a DMAi interrupt is used, the setting for enabling the interrupt is also required. For details, refer to "CHAPTER 7. INTERRUPTS." When external DMA source is selected When internal DMA source is selected Setting port P9 direction register b7 b0 Port P9 direction register (Address 1516) DMAREQ0 pin DMAREQ1 pin DMAREQ2 pin DMAREQ3 pin Clear the corresponding bit to "0." Setting interrupt priority level b7 b0 DMAi interrupt control register (i = 0 to 3) (Addresses 6C16 to 6F16) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Continue to "Figure 13.5.3" on next page. Fig. 13.5.2 Initial setting example for registers relevant to single transfer mode (1) 13-56 7721 Group User's Manual DMA CONTROLLER 13.5 Single transfer mode From preceding "Figure 13.5.2" Selection of transfer mode and each function b7 b0 0 DMA0 mode register L (Address 1FCC16) DMA1 mode register L (Address 1FDC16) DMA2 mode register L (Address 1FEC16) DMA3 mode register L (Address 1FFC16) Number-of-unit-transfer-bits select bit 0 : 16 bits 1 : 8 bits Transfer method select bit 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer Transfer mode select bit 0 : Burst transfer mode 1 : Cycle-steal transfer mode Transfer source address direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. Transfer destination address direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. b7 b0 DMA0 control register (Address 1FCE16) DMA1 control register (Address 1FDE16) DMA2 control register (Address 1FEE16) DMA3 control register (Address 1FFE16) DMA request source select bits 0 0 0 0 : Do not select. 0 0 0 1 : External source (DMAREQi) 0 0 1 0 : Software DMA source 0 0 1 1 : Timer A0 0 1 0 0 : Timer A1 0 1 0 1 : Timer A2 0 1 1 0 : Timer A3 0 1 1 1 : Timer A4 1 0 0 0 : Timer B0 1 0 0 1 : Timer B1 1 0 1 0 : Timer B2 1 0 1 1 : UART0 receive 1 1 0 0 : UART0 transmit 1 1 0 1 : UART1 receive 1 1 1 0 : UART1 transmit 1 1 1 1 : A-D conversion Edge sense/Level sense select bit (Note) 0 : Edge sense 1 : Level sense DMAACKi validity bit 0 : Invalid 1 : Valid Note: When an external source (DMAREQi) is selected or when the cycle-steal transfer mode is selected, set this bit to "0." b7 b0 00 00 DMA0 mode register H (Address 1FCD16) DMA1 mode register H (Address 1FDD16) DMA2 mode register H (Address 1FED16) DMA3 mode register H (Address 1FFD16) Transfer direction select bit (Used in 1-bus cycle transfer) 0 : From memory to I/O 1 : From I/O to memory I/O connection select bit (Valid in 1-bus cycle transfer) 0 : Data bus D0-D7 or D0-D15 1 : Data bus D8-D15 Transfer source wait bit (Valid in DMA transfer) 0 : Wait 1 : No wait Transfer destination wait bit (Valid in DMA transfer) 0 : Wait 1 : No wait Selection of single transfer mode Continue to "Figure 13.5.4" on next page. (b23) b7 (b16)(b15) b0 b7 (b8) b0 b7 b0 Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0) Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1) Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2) Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3) Set the transfer start address of transfer source. These bits can be set to "00000016" to "FFFFFF16." (b23) b7 (b16)(b15) b0 b7 (b8) b0 b7 b0 Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0) Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1) Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2) Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3) Set the transfer start address of destination. These bits can be set to "00000016" to "FFFFFF16." (b23) b7 (b16)(b15) b0 b7 (b8) b0 b7 b0 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3) Set the byte number of transfer data. These bits can be set to "00000116" to "FFFFFF16." Notes 1: When writing to these registers, write to all 24 bits. 2: Do not write "00000016" to TCRi. Note 3: When data is transferred from memory to I/O in 1-bus cycle transfer, it is unnecessary to set DARi. When data is transferred form I/O to memory in 1-bus cycle transfer, it is unnecessary to set SARi. Fig. 13.5.3 Initial setting example for registers relevant to single transfer mode (2) 7721 Group User's Manual 13-57 DMA CONTROLLER 13.5 Single transfer mode From preceding "Figure 13.5.3" Selection of priority level and TC pin, and setting DMAi request bit to "0" b7 b0 0000 DMAC control register L (Address 6816) Priority select bit 0 : Fixed 1 : Rotating TC pin validity bit 0 : Invalid (P103 pin functions as a programmable I/O port.) 1 : Valid (P103 pin functions as TC pin.) DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit 0 : No request b7 b0 DMAC control register H (Address 6916) Software DMAi request bit (Valid in software DMA source selected) Bit 0 : Channel 0 Bit 1 : Channel 1 Bit 2 : Channel 2 Bit 3 : Channel 3 DMA0 enable bit DMA1 enable bit DMA2 enable bit DMA3 enable bit 0 : Disabled 1 : Enabled When selecting external DMA source When selecting internal DMA source When selecting software DMA request When selecting internal DMA source except software Inputting DMA request signal to DMAREQi pin b7 b0 DMAC control register H (Address 6916) Software DMA0 request bit Software DMA1 request bit Software DMA2 request bit Software DMA3 request bit When writing "1," DMA request is generated. Interrupt request of each peripheral function occurs 0 : No request 1 : Requested DMA transfer starts Fig. 13.5.4 Initial setting example for registers relevant to single transfer mode (3) 13-58 7721 Group User's Manual DMA CONTROLLER 13.5 Single transfer mode 13.5.2 Operation in single transfer mode Figure 13.5.5 shows the operation flowchart of the single transfer mode, and Figure 13.5.6 shows a timing diagram of the single transfer mode (burst transfer mode). For the cycle-steal transfer mode, refer to the following: * All transfers except for the last 1-unit transfer: Figure 13.8.12 * Last 1-unit transfer: Figure 13.8.14 Also, refer to section "13.2.1 Bus access control circuit" for the bus request sampling during transfer. DMAi request bit 0 (Only in cycle-steal transfer mode) 1-unit transfer (Refer to section "13.4 Operation.") Transfer completion of 1 block ? Y N Burst*Edge Burst*Level*L Cycle-steal*Requested 1 DMAi request bit ? TC "L" output (Note) DMAi interrupt request bit 1 DMAi enable bit 0 Note: When TC pin validity bit is "1" 0 Burst*Level*H Cycle-Steal*No request DMAi request bit 0 (Only burst*edge) Burst*Edge Burst*Level*L Burst*Level*H Cycle-steal*Requested Cycle-steal*No request : In burst transfer mode (edge sense) : In burst transfer mode (level sense) with DMAREQi pin's input level = L : In burst transfer mode (level sense) with DMAREQi pin's input level = H : In cycle-steal transfer mode with any request of DMA0-3 : In cycle-steal transfer mode wit h no request of DMA0-3 Fig. 13.5.5 Operation flowchart of single transfer mode 7721 Group User's Manual 13-59 13-60 PCL sarL (sar+2)L (sar+6)M (sar+6)L sar M Data 0H dar M Data 0H (sar+2) M Data 1H (dar+2) M Data 1H (sar+4) M Data 2H (dar+4) M Data 2H ALE E R/W darL (dar+2)L (sar+4)L (dar+4)L (sar+6)L PCL PCH PG A0-A7 PC H 13.5 Single transfer mode A8/D8-A15/D15 PG sar H Data 0L dar H Data 0L (sar+2) H Data 1L (dar+2) H Data 1L (sar+4) H Data 2L (dar+4) H Data 2L DMA CONTROLLER A16/D0-A23/D7 Bus request sampling DMAACKi TC 1, 0 (DMAC) 1, 1 (CPU) Fig. 13.5.6 Timing diagram of single transfer mode (burst transfer mode) 7721 Group User's Manual Read cycle 1-unit transfer Transition of right to use bus Memory sar Data 0 H L Data 1 H L Data 2 H sar+5 L ST1, ST0 Write cycle Terminate processing Transition of right to use bus dar Transfer q This example applies on the following conditions: External data bus width : 16 bits Transfer unit : 16 bits Transfer method : 2-bus cycle transfer Transfer mode : Burst Transfer source address direction : Forward Transfer destination address direction : Forward Transfer source Wait : No Transfer destination Wait : No sar : The value which is set to SARi (even) dar : The value which is set to DARi (even) TCR set value :6 Right to use bus : CPU DMAC CPU dar+5 q The Bus request caused by DRAM refresh or Hold is sampled while the bus request sampling signal is "1," and is accepted. DMA CONTROLLER 13.6 Repeat transfer mode 13.6 Repeat transfer mode This mode is used to transfer one block of data repeatedly. Table 13.6.1 lists the specifications of the repeat transfer mode, and Figure 13.6.1 shows the register structures of SARi, DARi, and TCRi in this mode. Table 13.6.1 Specifications of repeat transfer mode Item Transfer parameter memory Condition of normal termination Conditions of forced termination Not required -- (No normal termination) q Falling edge of the TC pin's input from "H" to "L" ___ ___ Performance specifications (when the TC pin validity bit = "1") q Write "0" to the DMAi enable bit Interrupt request generation timing No request is generated. Functions of registers SARi latch: Indicates the transfer start address of data block at the transfer source. SARi: Indicates the address of the next transfer source. DARi latch: Indicates the transfer start address of data block at the transfer destination. DARi: Indicates the address of the next transfer destination. TCRi latch: Indicates the number of transfer bytes. TCRi: Indicates the number of remaining bytes being transferred. ___ TC pin validity bit: Bit 1 at address 6816 7721 Group User's Manual 13-61 DMA CONTROLLER 13.6 Repeat transfer mode b23 b16 b15 b8 b7 b0 Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0) Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1) Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2) Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the transfer start address of the source. These bits can be set to "00000016" to "FFFFFF16." [Read] The read value indicates the source address of data which is next transferred. Note: When writing to this register, write to all 24 bits. b23 b16 b15 b8 b7 b0 Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0) Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1) Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2) Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the transfer start address of the destination. These bits can be set to "00000016" to "FFFFFF16." [Read] The read value indicates the destination address of data which is next transferred. Note: When writing to this register, write to all 24 bits. b23 b16 b15 b8 b7 b0 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the byte number of transfer data. These bits can be set to "00000116" to "FFFFFF16." [Read] The read value indicates the remaining byte number of the block which is being transferred. Note: When writing to this register, write to all 24 bits. Do not write "00000016" to this register. Fig. 13.6.1 Register structures of SARi, DARi, and TCRi in repeat transfer mode 13-62 7721 Group User's Manual DMA CONTROLLER 13.6 Repeat transfer mode 13.6.1 Setting of repeat transfer mode Figures 13.6.2 through 13.6.4 show an initial setting example for registers relevant to the repeat transfer mode. In addition, when timer A, timer B, UART, or the A-D converter is selected as a DMA request source, the setting for the peripheral is required. For details of the setting, refer to the chapter of each peripheral function. In this mode, only the forced termination can terminate the DMA transfer. (Refer to section "13.3.5 (2) Forced termination." Therefore, in the burst transfer mode (edge sense selected), be sure to validate the ___ TC pin. When external DMA source is selected When internal DMA source is selected Setting port P9 direction register b7 b0 Port P9 direction register (Address 1516) DMAREQ0 pin DMAREQ1 pin DMAREQ2 pin DMAREQ3 pin Clear the corresponding bit to "0." Continue to "Figure 13.6.3" on next page. Fig. 13.6.2 Initial setting example for registers relevant to repeat transfer mode (1) 7721 Group User's Manual 13-63 DMA CONTROLLER 13.6 Repeat transfer mode From preceding "Figure 13.6.2" Selection of transfer mode and each function b7 b0 0 DMA0 mode register L (Address 1FCC16) DMA1 mode register L (Address 1FDC16) DMA2 mode register L (Address 1FEC16) DMA3 mode register L (Address 1FFC16) Number-of-unit-transfer-bits select bit 0 : 16 bits 1 : 8 bits Transfer method select bit 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer Transfer mode select bit 0 : Burst transfer mode 1 : Cycle-steal transfer mode Transfer source address direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. Transfer destination address direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. b7 b0 DMA0 control register (Address 1FCE16) DMA1 control register (Address 1FDE16) DMA2 control register (Address 1FEE16) DMA3 control register (Address 1FFE16) DMA request source select bits 1 0 0 0 : Timer B0 0 0 0 0 : Do not select. 0 0 0 1 : External source (DMAREQi) 1 0 0 1 : Timer B1 0 0 1 0 : Software DMA source 1 0 1 0 : Timer B2 0 0 1 1 : Timer A0 1 0 1 1 : UART0 receive 0 1 0 0 : Timer A1 1 1 0 0 : UART0 transmit 0 1 0 1 : Timer A2 1 1 0 1 : UART1 receive 0 1 1 0 : Timer A3 1 1 1 0 : UART1 transmit 0 1 1 1 : Timer A4 1 1 1 1 : A-D conversion Edge sense/Level sense select bit (Note) 0 : Edge sense 1 : Level sense DMAACKi validity bit 0 : Invalid 1 : Valid b7 b0 01 00 DMA0 mode register H (Address 1FCD16) DMA1 mode register H (Address 1FDD16) DMA2 mode register H (Address 1FED16) DMA3 mode register H (Address 1FFD16) Transfer direction select bit (Used in 1-bus cycle transfer) 0 : From memory to I/O 1 : From I/O to memory I/O connection select bit (Valid in 1-bus cycle transfer) 0 : Data bus D0-D7 or D0-D15 1 : Data bus D8-D15 Transfer source wait bit (Valid in DMA transfer) 0 : Wait 1 : No wait Transfer destination wait bit (Valid in DMA transfer) 0 : Wait 1 : No wait Selection of repeat transfer mode Note: When an external source (DMAREQi) is selected or when the cycle-steal transfer mode is selected, set this bit to "0." Continue to "Figure 13.6.4" on next page. (b23) b7 (b16)(b15) b0 b7 (b8) b0 b7 b0 Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0) Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1) Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2) Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3) Set the transfer start address of transfer source. These bits can be set to "00000016" to "FFFFFF16." (b23) b7 (b16)(b15) b0 b7 (b8) b0 b7 b0 Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0) Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1) Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2) Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3) Set the transfer start address of destination. These bits can be set to "00000016" to "FFFFFF16." (b23) b7 (b16)(b15) b0 b7 (b8) b0 b7 b0 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3) Set the byte number of transfer data. These bits can be set to "00000116" to "FFFFFF16." Notes 1: When writing to these registers, write to all 24 bits. 2: Do not write "00000016" to TCRi. Note 3: When data is transferred from memory to I/O in 1-bus cycle transfer, it is unnecessary to set DARi. When data is transferred form I/O to memory in 1-bus cycle transfer, it is unnecessary to set SARi. Fig. 13.6.3 Initial setting example for registers relevant to repeat transfer mode (2) 13-64 7721 Group User's Manual DMA CONTROLLER 13.6 Repeat transfer mode From preceding "Figure 13.6.3" Selection of priority level and TC pin, and setting DMAi request bit to "0" b7 b0 0000 DMAC control register L (Address 6816) Priority select bit 0 : Fixed 1 : Rotating TC pin validity bit 0 : Invalid (P103 pin functions as a programmable I/O port.) 1 : Valid (P103 pin functions as TC pin.) DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit 0 : No request Note: When the burst transfer mode (edge sense) is selected, set bit 1 to "1." b7 b0 DMAC control register H (Address 6916) Software DMAi request bit (Valid in software DMA source selected) Bit 0 : Channel 0 Bit 1 : Channel 1 Bit 2 : Channel 2 Bit 3 : Channel 3 DMA0 enable bit DMA1 enable bit DMA2 enable bit DMA3 enable bit 0 : Disabled 1 : Enabled When selecting external DMA source When selecting internal DMA source When selecting software DMA request When selecting internal DMA source except software Inputting DMA request signal to DMAREQi pin b7 b0 DMAC control register H (Address 6916) Software DMA0 request bit Software DMA1 request bit Software DMA2 request bit Software DMA3 request bit When writing "1," DMA request is generated. Interrupt request of each peripheral function occurs 0 : No request 1 : Requested DMA transfer starts Fig. 13.6.4 Initial setting example for registers relevant to repeat transfer mode (3) 7721 Group User's Manual 13-65 DMA CONTROLLER 13.6 Repeat transfer mode 13.6.2 Operation in repeat transfer mode Figure 13.6.5 shows the operation flowchart of the repeat transfer mode, and Figure 13.6.6 shows a timing diagram of the repeat transfer mode (burst transfer mode). For the cycle-steal transfer mode, refer to the following: * All transfers except for the last 1-unit transfer: Figure 13.8.12 * Last 1-unit transfer: Figure 13.8.13 Also, refer to section "13.2.1 Bus access control circuit" for the bus request sampling during transfer. DMAi request bit 0 (Only in cycle-steal transfer mode) 1-unit transfer (Refer to section "13.4 Operation.") 1 Burst*Edge Burst*Level*L Cycle-steal*Requested DMAi request bit ? 0 Burst*Level*H Cycle-steal*No request Burst*Edge Burst*Level*L Burst*Level*H Cycle-steal*Requested Cycle-steal*No request : In burst transfer mode (edge sense) : In burst transfer mode (level sense) with DMAREQi pin's input level = L : In burst transfer mode (level sense) with DMAREQi pin's input level = H : In cycle-steal transfer mode with any request of DMA0-3 : In cycle-steal transfer mode with no request of DMA0-3 Fig. 13.6.5 Operation flowchart of repeat transfer mode 13-66 7721 Group User's Manual ALE E R/W A0-A7 dar L (sar+6) L (sar+6) M (sar+6) L sarH sarM Data0H PCL sar L sar L dar M dar H Data0L (sar+4) L (sar+4)M Data2H (dar+4)M (dar+4) L Data2H dar L A8/D8-A15/D15 Data0H Data0H PCH darM darH Data0L (sar+4)H Data2L (dar+4)H sar M Data2L A16/D0-A23/D7 PG Data0L sar H Bus request sampling DMAACKi TC ST1, ST0 1, 0 (DMAC) H Fig. 13.6.6 Timing diagram of repeat transfer mode (burst transfer mode) 1-unit transfer Transfer of entire batch of data (first) Transition of right to use bus Memory sar Data 0 H L Data 1 H L Data 2 H sar+5 dar+5 L dar 7721 Group User's Manual q This example applies on the following conditions: External data bus width : 16 bits Transfer unit : 16 bits Transfer method : 2-bus cycle transfer Transfer mode : Burst Transfer source address direction : Forward Transfer destination address direction : Forward Transfer source Wait : No Transfer destination Wait : No sar : The value which is set to SARi (even) dar : The value which is set to DARi (even) TCR set value :6 Right to use bus : CPU DMAC q The Bus request caused by DRAM refresh or Hold is sampled while the bus request sampling signal is "1," and is accepted. Transfer of entire batch of data (second) DMA CONTROLLER Transfer 13.6 Repeat transfer mode 13-67 DMA CONTROLLER 13.7 Array chain transfer mode 13.7 Array chain transfer mode This mode is used to transfer several blocks of data. According to the information of each block stored in memory area (Note), several blocks of data are transferred. All of the transfer parameters must be located in series. Table 13.7.1 lists the specifications of the array chain transfer mode, and Figure 13.7.1 shows the register structures of SARi, DARi, and TCRi in this mode. Note: Each of the following information is called "transfer parameter": transfer start addresses of transfer source and destination, and transfer data's byte number. Table 13.7.1 Specifications of array chain transfer mode Item Performance specifications Transfer parameter memory Required. q In 2-bus cycle transfer: 12 bytes per one block (transfer source's transfer start address, transfer destination's transfer start address, transfer data's byte number) q In 1-bus cycle transfer: 8 bytes per one block (from memory to I/O: transfer source's transfer start address, transfer data's byte number) (from I/O to memory: transfer destination's transfer start address, transfer data's byte number) Condition of normal termination Conditions of forced termination TCRi latch = 0 and TCRi = 0 q Falling edge of the TC pin's input from "H" to "L" ___ ___ (when the TC pin validity bit = "1") q Write "0" to the DMAi enable bit Interrupt request generation timing At normal termination SARi latch: Indicates the transfer parameter memory's start address of Functions of registers the next block. SARi: Indicates the address of the next transfer source. DARi latch: Not used. DARi: Indicates the address of the next transfer destination. TCRi latch: Indicates the number of remaining transfer blocks. TCRi: Indicates the number of remaining transfer bytes. ___ TC pin validity bit: Bit 1 at address 6816 13-68 7721 Group User's Manual DMA CONTROLLER 13.7 Array chain transfer mode b23 b16 b15 b8 b7 b0 Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0) Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1) Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2) Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the start address of transfer parameter memory. These bits can be set to "00000016" to "FFFFFF16." [Read] * After a value is written to this register and until transfer starts, the read value indicates the written value (the start address of the transfer parameter memory). * After transfer starts, the read value indicates the source address of data which is next transferred. Note: When writing to this register, write to all 24 bits. b23 b16 b15 b8 b7 b0 Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0) Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1) Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2) Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3) Bit Functions At reset Undefined RW RW 23 to 0 Need not to be set. [Read] After transfer starts, the read value indicates the destination address of data which is next transferred. b23 b16 b15 b8 b7 b0 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the number of transfer blocks. These bits can be set to "00000116" to "FFFFFF16." [Read] * After a value is written to this register and until transfer starts, the read value indicates the written value (the transfer block number) . * After transfer starts, the read value indicates the remaining byte number of the block which is being transferred. Note: When writing to this register, write to all 24 bits. Do not write "00000016" to this register. Fig. 13.7.1 Register structures of SARi, DARi, and TCRi in array chain transfer mode 7721 Group User's Manual 13-69 DMA CONTROLLER 13.7 Array chain transfer mode 13.7.1 Transfer parameter memory in array chain transfer mode The transfer parameters required for each transfer method are described below. These parameters must be located in series starting at an even addresses. Figure 13.7.2 shows a transfer parameter memory map in the array chain transfer mode. (1) In 2-bus cycle transfer All of the following transfer parameters are required for each block of data; that is, a transfer parameter memory consumes 12 bytes for each block. * Transfer source's transfer start address (24 bits) + Dummy data (8 bits) * Transfer destination's transfer start address (24 bits) + Dummy data (8 bits) * Transfer data's byte number (24 bits) + Dummy data (8 bits) (2) In 1-bus cycle transfer from memory to I/O All of the following transfer parameters are required for each block of data; that is, a transfer parameter memory consumes 8 bytes for each block. * Transfer source's transfer start address (24 bits) + Dummy data (8 bits) * Transfer data's byte number (24 bits) + Dummy data (8 bits) (3) In 1-bus cycle transfer from I/O to memory All of the following transfer parameters are required for each block of data; that is, a transfer parameter memory consumes 8 bytes for each block. * Transfer destination's transfer start address (24 bits) + Dummy data (8 bits) * Transfer data's byte number (24 bits) + Dummy data (8 bits) 13-70 7721 Group User's Manual DMA CONTROLLER 13.7 Array chain transfer mode (1) 2-bus cycle transfer L Even address source's transfer M start address H Transfer Dummy data 4 bytes 4 bytes 4 bytes Transfer source's transfer start address 1 Transfer destination's transfer start address 1 Transfer data's byte number 1 Transfer source's transfer start address 2 Transfer destination's transfer start address 2 Transfer parameters for 1 block Transfer data's byte number 2 Transfer source's transfer start address 3 Transfer destination's transfer start address 3 L Even address destination's transfer M H start address Transfer Dummy data Transfer data's byte number 3 Transfer source's transfer start address 4 Transfer destination's transfer start address 4 L Transfer data's M byte number Even address H Transfer data's byte number 4 Dummy data V The above applies when 4-block transfer is performed. (2) 1-bus cycle transfer 4 bytes 4 bytes Transfer source's transfer start address 1 Transfer start address Dummy data L H L Even address Transfer parameters for 1 block Transfer data's byte number 1 Transfer source's transfer start address 2 source's transfer M Transfer data's byte number 2 Transfer source's transfer start address 3 Even address Transfer data's byte number 3 Transfer source's transfer start address 4 Transfer data's M byte number H Dummy data Transfer data's byte number 4 V The above applies on the following conditions: *When data is transferred from memory to I/O (When transferring from I/O to memory, replace all the above mentioned "Transfer source's transfer start address" with "Transfer destination's transfer start address.") *4-block transfer Fig. 13.7.2 Transfer parameter memory map in array chain transfer mode 7721 Group User's Manual 13-71 DMA CONTROLLER 13.7 Array chain transfer mode 13.7.2 Setting of array chain transfer mode Figures 13.7.3 through 13.7.5 show an initial setting example for registers relevant to the array chain transfer mode. In addition, when timer A, timer B, UART, or the A-D converter is selected as a DMA request source, the setting for the peripheral is required. For details of the setting, refer to the chapter of each peripheral function. When a DMAi interrupt is used, the setting for enabling the interrupt is also required. For details, refer to "CHAPTER 7. INTERRUPTS." When external DMA source is selected When internal DMA source is selected Setting port P9 direction register b7 b0 Port P9 direction register (Address 1516) DMAREQ0 pin DMAREQ1 pin DMAREQ2 pin DMAREQ3 pin Clear the corresponding bit to "0." Setting interrupt priority level b7 b0 DMAi interrupt control register (i = 0 to 3) (Addresses 6C16 to 6F16) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Continue to "Figure 13.7.4" on next page. Fig. 13.7.3 Initial setting example for registers relevant to array chain transfer mode (1) 13-72 7721 Group User's Manual DMA CONTROLLER 13.7 Array chain transfer mode From preceding "Figure 13.7.3" Selection of transfer mode and each function b7 b0 0 DMA0 mode register L (Address 1FCC16) DMA1 mode register L (Address 1FDC16) DMA2 mode register L (Address 1FEC16) DMA3 mode register L (Address 1FFC16) Number-of-unit-transfer-bits select bit 0 : 16 bits 1 : 8 bits Transfer method select bit 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer Transfer mode select bit 0 : Burst transfer mode 1 : Cycle-steal transfer mode Transfer source address direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. Transfer destination address direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. b7 b0 DMA0 control register (Address 1FCE16) DMA1 control register (Address 1FDE16) DMA2 control register (Address 1FEE16) DMA3 control register (Address 1FFE16) DMA request source select bits 0 0 0 0 : Do not select. 0 0 0 1 : External source (DMAREQi) 0 0 1 0 : Software DMA source 0 0 1 1 : Timer A0 0 1 0 0 : Timer A1 0 1 0 1 : Timer A2 0 1 1 0 : Timer A3 0 1 1 1 : Timer A4 1 0 0 0 : Timer B0 1 0 0 1 : Timer B1 1 0 1 0 : Timer B2 1 0 1 1 : UART0 receive 1 1 0 0 : UART0 transmit 1 1 0 1 : UART1 receive 1 1 1 0 : UART1 transmit 1 1 1 1 : A-D conversion Edge sense/Level sense select bit (Note) 0 : Edge sense 1 : Level sense DMAACKi validity bit 0 : Invalid 1 : Valid Note: When an external source (DMAREQi) is selected or when the cycle-steal transfer mode is selected, set this bit to "0." b7 b0 10 00 DMA0 mode register H (Address 1FCD16) DMA1 mode register H (Address 1FDD16) DMA2 mode register H (Address 1FED16) DMA3 mode register H (Address 1FFD16) Transfer direction select bit (Used in 1-bus cycle transfer) 0 : From memory to I/O 1 : From I/O to memory I/O connection select bit (Valid in 1-bus cycle transfer) 0 : Data bus D0-D7 or D0-D15 1 : Data bus D8-D15 Transfer source wait bit (Valid in DMA transfer) 0 : Wait 1 : No wait Transfer destination wait bit (Valid in DMA transfer) 0 : Wait 1 : No wait Selection of array chain transfer mode Continue to "Figure 13.7.5" on next page. (b23) b7 (b16)(b15) b0 b7 (b8) b0 b7 b0 Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0) Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1) Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2) Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3) Set the start address of transfer parameter memory. These bits can be set to "00000016" to "FFFFFF16." (b23) b7 (b16)(b15) b0 b7 (b8) b0 b7 b0 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3) Set the number of transfer blocks. These bits can be set to "00000116" to "FFFFFF16." Notes 1: When writing to these registers, write to all 24 bits. 2: Do not write "00000016" to TCRi. Fig. 13.7.4 Initial setting example for registers relevant to array chain transfer mode (2) 7721 Group User's Manual 13-73 DMA CONTROLLER 13.7 Array chain transfer mode From preceding "Figure 13.7.4" Selection of priority level and TC pin, and setting DMAi request bit to "0" b7 b0 0000 DMAC control register L (Address 6816) Priority select bit 0 : Fixed 1 : Rotating TC pin validity bit 0 : Invalid (P103 pin functions as a programmable I/O port.) 1 : Valid (P103 pin functions as TC pin.) DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit 0 : No request b7 b0 DMAC control register H (Address 6916) Software DMAi request bit (Valid in software DMA source selected) Bit 0 : Channel 0 Bit 1 : Channel 1 Bit 2 : Channel 2 Bit 3 : Channel 3 DMA0 enable bit DMA1 enable bit DMA2 enable bit DMA3 enable bit 0 : Disabled 1 : Enabled When selecting external DMA source When selecting internal DMA source When selecting software DMA request When selecting internal DMA source except software Inputting DMA request signal to DMAREQi pin b7 b0 DMAC control register H (Address 6916) Software DMA0 request bit Software DMA1 request bit Software DMA2 request bit Software DMA3 request bit When writing "1," DMA request is generated. Interrupt request of each peripheral function occurs 0 : No request 1 : Requested DMA transfer starts Fig. 13.7.5 Initial setting example for registers relevant to array chain transfer mode (3) 13-74 7721 Group User's Manual DMA CONTROLLER 13.7 Array chain transfer mode 13.7.3 Operation in array chain transfer mode Figure 13.7.6 shows the operation flowchart of the array chain transfer mode, and Figures 13.7.7 and 13.7.8 show timing diagrams of the array chain transfer mode (burst transfer mode). For the cycle-steal transfer mode, refer to the following: * Transfer of transfer parameters in an array state: Figures 13.8.10 and 13.8.11 * All transfers except in an array state and except the last 1-unit transfer of each block: Figure 13.8.12 * Last 1-unit transfer of each block except the last block: Figure 13.8.13 * Last 1-unit transfer of the last block: Figure 13.8.14 The processing performed in the array chain transfer mode consists of an array state and a transfer state. (1) Array state In an array state, transfer parameters are read from the transfer parameter memory in a unit of 2 bytes and transferred to registers SARi, DARi, and TCRi and their latches. As shown in Figure 13.7.2, a transfer parameter consists of 4 bytes (24 bits of data + 8 bits of dummy data). One bus cycle always consumes 3 cycles of . _________ During an array state, the DMAACKi pin outputs "H" level. For the bus request sampling in an array state, refer to section "13.2.1 Bus access control circuit." (2) Transfer state Data is transferred in a transfer state. For the bus request sampling in a transfer state, refer to section "13.2.1 Bus access control circuit." 7721 Group User's Manual 13-75 DMA CONTROLLER 13.7 Array chain transfer mode First of 1 block ? First On and after second SARi Transfer parameter (Note) (Transfer source's transfer start address) DARi Transfer parameter (Note) (Transfer destination's transfer start address) TCRi Transfer parameter (Byte number of transfer data) TCRi latch TCRi latch - 1 DMAi request bit 0 (Only in cycle-steal transfer mode) 1-unit transfer (Refer to section "13.4 Operation.") Burst*Edge Burst*Level*L Cycle-steal*Requested N Transfer completion of 1 block ? Burst*Edge Burst*Level*L Cycle-steal*Requested N Y DMAi request bit ? 1 Transfer completion of all blocks ? TCRi latch = 0 ? Y. Completion 0 Burst*Level*H Cycle-steal*No request 1 DMAi request bit ? 0 Burst*Level*H Cycle-steal*No request TC "L" output (Note) DMAi interrupt request bit 1 DMAi enable bit 0 Note: When TC pin validity bit is "1" DMAi request bit 0 (Only in burst transfer mode (edge sense)) Burst*Edge : In burst transfer mode (edge sense) Burst*Level*L : In burst transfer mode (level sense) with DMAREQi pin = L Burst*Level*H : In burst transfer mode (level sense) with DMAREQi pin = H Cycle-steal*Requested : In cycle-steal transfer mode with any request of DMA0-3 Cycle-steal*No request : In cycle-steal transfer mode with no request of DMA0-3 SARi latch indicates the start address of the transfer parameter memory of the next block. TCRi latch indicates the number of remaining transfer blocks. Note: The above figure applies when 2-bus cycle transfer is performed. When data is transferred from memory to I/O in 1-bus cycle transfer, there is no "DARi Transfer parameter." When data is transferred from I/O to memory in 1-bus cycle transfer, there is no "SARi Transfer parameter." Fig. 13.7.6 Operation flowchart of array chain transfer mode 13-76 7721 Group User's Manual Continue to "Figure 13.7.8" on next page. 1 ALE E H R/W tpL (tp+12)L A0-A7 sa1M (tp+2)M (tp+4)M (tp+6)M (tp+8)M (tp+10)M Dummy data PCL (tp+2)L Dummy data (tp+4)L da1M Dummy data (tp+6)L (tp+8)L mM mL (tp+10)H (tp+12)M (tp+10)L sa1L da1L sa1M DataH da1M DataH A8/D8-A15/D15 sa1L (tp+2)H (tp+4)H PCH sa1H da1L (tp+6)H tpM da1 H (tp+8)H A16/D0-A23/D7 PG tpH mH (tp+12)H sa1H DataL da1H DataL Bus request sampling H DMAACKi H TC 1, 0 (DMAC) 1-unit transfer Transfer of transfer parameters Array state Transfer of data Transfer state Fig. 13.7.7 Timing diagram of array chain transfer mode (burst transfer mode) (1) 7721 Group User's Manual Memory tp tp+4 tp+8 tp+12 tp+16 tp+20 ST1, ST0 Transfer of 1 transfer parameter Transition of right to use bus Memory sa1 da1 m sa2 da2 n Second block's transfer parameters First block's transfer parameters Memory sa1 First block transfer sa1+m-1 sa1+m sa2 Second block transfer sa2+n-1 sa2+n da2+n-1 da2+n da1+m-1 da1+m da2 da1 qThis example applies on the following conditions: External data bus width : 16 bits Transfer unit : 16 bits Transfer method : 2-bus cycle transfer Transfer mode : Burst Transfer source address direction : Forward Transfer destination address direction : Forward Transfer source Wait : No Transfer destination Wait : No sa1, sa2, da1, da2 : Transfer parameters (even) tp : Start address of first block's transfer parameter memory TCR set value :6 Right to use bus : CPU DMAC CPU DMA CONTROLLER qThe Bus request caused by DRAM refresh or Hold is sampled while the bus request sampling signal is "1," and is accepted. 13.7 Array chain transfer mode 13-77 13-78 From proceeding " Figure 13.7.7" 1 ALE E R/W A0-A7 DataH DataL (sa1+m)H (tp+12)H (tp+24)H 13.7 Array chain transfer mode DMA CONTROLLER (da1+m-2)L (sa1+m)L (tp+22)L (tp+24) L (tp+12)L sa2L sa2M DataH (tp+12)M (tp+24)M (da2+n-2)L DataH (sa2+n)L (sa2+n)M PCL PCH A8/D8-A15/D15 sa2L nH sa2H (sa1+m)M Dummy data sa2M A16/D0-A23/D7 DataL DataL (sa2+n)H PG Bus request sampling DMAACKi TC ST1, ST0 1, 0 (DMAC) 1, 1 (CPU) Fig. 13.7.8 Timing diagram of array chain transfer mode (burst transfer mode) (2) 7721 Group User's Manual Transfer of data Transfer state Array state Terminate processing Transfer state Transition of right to use bus DMA CONTROLLER 13.7 Array chain transfer mode [Precautions for array chain transfer mode] If the following two conditions are satisfied when the transfer unit is 16 bits and the address direction of transfer source or destination is fixed, the array chain transfer mode can be used: * The external data bus width = 16 bits or the internal memory is used. * The transfer start address on the address-direction-fixed side is an even address. 7721 Group User's Manual 13-79 DMA CONTROLLER 13.8 Link array chain transfer mode 13.8 Link array chain transfer mode This mode is used to transfer several blocks of data. According to the information of each block stored in memory area (Note), several blocks of data are transferred. Transfer parameters can be located in separate memory locations, in a unit of one block's parameters. Table 13.8.1 lists the specifications of the link array chain transfer mode, and Figure 13.8.1 shows the register structures of SARi, DARi, and TCRi in this mode. Note: Each of the following information is called "transfer parameter": transfer start addresses of transfer source and destination, and transfer data's byte number. Table 13.8.1 Specifications of link array chain transfer mode Item Transfer parameter memory Required. q In 2-bus cycle transfer: 16 bytes per one block (transfer source's transfer start address, transfer destination's transfer start address, transfer data's byte number, next transfer parameter memory's start address) q In 1-bus cycle transfer: 12 bytes per one block (from memory to I/O: transfer source's transfer start address, transfer data's byte number, next transfer parameter memory's start address) (from I/O to memory: transfer destination's transfer start address, transfer data's byte number, next transfer parameter memory's start address) Condition of normal termination Conditions of forced termination SARi latch = 0 and TCRi = 0 qFalling edge of TC pin's input from "H" to "L" ___ ___ Performance specifications (when the TC pin validity bit = "1") qWrite "0" to the DMAi enable bit Interrupt request generation timing At normal termination SARi latch: Indicates the transfer parameter memory's start address of Functions of registers the next block. SARi: Indicates the address of the next transfer source. DARi latch: Not used. DARi: Indicates the address of the next transfer destination. TCRi latch: Not used. ___ TCRi: Indicates the number of remaining bytes being transferred. TC pin validity bit: Bit 1 at address 6816 13-80 7721 Group User's Manual DMA CONTROLLER 13.8 Link array chain transfer mode b23 b16 b15 b8 b7 b0 Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0) Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1) Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2) Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the start address of transfer parameter memory of block which is first transferred. These bits can be set to "00000016" to "FFFFFF16." [Read] * After a value is written to this register and until transfer starts, the read value indicates the written value (the start address of the transfer parameter memory of block which is first transferred). * After transfer starts, the read value indicates the source address of data which is next transferred. Note: When writing to this register, write to all 24 bits. b23 b16 b15 b8 b7 b0 Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0) Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1) Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2) Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3) Bit Functions At reset Undefined RW RW 23 to 0 Need not to be set. [Read] After transfer starts, the read value indicates the destination address of data which is next transferred. b23 b16 b15 b8 b7 b0 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the dummy data. These bits can be set to "00000116" to "FFFFFF16." [Read] * After a value is written to this register and until transfer starts, the read value indicates the written value (dummy data). * After transfer starts, the read value indicates the remaining byte number of the block which is being transferred. Note: When writing to this register, write to all 24 bits. Do not write "00000016" to this register. Fig. 13.8.1 Register structures of SARi, DARi, and TCRi in link array chain transfer mode 7721 Group User`s Manual 13-81 DMA CONTROLLER 13.8 Link array chain transfer mode 13.8.1 Transfer parameter memory in link array chain transfer mode The transfer parameters required for each transfer method are described below. These parameters can be located in separate memory locations, in a unit of one block's parameters. However, these parameters must be located starting at an even address. Figure 13.8.2 shows a transfer parameter memory map in the link array chain transfer mode. (1) In 2-bus cycle transfer All of the following transfer parameters are required for each block of data; that is, a transfer parameter memory consumes 16 bytes for each block. * Transfer source's transfer start address (24 bits) + Dummy data (8 bits) * Transfer destination's transfer start address (24 bits) + Dummy data (8 bits) * Transfer data's byte number (24 bits) + Dummy data (8 bits) * Start address of next transfer parameter memory (24 bits) (Note) + Dummy data (8 bits) (2) In 1-bus cycle transfer from memory to I/O All of the following transfer parameters are required for each block of data; that is, a transfer parameter memory consumes 12 bytes for each block. * Transfer source's transfer start address (24 bits) + Dummy data (8 bits) * Transfer data's byte number (24 bits) + Dummy data (8 bits) * Start address of next transfer parameter memory (24 bits) (Note) + Dummy data (8 bits) (3) In 1-bus cycle transfer from I/O to memory All of the following transfer parameters are required for each block of data; that is, a transfer parameter memory consumes 12 bytes for each block. * Transfer destination's transfer start address (24 bits) + Dummy data (8 bits) * Transfer data's byte number (24 bits) + Dummy data (8 bits) * Start address of next transfer parameter memory (24 bits) (Note) + Dummy data (8 bits) Note: For the last block of data, write "00000016" as the start address of the next transfer parameter memory. 13-82 7721 Group User's Manual DMA CONTROLLER 13.8 Link array chain transfer mode (1) 2-bus cycle transfer Transfer source's transfer start address 1 Transfer parameter address 1 Transfer destination's transfer start address 1 Transfer data's byte number 1 Next transfer parameter memory's start address 2 4 bytes Transfer source's L Even address M transfer start H address Dummy data L Even address Transfer destination's transfer M H start address Dummy data L Even address Transfer data's M byte number H Dummy data L Even address Next transfer parameter memory's M start address H Dummy data Transfer parameters for 1 block Transfer source's transfer start address 4 Transfer parameter address 4 (last block) Transfer destination's transfer start address 4 Transfer data's byte number 4 "00000016" Transfer source's transfer start address 3 Transfer parameter address 3 Transfer destination's transfer start address 3 Transfer data's byte number 3 Next transfer parameter memory's start address 4 Transfer source's transfer start address 2 Transfer parameter address 2 Transfer destination's transfer start address 2 Transfer data's byte number 2 Next transfer parameter memory's start address 3 V The above figure applies when 4-block transfer is performed. (2) 1-bus cycle transfer Transfer source's transfer start address 1 Transfer parameter address 1 Transfer data's byte number 1 Next transfer parameter memory's start address 2 4 bytes Transfer source's transfer start address 3 Transfer parameter address 3 Transfer data's byte number 3 Next transfer parameter memory's start address 4 Transfer source's L M transfer start H address Dummy data L Transfer data's M byte number H Dummy data L Next transfer parameter memory's M start address H Dummy data Even address Transfer parameters for 1 block Even address Even address Transfer source's transfer start address 2 Transfer parameter address 2 Transfer data's byte number 2 Next transfer parameter memory's start address 3 Transfer source's transfer start address 4 Transfer parameter address 4 (last block) Transfer data's byte number 4 "00000016" V The above applies on the following conditions: *When data is transferred from memory to I/O (When transferring from I/O to memory, replace all the above mentioned "Transfer source's transfer start address" with "Transfer destination's transfer start address." *4-block transfer Fig. 13.8.2 Transfer parameter memory map in link array chain transfer mode 7721 Group User`s Manual 13-83 DMA CONTROLLER 13.8 Link array chain transfer mode 13.8.2 Setting of link array chain transfer mode Figures 13.8.3 through 13.8.5 show an initial setting example for registers relevant to the link array chain transfer mode. In addition, when timer A, timer B, UART, or the A-D converter is selected as a DMA request source, the setting for the peripheral is required. For details of the setting, refer to the chapter of each peripheral function. When a DMAi interrupt is used, the setting for enabling the interrupt is also required. For details, refer to "CHAPTER 7. INTERRUPTS." When external DMA source is selected When internal DMA source is selected Setting port P9 direction register b7 b0 Port P9 direction register (Address 1516) DMAREQ0 pin DMAREQ1 pin DMAREQ2 pin DMAREQ3 pin Clear the corresponding bit to "0." Setting interrupt priority level b7 b0 DMAi interrupt control register (i = 0 to 3) (Addresses 6C16 to 6F16) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Continue to "Figure 13.8.4" on next page. Fig. 13.8.3 Initial setting example for registers relevant to link array chain transfer mode (1) 13-84 7721 Group User's Manual DMA CONTROLLER 13.8 Link array chain transfer mode From preceding "Figure 13.8.3" Selection of transfer mode and each function b7 b0 0 DMA0 mode register L (Address 1FCC16) DMA1 mode register L (Address 1FDC16) DMA2 mode register L (Address 1FEC16) DMA3 mode register L (Address 1FFC16) Number-of-unit-transfer-bits select bit 0 : 16 bits 1 : 8 bits Transfer method select bit 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer Transfer mode select bit 0 : Burst transfer mode 1 : Cycle-steal transfer mode Transfer source address direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. Transfer destination address direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. b7 b0 DMA0 control register (Address 1FCE16) DMA1 control register (Address 1FDE16) DMA2 control register (Address 1FEE16) DMA3 control register (Address 1FFE16) DMA request source select bits 0 0 0 0 : Do not select. 0 0 0 1 : External source (DMAREQi) 0 0 1 0 : Software DMA source 0 0 1 1 : Timer A0 0 1 0 0 : Timer A1 0 1 0 1 : Timer A2 0 1 1 0 : Timer A3 0 1 1 1 : Timer A4 1 0 0 0 : Timer B0 1 0 0 1 : Timer B1 1 0 1 0 : Timer B2 1 0 1 1 : UART0 receive 1 1 0 0 : UART0 transmit 1 1 0 1 : UART1 receive 1 1 1 0 : UART1 transmit 1 1 1 1 : A-D conversion Edge sense/Level sense select bit (Note) 0 : Edge sense 1 : Level sense DMAACKi validity bit 0 : Invalid 1 : Valid Note: When an external source (DMAREQi) is selected or when the cycle steal transfer mode is selected, set this bit to "0." b7 b0 11 00 DMA0 mode register H (Address 1FCD16) DMA1 mode register H (Address 1FDD16) DMA2 mode register H (Address 1FED16) DMA3 mode register H (Address 1FFD16) Transfer direction select bit (Used in 1-bus cycle transfer) 0 : From memory to I/O 1 : From I/O to memory I/O connection select bit (Valid in 1-bus cycle transfer) 0 : Data bus D0-D7 or D0-D15 1 : Data bus D8-D15 Transfer source wait bit (Valid in DMA transfer) 0 : Wait 1 : No wait Transfer destination wait bit (Valid in DMA transfer) 0 : Wait 1 : No wait Selection of link array chain transfer mode Continue to "Figure 13.8.5" on next page. (b23) b7 (b16)(b15) b0 b7 (b8) b0 b7 b0 Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0) Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1) Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2) Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3) Set the start address of transfer parameter memory of block which is first transferred. These bits can be set to "00000016" to "FFFFFF16." (b23) b7 (b16)(b15) b0 b7 (b8) b0 b7 b0 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3) Set the dummy data. These bits can be set to "00000116" to "FFFFFF16." Notes 1: When writing to these registers, write to all 24 bits. 2: Do not write "00000016" to TCRi. Fig. 13.8.4 Initial setting example for registers relevant to link array chain transfer mode (2) 7721 Group User`s Manual 13-85 DMA CONTROLLER 13.8 Link array chain transfer mode From preceding "Figure 13.8.4" Selection of priority level and TC pin, and setting DMAi request bit to "0" b7 b0 0000 DMAC control register L (Address 6816) Priority select bit 0 : Fixed 1 : Rotating TC pin validity bit 0 : Invalid (P103 pin functions as a programmable I/O port.) 1 : Valid (P103 pin functions as TC pin.) DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit 0 : No request b7 b0 DMAC control register H (Address 6916) Software DMAi request bit (Valid in software DMA source selected) Bit 0 : Channel 0 Bit 1 : Channel 1 Bit 2 : Channel 2 Bit 3 : Channel 3 DMA0 enable bit DMA1 enable bit DMA2 enable bit DMA3 enable bit 0 : Disabled 1 : Enabled When selecting external DMA source When selecting internal DMA source When selecting software DMA request When selecting internal DMA source except software Inputting DMA request signal to DMAREQi pin b7 b0 DMAC control register H (Address 6916) Software DMA0 request bit Software DMA1 request bit Software DMA2 request bit Software DMA3 request bit When writing "1," DMA request is generated. Interrupt request of each peripheral function occurs 0 : No request 1 : Requested DMA transfer starts Fig. 13.8.5 Initial setting example for registers relevant to link array chain transfer mode (3) 13-86 7721 Group User's Manual DMA CONTROLLER 13.8 Link array chain transfer mode 13.8.3 Operation in link array chain transfer mode Figure 13.8.6 shows the operation flowchart of the link array chain transfer mode, and Figures 13.8.7 and 13.8.8 show timing diagrams of the link array chain transfer mode (burst transfer mode). In addition, Figure 13.8.9 shows the conditions necessary for timings shown in Figures 13.8.7, 13.8.8, and 13.8.10 through 13.8.14. For the cycle-steal transfer mode, refer to the following: * Transfer of transfer parameters in an array state: Figures 13.8.10 and 13.8.11 * All transfers except for that in an array state and except for the last 1-unit transfer of each block: Figure 13.8.12 * Last 1-unit transfer of each block except for the last block: Figure 13.8.13 * Last 1-unit transfer of the last block: Figure 13.8.14 The processing performed in the link array chain transfer mode consists of an array state and a transfer state. (1) Array state In an array state, transfer parameters are read from the transfer parameter memory in a unit of 2 bytes and transferred to registers SARi, DARi, and TCRi and their latches. As shown in Figure 13.8.2, a transfer parameter consists of 4 bytes (24 bits of data + 8 bits of dummy data). One bus cycle always consumes 3 cycles of . _________ During an array state, the DMAACKi pin outputs "H" level. For the bus request sampling in an array state, refer to section "13.2.1 Bus access control circuit." (2) Transfer state Data is transferred in a transfer state. For the bus request sampling in a transfer state, refer to section "13.2.1 Bus access control circuit." 7721 Group User`s Manual 13-87 DMA CONTROLLER 13.8 Link array chain transfer mode First of each block ? On and after second First SARi Transfer parameter (Note) (Transfer source's transfer start address) DARi Transfer parameter (Note) (Transfer destination's transfer start address) TCRi Transfer parameter (Byte number of transfer data) SARi latch Transfer parameter (Start address of next transfer parameter memory) DMAi request bit 0 (Only in cycle-steal transfer mode) 1-unit transfer (Refer to section "13.4 Operation.") Burst*Edge Burst*Level*L Cycle-steal*Requested Transfer completion of 1 block ? Burst*Edge Burst*Level*L Cycle-steal*Requested N Y N DMAi request bit ? 1 Transfer completion of all blocks ? SARi latch = 0 ? Y. Completion 0 Burst*Level*H Cycle-steal*No request 1 DMAi request bit ? 0 Burst*Level*H Cycle-steal*No request TC "L" output (Note) DMAi interrupt request bit 1 DMAi enable bit 0 Note: When TC pin validity bit is "1" DMAi request bit 0 (Only in burst transfer mode (edge sense)) Burst*Edge : In burst transfer mode (edge sense) Burst*Level*L : In burst transfer mode (level sense) with DMAREQi pin's input level = L Burst*Level*H : In burst transfer mode (level sense) with DMAREQi pin's input level = H Cycle-steal*Requested : In cycle-steal transfer mode with any request of DMA0-3 Cycle-steal*No request : In cycle-steal transfer mode with no request of DMA0-3 SARi latch indicates the start address of the transfer parameter memory of the next block. Note: The above figure applies when 2-bus cycle transfer is performed. When data is transferred from memory to I/O in 1-bus cycle transfer, there is no "DARi Transfer parameter." When data is transferred from I/O to memory in 1-bus cycle transfer, there is no "SARi Transfer parameter." Fig. 13.8.6 Operation flowchart of link array chain transfer mode 13-88 7721 Group User's Manual Continue to "Figure 13.8.8." 1 ALE E H R/W (tp1+2)L (tp1+6)L (tp1+6)M (tp1+10)M A0-A7 (tp1+2)M (tp1+4)M (tp1+8)M PCL (tp1+10)L Dummy data Dummy data tp1L da1M da1L (tp1+6)H (tp1+8)H (tp1+10)H (tp1+4)L Dummy data (tp1+8)L mM mL (tp1+12)L (tp1+12)M (tp1+14)L tp2M (tp1+14)M A8/D8-A15/D15 (tp1+2)H (tp1+4)H PCH sa1H da1H tp1M sa1M Dummy data A16/D0-A23/D7 PG tp1H sa1L mH (tp1+12)H tp2L (tp1+14)H tp2H Bus request sampling H Fig. 13.8.7 Timing diagram of link array chain transfer mode (burst transfer mode) (1) 7721 Group User`s Manual 1, 0 (DMAC) Transfer of transfer parameters Array state DMAACKi H TC ST1, ST0 Transfer of 1 transfer parameter DMA CONTROLLER Transition of right to use bus qThe Bus request caused by DRAM refresh or Hold is sampled while the bus request sampling signal is "1," and is accepted. 13.8 Link array chain transfer mode 13-89 13-90 From preceding " Figure 13.8.7" 1 ALE E DMA CONTROLLER R/W da1L (da1+m-2)L 13.8 Link array chain transfer mode A0-A7 DataH tp2L tp2L 0016 0016 0016 sa2H tp2M sa2M sa2H 0016 Dummy data sa1L (sa1+m)M (sa1+m)H tp2H (sa1+m)L (tp2+14)L sa2L (da2+n-2)L DataH (sa2+n)L (sa2+n)M PCL PCH A8/D8-A15/D15 DataL DataL tp2M sa1M DataH da1M DataH sa2M DataH DataL A16/D0-A23/D7 tp2H sa1H DataL da1H DataL (sa2+n)H PG Bus request sampling Fig. 13.8.8 Timing diagram of link array chain transfer mode (burst transfer mode) (2) 7721 Group User's Manual 1,0 (DMAC) Transfer of data Transfer state Array state DMAACKi TC 1, 1 (CPU) ST1, ST0 1-unit transfer Array state Transfer state Terminate processing Transition of right to use bus DMA CONTROLLER 13.8 Link array chain transfer mode Figure 13.8.9 shows the conditions necessary for timings shown in Figures 13.8.7, 13.8.8, and 13.8.10 through 13.8.14. External data bus width Transfer unit Transfer method Transfer mode Transfer source address direction Transfer destination address direction Transfer source Wait Transfer destination Wait sa1, sa2, da1, da2 tp1 Transfer block's number Right to use bus : 16 bits : 16 bits : 2-bus cycle transfer : Burst ("Figure 13.8.7" and "Figure 13.8.8") : Cycle-steal ("Figure 13.8.10" through "Figure 13.8.14") : Forward : Forward : No : No : Transfer parameter (even) : Start address of first block's transfer parameter memory :2 : CPU DMAC CPU Memory tp1 tp1+4 tp1+8 tp1+12 Memory sa1 First block transfer First block's transfer parameter Memory da1 sa1 da1 m tp2 sa1+m-1 sa1+m sa2 Second block transfer da1+m-1 da1+m da2 tp2 tp2+4 tp2+8 sa2 da2 n Second block's transfer parameter sa2+n-1 sa2+n da2+n-1 da2+n tp2+12 00000016 Fig. 13.8.9 Conditions necessary for timings shown in Figures 13.8.7, 13.8.8, and 13.8.10 through 13.8.14 7721 Group User`s Manual 13-91 13-92 Continue to "Figure 13.8.11." q Initial term for processing each block in array chain and link array chain transfer modes The operation from an array state to the first 1-unit transfer is continuously performed by one DMAi request. 1 ALE E H R/W PCL tp1L (tp1+2)L (tp1+4)L (tp1+4)M DMA CONTROLLER A0-A7 (tp1+6)L (tp1+6)M (tp1+8)L mM (tp1+8)H 13.8 Link array chain transfer mode A8/D8-A15/D15 da1 M da1L (tp1+6)H PCH sa1M (tp1+2)M tp1M Dummy data Dummy data (tp1+8)M A16/D0-A23/D7 PG sa1L (tp1+2)H (tp1+4)H tp1H sa1H da1H mL V1 Bus request sampling H Fig. 13.8.10 Timing diagram of cycle-steal transfer mode (1) 7721 Group User's Manual DMAACKi H TC 1, 0 (DMAC) ST1, ST0 Transfer of transfer parameters Array state Transition of right to use bus q The above figure is the example of initial term for processing the first block in "Figure 13.8.9." q The Bus request caused by DRAM refresh or Hold is sampled while the bus request sampling signal is "1," and is accepted. q The Bus request caused by DMA is sampled while the bus request sampling signal (V1) is "1" in the transition of the right to use bus, and is accepted. The DMA requests of the other channels are not accepted in an array state. From preceding "Figure 13.8.10" 1 ALE E R/W (tp1+10)L (tp1+12)L (tp1+14)L tp2H sa1L da1L PCL (tp1+14)M A0-A7 Dummy data (tp1+12)M A8/D8-A15/D15 mH (tp1+12)H (tp1+10)M tp2M Dummy data tp2M sa1M DataH da1 M Data H sa1H Data L PCH A16/D0-A23/D7 (tp1+10)H tp2L (tp1+14)H tp2H tp2L da1H Data L PG V1 Bus request sampling DMAACKi Fig. 13.8.11 Timing diagram of cycle-steal transfer mode (2) 7721 Group User`s Manual H TC 1, 0 (DMAC) Transfer of transfer parameters Array state V2 First 1-unit transfer ST1, ST0 1, 1 (CPU) Transition of right to use bus DMA CONTROLLER 13.8 Link array chain transfer mode q The above figure is the example of initial term for processing the first block in "Figure 13.8.9." When the array chain transfer mode is selected, there is not the term of V2. q The Bus request caused by DRAM refresh or Hold is sampled while the bus request sampling signal is "1," and is accepted. q The Bus request caused by DMA is sampled while the bus request sampling signal (V1) is "1" in transition of the right to use bus, and is accepted. The DMA requests of the other channels are not accepted in an array state. 13-93 DMA CONTROLLER 13.8 Link array chain transfer mode q 1-unit transfer 1-unit transfer is performed with a DMAi request on the following conditions: * Single transfer mode (except for the last 1-unit transfer) * Repeat transfer mode (except for the last 1-unit transfer of block) * Array chain transfer mode (except for the first and last 1-unit transfers of each block) * Link array chain transfer mode (except for the first and last 1-unit transfers of each block) 1 ALE E R/W A0-A7 A8/D8-A15/D15 A16/D0-A23/D7 Bus request sampling DMAACKi TC ST1, ST0 H PCL PCH PG (sa1+2)L (sa1+2)M (da1+2)L (da1+2)M PCL PCH PG Data H Data H (sa1+2)H DataL (da1+2)H DataL 1, 0 (DMAC) 1-unit transfer 1, 1 (CPU) Transition of right to use bus Transition of right to use bus q The above figure is the example of the second 1-unit transfer for processing the first block in "Figure 13.8.9." q The Bus request caused by DRAM refresh, Hold, or DMA is sampled while the Bus request sampling signal is "H," and is accepted. Fig. 13.8.12 Timing diagram of cycle-steal transfer mode (3) 13-94 7721 Group User's Manual DMA CONTROLLER 13.8 Link array chain transfer mode q Last transfer of each block At the last term (except for the last block) for processing of each block in the repeat, array chain, and link array chain transfer modes, 1-unit transfer is performed with one DMAi request, and the right to use bus is relinquished after 3 cycles of . 1 ALE E R/W A0-A7 A8/D8-A15/D15 A16/D0-A23/D7 Bus request sampling DMAACKi TC ST1, ST0 H PCL PCH PG (sa1+m-2)L (sa1+m-2)M (da1+m-2)L (da1+m-2)M (sa1+m)L (sa1+m)M (sa1+m)H PCL PCH PG DataH DataH (sa1+m-2)H DataL (da1+m-2)H DataL 1, 0 (DMAC) 1-unit transfer 1, 1 (CPU) Transition of right to use bus Transition of right to use bus q The above figure is the example of the last term for processing the first block in "Figure 13.8.9." q The Bus request caused by DRAM refresh, Hold, or DMA is sampled while the bus request sampling signal is "H," and is accepted. Fig. 13.8.13 Timing diagram of cycle-steal transfer mode (4) 7721 Group User`s Manual 13-95 DMA CONTROLLER 13.8 Link array chain transfer mode q Last transfer of last block At the last term for processing the last block in the single, array chain, and link array chain transfer modes, 1-unit transfer and terminate processing are subsequently performed with one DMAi request. 1 ALE E R/W A0-A7 A8/D8-A15/D15 A16/D0-A23/D7 Bus request sampling DMAACKi TC ST1, ST0 H PCL PCH PG (sa2+n-2)L (sa2+n-2)M (da2+n-2)L (da2+n-2)M (sa2+n)L (sa2+n)M (sa2+n)H PCL PCH PG DataH DataH (sa2+n-2)H DataL (da2+n-2)H Data L 1, 0 (DMAC) 1, 1 (CPU) 1-unit transfer Transition of right to use bus Terminate processing Transition of right to use bus q The above figure is the example of the last term for processing the second block in "Figure 13.8.9." q The Bus request caused by DRAM refresh, Hold, or DMA is sampled while the bus request sampling signal is "H," and is accepted. Fig. 13.8.14 Timing diagram of cycle-steal transfer mode (5) 13-96 7721 Group User's Manual DMA CONTROLLER 13.8 Link array chain transfer mode [Precautions for link array chain transfer mode] If the following two conditions are satisfied when the transfer unit is 16 bits and the address direction of transfer source or destination is fixed, the link array chain transfer mode can be used: * The external data bus width = 16 bits or the internal memory is used. * The transfer start address on the address-direction-fixed side is an even address. 7721 Group User`s Manual 13-97 DMA CONTROLLER 13.9 DMA transfer time 13.9 DMA transfer time Calculation of time from the CPU's relinquishing the right to use bus until its regaining the right under the following conditions is described with reference to cycles of : * A DMAi request is generated while the CPU holds the right to use bus. * The above right is returned to the CPU after completion of DMA transfer for one DMA request. For the time per 1-unit transfer, refer to section "13.4.1 (2) Bus operation in 2-bus cycle transfer" and section "13.4.2 (2) Bus operation in 1-bus cycle transfer." Also, for the time from DMA request generation until the start of the DMA transfer, refer to section "13.3.4 Processing from DMA request until DMA transfer execution": and for that from issuing instructions for forced termination until returning the right to use bus to the CPU, refer to section "13.3.5 (2) Forced termination." 13.9.1 Cycle-steal transfer mode (1) 1-unit transfer In the following cases, 1-unit transfer is performed at one DMAi transfer. (Refer to "Figure 13.8.12.") * Single transfer mode: except for the last 1-unit transfer * Repeat transfer mode: except for the last 1-unit transfer of a block * Array chain transfer mode: except for the first and last 1-unit transfers of each block * Link array chain transfer mode: except for the first and last 1-unit transfers of each block Right to use bus CPU Transition DMAC Transfer Transition CPU Fig. 13.9.1 1-unit transfer Transition of the right to use bus from CPU to DMAC: 1 cycle DMA transfer per 1-transfer unit: * In 2-bus cycle transfer***Read cycle + Write cycle (Add a value which satisfies the read/write conditions. Refer to "Table 13.4.1.") * In 1-bus cycle transfer***Refer to "Table 13.4.5." Transition of the right to use bus from DMAC to CPU: 1 cycle [Example] 2-bus cycle transfer, transfer unit =16 bits, external data bus width = 16 bits, and under the following conditions: * Transfer source: address direction = forward, start address of data = even, with Wait * Transfer destination: address direction = backward, start address of data = even, without Wait + + = 1 + (3 + 4) + 1 = 9 cycles 13-98 7721 Group User's Manual DMA CONTROLLER 13.9 DMA transfer time (2) Last transfer of each block In the following cases, 1-unit transfer and the processing for 3 cycles are performed sequentially. (Refer to "Figures 13.8.13 and 13.8.14.") * Single transfer mode: the last 1-unit transfer * Repeat transfer mode: the last 1-unit transfer of a block * Array chain transfer mode: the last 1-unit transfer of each block (including the last block) * Link array chain transfer mode: the last 1-unit transfer of each block (including the last block) Right to use bus CPU Transition DMAC Transfer TerminationTransition etc. CPU Fig. 13.9.2 Last transfer of each block Transition of the right to use bus from CPU to DMAC: 1 cycle DMA transfer per 1-unit transfer: * In 2-bus cycle transfer***Read cycle + Write cycle (Add a value which satisfies the read/write conditions. Refer to "Table 13.4.1.") * In 1-bus cycle transfer***Refer to "Table 13.4.5." Terminate processing or the last processing of each block: 3 cycles Transition of the right to use bus from DMAC to CPU: 1 cycle [Example] 2-bus cycle transfer, transfer unit =16 bits, external data bus width = 16 bits, and under the following conditions: * Transfer source: address direction = forward, start address of data = even, with Wait * Transfer destination: address direction = backward, start address of data = even, without Wait + + + = 1 + (3 + 4) + 3 + 1 = 12 cycles 7721 Group User's Manual 13-99 DMA CONTROLLER 13.9 DMA transfer time (3) Transfer of array state In the following cases, the processing in an array state and the first 1-unit transfer are performed sequentially. (Refer to "Figures 13.8.10 and 13.8.11.") * Array chain transfer mode: the first transfer of each block * Link array chain transfer mode: the first transfer of each block Right to use bus CPU DMAC Transition Array state Transfer Transition CPU Fig. 13.9.3 Transfer of array state Transition of the right to use bus from CPU to DMAC: 1 cycle Array state: The number of transfer parameters x the number of reads of a transfer parameter x the number of bus cycles for a read + 1 cycle (Refer to "Table 13.9.1.") DMA transfer per 1-unit transfer: * In 2-bus cycle transfer***Read cycle + Write cycle (Add a value which satisfies the read/write conditions. Refer to "Table 13.4.1.") * In 1-bus cycle transfer***Refer to "Table 13.4.5." Transition of the right to use bus from DMAC to CPU: 1 cycle [Example] Link array chain transfer mode, external data bus width = 16 bits, 2-bus cycle transfer, transfer unit =16 bits, and under the following conditions: * Transfer source: address direction = forward, start address of data = even, with Wait * Transfer destination: address direction = backward, start address of data =odd, with Wait + + + = 1 + 25 + (3 + 4) + 1 = 34 cycles Table 13.9.1 Time required for processing in array state Number of transfer External data Mode Transfer method parameters bus width Array chain transfer mode 16 bits (Including internal bus) Number of reads of a transfer parameter Time required for processing in array state (Unit: cycle) 8 bits Link array chain transfer mode 16 bits (Including internal bus) 2-bus cycle transfer 1-bus cycle transfer 2-bus cycle transfer 1-bus cycle transfer 2-bus cycle transfer 1-bus cycle transfer 2-bus cycle transfer 1-bus cycle transfer 3 2 3 2 4 3 4 3 2 2 4 4 2 2 4 4 3 x 2 x 3 + 1 = 19 2 x 2 x 3 + 1 = 13 3 x 4 x 3 + 1 = 37 2 x 4 x 3 + 1 = 25 4 x 2 x 3 + 1 = 25 3 x 2 x 3 + 1 = 19 4 x 4 x 3 + 1 = 49 3 x 4 x 3 + 1 = 37 8 bits 13-100 7721 Group User's Manual DMA CONTROLLER 13.9 DMA transfer time 13.9.2 Burst transfer mode (1) Single transfer mode Right to use bus CPU Transition DMAC Transfer TerminationTransition CPU Fig. 13.9.4 Single transfer mode (burst transfer mode selected) Transition of the right to use bus from CPU to DMAC: 1 cycle DMA transfer per an entire batch of data: * In 2-bus cycle transfer***(Read cycle + Write cycle g1) x the number of transfers g2 g1: Add a value which satisfies the read/write conditions. Refer to "Table 13.4.1." g2: When the transfer unit is 16 bits, the number of transfers = the number of transfer bytes/2 When the transfer unit is 8 bits, the number of transfers = the number of transfer bytes * In 1-bus cycle transfer***Refer to "Table 13.4.5." Terminate processing: 3 cycles Transition of the right to use bus from DMAC to CPU: 1 cycle [Example] External data bus width = 16 bits, 2-bus cycle transfer, transfer unit =16 bits, the number of the transfer bytes = 10 bytes, and under the following conditions: * Transfer source: address direction = forward, start address of data = even, with Wait * Transfer destination: address direction = backward, start address of data = even, without Wait + + + = 1 + 5 (3 + 4) + (3 + 1) = 40 cycles 7721 Group User's Manual 13-101 DMA CONTROLLER 13.9 DMA transfer time (2) Repeat transfer mode In the repeat transfer mode of burst ___ transfer (edge sense), the method of terminating DMA transfer is only the forced termination by the TC input. Therefore, the time from ___ CPU's relinquishing the the right to use bus until regaining the right depends on the timing of the TC input. TC input Right to use bus CPU DMAC CPU Transition Transfer 1 block Transfer Transfer Transition Fig. 13.9.5 Repeat transfer mode (burst transfer mode and edge sense selected) Transition of the right to use bus from CPU to DMAC: 1 cycle DMA transfer per 1 block: * In 2-bus cycle transfer***(Read cycle + Write cycle g1) x the number of transfers g2 g1: Add a value which satisfies the read/write conditions. Refer to "Table 13.4.1." g2: When the transfer unit is 16 bits, the number of transfers = the number of transfer bytes/2 When the transfer unit is 8 bits, the number of transfers = the number of transfer bytes * In 1-bus cycle transfer***Refer to "Table 13.4.5." Terminate processing: 3 cycles ___ DMA transfer of the block at the TC input: above The number of transfers is assumed to be up to the DMA transfer of 1-unit transfer which was in ___ progress at the TC input. Transition of the right to use bus from DMAC to CPU: 1 cycle [Example] External data bus width = 16 bits, 2-bus cycle transfer, transfer unit =16 bits, the number of the transfer bytes = 10 bytes, and under the following conditions: * Transfer source: address direction = forward, start address of data = even, with Wait * ___ Transfer destination: address direction = backward, start address of data = even, without Wait * TC is input when the "m"th byte (m = even) of the "n"th block is in transfer. + (n - 1) ( + ) + + = 1 + (n - 1){5(3 + 4) + 3} + m/2 + 1 = 38n + m/2 - 36 cycles 13-102 7721 Group User's Manual DMA CONTROLLER 13.9 DMA transfer time (3) Array chain transfer mode and Link array chain transfer mode Right to use bus CPU DMAC Transition Array state Transfer Array state Transfer Termination Transition CPU 1 block Fig 13.9.6 Array chain transfer mode and Link array chain transfer mode Transition of the right to use bus from CPU to DMAC: 1 cycle Array state: The number of transfer parameters x the number of reads of a transfer parameterx the number of bus cycles for a read + 1 cycle (Refer to "Table 13.9.1.") DMA transfer per an entire batch of data: * In 2-bus cycle transfer***(Read cycle + Write cycle g1) x the number of transfers g2 g1: Add a value which satisfies the read/write conditions. Refer to "Table 13.4.1." g2: When the transfer unit is 16 bits, the number of transfers = the number of transfer bytes/2 When the transfer unit is 8 bits, the number of transfers = the number of transfer bytes * In 1-bus cycle transfer***Refer to "Table 13.4.5." Last processing of each block: 3 cycles Terminate processing: 3 cycles Transition of the right to use bus from DMAC to CPU: 1 cycle [Example] Array chain transfer mode, external data bus width = 16 bits, 2-bus cycle transfer, transfer unit =16 bits, the number of transfer blocks = 3, and under the following conditions: * Transfer source: address direction = forward, without Wait * Transfer destination: address direction = backward, without Wait * First block: transfer source's data start address = even, transfer destination's data start address = even, the number of transfer bytes =10 bytes * Second block: transfer source's data start address = even, transfer destination's data start address =odd, the number of transfer bytes =12 bytes * Third block: transfer source's data start address =odd, transfer destination's data start address =odd, the number of transfer bytes =14 bytes ++++++++++ = 1 + 19 + 5(2 + 4) + 3 + 19 + 6(2 + 3) + 3 + 19 + 7(4 + 3) + 3 + 1 = 177 cycles 7721 Group User's Manual 13-103 DMA CONTROLLER 13.9 DMA transfer time MEMORANDUM 13-104 7721 Group User's Manual CHAPTER 14 DRAM CONTROLLER 14.1 14.2 14.3 14.4 14.5 Overview Block description Setting for DRAMC DRAMC operation Precautions for DRAMC DRAM CONTROLLER 14.1 Overview, 14.2 Block description 14.1 Overview Table 14.1.1 lists the performance specifications of DRAM controller (hereafter called DRAMC). Table 14.1.1 Performance specifications of DRAMC Item DRAM area Refreshing method Refresh timer Multiplexed address pins Performance specifications 0 to 15 Mbytes; programmable in a unit of 1 Mbyte ____ ____ CAS before RAS; dispersive refreshing 8 bits 10 14.2 Block description Figure 14.2.1 shows the block diagram of DRAMC. Registers relevant to DRAMC are described below. f(XIN) Refresh request 1/16 f16 RAS CAS Bus Access controller Refresh timer 1/(n+1) Bits 0-3 DRAM control register A20-A23 A0-A20 Address Address comparator RAS and CAS generating circuit Address multiplexer MA0-MA9 Fig. 14.2.1 Block diagram of DRAMC 14-2 7721 Group User's Manual DRAM CONTROLLER 14.2 Block description 14.2.1 DRAM control register Figure 14.2.2 shows the structure of the DRAM control register. b7 b6 b5 b4 b3 b2 b1 b0 DRAM control register (Address 6416) Bit 0 Bit name b3 b2 b1 b0 Functions 0 0 0 0 : No DRAM area 0 0 0 1 : F0000016-FFFFFF16 (1 Mbyte) 0 0 1 0 : E0000016-FFFFFF16 (2 Mbytes) 0 0 1 1 : D0000016-FFFFFF16 (3 Mbytes) 0 1 0 0 : C0000016-FFFFFF16 (4 Mbytes) 0 1 0 1 : B0000016-FFFFFF16 (5 Mbytes) 0 1 1 0 : A0000016-FFFFFF16 (6 Mbytes) 0 1 1 1 : 90000016-FFFFFF16 (7 Mbytes) 1 0 0 0 : 80000016-FFFFFF16 (8 Mbytes) 1 0 0 1 : 70000016-FFFFFF16 (9 Mbytes) 1 0 1 0 : 60000016-FFFFFF16 (10 Mbytes) 1 0 1 1 : 50000016-FFFFFF16 (11 Mbytes) 1 1 0 0 : 40000016-FFFFFF16 (12 Mbytes) 1 1 0 1 : 30000016-FFFFFF16 (13 Mbytes) 1 1 1 0 : 20000016-FFFFFF16 (14 Mbytes) 1 1 1 1 : 10000016-FFFFFF16 (15 Mbytes) At reset RW RW DRAM area select bits 0 1 0 RW 2 0 RW 3 0 RW 6 to 4 7 Nothing is assigned. The value is "0" at reading. DRAM validity bit (Note) 0 : Invalid (P104-P107 pins function as programmable input ports. A0- A7 pins function as address output pins. Refresh timer stops counting.) 1 : Valid (P104-P107 pins function as CAS, RAS, MA8, and MA9. A0-A7 function as MA0-MA7. Refresh timer starts counting.) 0 0 - RW Note: Set the refresh timer (address 6616) before setting this bit to "1." Fig. 14.2.2 Structure of DRAM control register 7721 Group User's Manual 14-3 DRAM CONTROLLER 14.2 Block description (1) DRAM area select bits (bits 0 to 3) These 4 bits specify a DRAM area of 15 Mbytes maximum in a unit of 1 Mbyte. Figure 14.2.3 shows setting examples of DRAM areas. 1 Mbyte 00000016 00000016 4 Mbytes 00000016 8 Mbytes 00000016 10000016 15 Mbytes 80000016 Maximum C0000016 F0000016 FFFFFF16 Minimum (00012) FFFFFF16 FFFFFF16 FFFFFF16 DRAM area select bits (Bits 3-0) (01002) (10002) (11112) DRAM area Fig. 14.2.3 Setting examples of DRAM areas (2) DRAM validity bit (bit 7) When this bit is set to "1," pin functions for DRAM control become valid, and the refresh timer starts counting. Table 14.2.1 lists the pin functions for DRAM control. Table 14.2.1 Pin functions for DRAM control Pins DRAM validity bit Operation A0/MA0 -A7/MA7 Accessing DRAM area 1 DRAM refresh MA0-MA7 _______ P106/MA8, P107/MA9 MA8, MA9 P104/CAS, _______ A16/D0-A23/D7, ___ ST0, ST1 P105/RAS _______ _______ A8/D8-A15/D15, __ _______ _______ ST0, ST1 CAS, RAS R/W, E, BLE, BHE A16/D0-A23/D7, ___ A8/D8-A15/D15, __ _______ ________ A16/D0-A23/D7, ST0, ST1 ([0,0] is output.) ST0, ST1 _______ _______ R/W, E, BLE, BHE A8/D8-A15/D15 __ _______ ________ A0-A7 MA8, MA9 CAS, RAS ___ _______ _______ Other than the above A0-A7 MA8, MA9 CAS, RAS R/W, E, BLE, BHE A16/D0-A23/D7, ___ A8/D8-A15/D15, __ _______ ________ A16/D0-A23/D7, ST0, ST1 R/W, E, BLE, BHE A0-A7 0 -- P106, P107 P104,P105 A8/D8-A15/D15 ___ __ _______ ________ R/W, E, BLE, BHE 14-4 7721 Group User's Manual DRAM CONTROLLER 14.2 Block description 14.2.2 Refresh timer The refresh timer is an 8-bit timer with a reload register and is used to generate refresh requests for DRAM data. Assuming that the set value of the refresh timer = "n," the refresh timer counts f16 (n + 1) times. Figure 14.2.4 shows the structure of the refresh timer, and the following formula gives the value to be written to the refresh timer. n = {m [s] ! f(XIN) }-1 16 n: a set value of the refresh timer (n = 0116-FF16) m: a refresh interval Examples of "m": an average of 15.625 s for 512 refresh cycles at 8-ms intervals an average of 125 s for 512 refresh cycles at 64-ms intervals b7 b0 Refresh timer (Address 6616) Bit Functions At reset Undefined RW WO 7 to 0 These bits can be set to "0116" to "FF16." Assuming that the set value = n, this register divides f16 by (n + 1). Note: Use the LDM or STA instruction for writing to this register. Do not set this register to "0016." Fig. 14.2.4 Structure of refresh timer 7721 Group User's Manual 14-5 DRAM CONTROLLER 14.2 Block description 14.2.3 Address comparator The address comparator examines whether the address to be accessed is____ within the DRAM area. When ____ this address is within DRAM area, control signals are sent to the RAS and CAS generating circuit and the address multiplexer. ____ ____ 14.2.4 RAS and CAS generating circuit ____ ____ The RAS signal (a timing signal to latch a row address) and the CAS signal (a timing signal to latch a column address) are generated by a control signal from the address comparator. 14.2.5 Address multiplexer Address data is time-shared by the control signal from the address comparator and is output to the MA0- MA9 pins. The time-sharing method depends on the external bus width. Table 14.2.2 lists the time-sharing method for the address at DRAM access. When the 8-bit external bus width is selected, A0-A19 are timeshared and are output; when the 16-bit external bus width is selected, A1-A20 are time-shared and are output. Table 14.2.2 Time-sharing method for address at DRAM access Pin name Output signal 8-bit external Row address bus width Column address 16-bit external Row address bus width Column address A0/MA0 A1/MA1 A2/MA2 A3/MA3 A4/MA4 A5/MA5 A6/MA6 A7/MA7 P106/MA8 P107/MA9 A0 A8 A16 A8 A1 A9 A1 A9 A2 A10 A2 A10 A3 A11 A3 A11 A4 A12 A4 A12 A5 A13 A5 A13 A6 A14 A6 A14 A7 A15 A7 A15 A16 A17 A18 A17 A18 A19 A20 A19 14-6 7721 Group User's Manual DRAM CONTROLLER 14.3 Setting for DRAMC 14.3 Setting for DRAMC Figure 14.3.1 shows an initial setting example for registers relevant to DRAMC. Division ratio setting for refresh timer b7 b0 Refresh timer (Address 6616) Can be set to "0016" to "FF16" (n). Refresh timer divides f16 by (n+1). DRAM area setting and DRAM validity selection b7 b0 1 DRAM control register [Address 6416] DRAM area select bits b3 b2 b1 b0 0 0 0 0: No DRAM area 0 0 0 1: Addresses F0000016-FFFFFF16 (1 Mbyte) 0 0 1 0: Addresses E0000016-FFFFFF16 (2 Mbytes) 0 0 1 1: Addresses D0000016-FFFFFF16 (3 Mbytes) 0 1 0 0: Addresses C0000016-FFFFFF16 (4 Mbytes) 0 1 0 1: Addresses B0000016-FFFFFF16 (5 Mbytes) 0 1 1 0: Addresses A0000016-FFFFFF16 (6 Mbytes) 0 1 1 1: Addresses 90000016-FFFFFF16 (7 Mbytes) 1 0 0 0: Addresses 80000016-FFFFFF16 (8 Mbytes) 1 0 0 1: Addresses 70000016-FFFFFF16 (9 Mbytes) 1 0 1 0: Addresses 60000016-FFFFFF16 (10 Mbytes) 1 0 1 1: Addresses 50000016-FFFFFF16 (11 Mbytes) 1 1 0 0: Addresses 40000016-FFFFFF16 (12 Mbytes) 1 1 0 1: Addresses 30000016-FFFFFF16 (13 Mbytes) 1 1 1 0: Addresses 20000016-FFFFFF16 (14 Mbytes) 1 1 1 1: Addresses 10000016-FFFFFF16 (15 Mbytes) DRAM is valid. (P104-P107 pins function as CAS,RAS, MA8, and MA9. A0-A7 function as MA0-MA7 when accessing the DRAM area. Refresh timer starts counting.) *During DRAM area access, CAS, RAS, and MA0-MA9 are output. *Each time an underflow of the refresh timer occurs, CAS and RAS for refresh are output. *During refresh, ST0 and ST1 output "L" level. Fig. 14.3.1 Initial setting example for registers relevant to DRAMC 7721 Group User's Manual 14-7 DRAM CONTROLLER 14.4 DRAMC operation 14.4 DRAMC operation 14.4.1 Waveform example of DRAM control signals Figure 14.4.1 shows a waveform example of the DRAM control signals. When DRAM is accessed, the bus __ cycle is always with "wait" (the low-level width of E is equivalent to 2 cycles of ). It is not affected by the wait bit, the wait bit of the transfer source, and the wait bit of the transfer destination. (1) Read Cycle ____ ____ In the read cycle, the CAS signal falls with a delay of 0.5 cycle of after the RAS signal has changed from "H" to "L." The address bus signal ____ changes from "row address" to "column address" within a ____ period from a fall of RAS until a fall of CAS. Pins A16/D0-A23/D7 and A8/D8-A15/D15 output addresses and input data in the same way as in reading external devices other than DRAM. (2) Write Cycle ____ ____ In the write cycle, the CAS signal falls with a delay of 1 cycle of after the RAS signal has changed from "H" to "L." The address bus ____ changes "row address" to "column address" within a period signal ____ from a fall of RAS until a fall of CAS. Pins A16/D0-A23/D7 and A8/D8-A15/D15 output addresses and data in the same way as in writing external devices other than DRAM. (3) Refresh Cycle ____ ____ In the refresh cycle, the RAS signal falls with a delay of 0.5 cycle of after the CAS signal has changed from "H" to "L." __ R/W is undefined. One refresh request requires 5 cycle of , including the time for passing the right to use buses. 14-8 7721 Group User's Manual DRAM CONTROLLER 14.4 DRAMC operation (a) At reading E RAS CAS R/W MA0-MA9 A16/D0-A23/D7 A8/D8-A15/D15 Row address Address Column address Data Read cycle (1 bus cycle) (b) At writing E RAS CAS R/W MA0-MA9 A16/D0-A23/D7 A8/D8-A15/D15 Row address Address Column address Data Write cycle (1 bus cycle) (c) At refresh E RAS CAS R/W MA0-MA9 A16/D0-A23/D7 A8/D8-A15/D15 Undefined Undefined Undefined Transition of right to use bus Floating Refresh cycle Undefined Transition of right to use bus Fig. 14.4.1 Waveform example of DRAM control signals 7721 Group User's Manual 14-9 DRAM CONTROLLER 14.4 DRAMC operation 14.4.2 Refresh request When the DRAM validity bit is set to "1," the refresh timer starts counting down. The count source is f16. When the contents of the refresh timer reach "0016," a refresh request occurs. The refresh timer reloads the contents of address 6616 and continues counting. Refresh requests are sampled as bus requests (DRAMC) by using the bus access controller. As soon as a refresh request is acknowledged by sampling, the following is performed because DRAM refresh has the highest priority in using the bus. However, when the CPU or DMAC uses the bus, no bus request is sampled until the CPU or DMAC releases the bus. Therefore, in a period from when a refresh request occurs until DRAM refresh is performed, the delay listed in Table 14.4.1 occurs depending on the refresh request generating timing. Figures 14.4.2 and 14.4.3 show refresh delay time examples when CPU is operating and during DMA transfer. For a bus request, refer to "13.2.1 Bus access control circuit." When the refresh request is accepted, the right to use the bus is passed to DRAM refresh (1 cycle of ). Both of the output levels of ST1 and ST0 are "L." (The bus status is indicated as [0, 0].) ____ ____ The RAS and the CAS signals are output and the DRAM data is refreshed (refresh cycle: 3 cycles of ). The right to use the bus is passed to the CPU, DRAM or Hold (1 cycle of ). The outputs of ST1 and ST0 change. Note: In Stop or Wait mode, DRAM refresh is not performed because no refresh request occurs. Table 14.4.1 Delay time from when refresh request occurs until DRAM refresh is performed Delay time (unit: cycle) Source of using bus Maximum (no Wait) Maximum (with Wait) Minimum 4.5 6.5 1.5 CPU Transfer (a unit of 1 transfer) 8.5 12.5 DMAC Transfer (a unit of 1 transfer) + Complete cycle 11.5 15.5 1.5 Array state 6.5 6.5 1.5 1.5 1.5 Hold Note: The above is applied when Ready is not used. The delay time includes the time for passing the right to use buses to DRAM refresh (1 cycle). 14-10 7721 Group User's Manual DRAM CONTROLLER 14.4 DRAMC operation E R/W Refresh request Bus request (DRAMC) Bus request sampling ST1,ST0 Delay time (Min.): 1.5 cycles of 00 Refresh cycle 11 (CPU) 00 (Refresh) Refresh cycle Delay time (Max.): 6.5 cycles of Transition of right to use bus Transition of right to use bus Transition of right to use bus Transition of right to use bus The following are internal signals: *Refresh request *Bus request (DRAMC) *Bus request sampling Refresh request becomes "0" at an underflow of the refresh timer. Fig. 14.4.2 Refresh delay time example when CPU is operating E R/W Refresh request Bus request (DRAMC) Bus request sampling ST1,ST0 10 (DMAC) Delay time (Max.): 12.5 cycles of 00 (Refresh) Refresh cycle Transition of right to use bus The following are internal signals: *Refresh request *Bus request (DRAMC) *Bus request sampling Refresh request becomes "0" at an underflow of the refresh timer. Fig. 14.4.3 Refresh delay time example during DMA transfer 7721 Group User's Manual 14-11 DRAM CONTROLLER 14.5 Precautions for DRAMC 14.5 Precautions for DRAMC 1. Set the refresh timer (address 6616) to any of 0116-FF16. 2. When a DRAM refresh request occurs during Hold state, a refresh cycle is activated regardless of the bus state. It is because a bus request is always sampled during Hold state. Therefore, in order to use the DRAMC together with the Hold function, an external circuit which is controlled depending on the states of ST0 and ST1 is required. 3. DRAM refresh is not performed in Stop or Wait mode. 14-12 7721 Group User's Manual CHAPTER 15 WATCHDOG TIMER 15.1 Block description 15.2 Operation description 15.3 Precautions for Watchdog timer WATCHDOG TIMER 15.1 Block description Watchdog functions as follows: q Detects a program runaway. q Measures a certain time from when oscillation starts owing to terminating Stop mode. (Refer to section "5.3 Stop mode.") 15.1 Block description Figure 15.1.1 shows the block diagram of Watchdog timer. f32 f512 Watchdog timer Bus request (DRAMC) Bus request (Hold) Bus request (DMAC) Writing to watchdog timer register (address 6016) CPU wait request "FFF16" is set. Watchdog timer interrupt request RESET 2Vcc detection circuit STP instruction S Q R Fig. 15.1.1 Block diagram of Watchdog timer 15-2 7721 Group User's Manual WATCHDOG TIMER 15.1 Block description 15.1.1 Watchdog timer Watchdog timer is a 12-bit counter where the count source which is selected with the watchdog timer frequency select bit (bit 0 at address 6116) is counted down. A value "FFF16" is automatically set in Watchdog timer in the cases listed below. An arbitrary value cannot be set to Watchdog timer. q q q q When dummy data is written to the watchdog timer register (Refer to "Figure 15.1.2.") When the most significant bit of Watchdog timer becomes "0" When the STP instruction is executed (Refer to section "5.3 Stop mode.") At reset b7 b0 Watchdog timer register (Address 6016) Bit 7 to 0 Functions Initializes Watchdog timer. When dummy data is written to this register, Watchdog timer's value is initialized to "FFF16." (Dummy data: 0016 to FF16) At reset Undefined RW - Fig. 15.1.2 Structure of watchdog timer register 15.1.2 Watchdog timer frequency select register This is used to select a Watchdog timer's count source. Figure 15.1.3 shows the structure of the watchdog timer frequency select register. b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer frequency select register (Address 6116) Bit 0 Bit name Watchdog timer frequency select 0 : f512 1 : f32 bit Functions At reset RW RW 0 Undefined 7 to 1 Nothing is assigned. - Fig. 15.1.3 Structure of watchdog timer frequency select register 7721 Group User's Manual 15-3 WATCHDOG TIMER 15.2 Operation description 15.2 Operation description 15.2.1 Basic operation Watchdog timer starts counting down from "FFF16." When the Watchdog timer's most significant bit becomes "0" (counted 2048 times), a watchdog timer interrupt request occurs. (Refer to "Table 15.2.1.") When the interrupt request occurs at above , a value "FFF16" is set to Watchdog timer. The watchdog timer interrupt is a non-maskable interrupt. When the watchdog timer interrupt request is accepted, the processor interrupt priority level (IPL) is set to "1112." Table 15.2.1 Occurrence interval of watchdog timer interrupt request Watchdog timer frequency select bit 0 1 f(XIN) = 25 MHz Count source Occurrence interval f512 41.94 ms f32 2.62 ms 15-4 7721 Group User's Manual WATCHDOG TIMER 15.2 Operation description Write dummy data to the watchdog timer register (address 6016) before the most significant bit of Watchdog timer becomes "0." When Watchdog timer is used to detect a program runaway, a watchdog timer interrupt request occurs if writing to address 6016 is not performed owing to a program runaway and the most significant bit of Watchdog timer becomes "0." This means that a program runaway has occurred. In order to reset the microcomputer when a program runaway is detected, write "1" to the software reset bit (bit 3 at address 5E16) in the watchdog timer interrupt routine. Main routine Watchdog timer register (Address 6016) Watchdog timer interrupt request occur (program runaway detected) 8-bit dummy data Watchdog timer initialized Value of watchdog timer : "FFF16" (Note 1) Watchdog timer interrupt routine Software reset bit (Address 5E16, b3) "1" (Note 2) Reset microcomputer RTI Notes 1: Initialize Watchdog timer before the most significant bit of Watchdog timer becomes "0." (Write dummy data to address 6016 before a watchdog timer interrupt request occurs). 2: When a program runaway occurs, values of the data bank register (DT), direct page register (DPR), etc., may be changed. When "1" is written to the software reset bit by the addressing mode using DT, DPR, etc., set values to DT and DPR again. Fig. 15.2.1 Example of program runaway detection by Watchdog timer 7721 Group User's Manual 15-5 WATCHDOG TIMER 15.2 Operation description 15.2.2 Stop period Watchdog timer stops operation in the following period: Hold state (Refer to section "3.4 Hold function.") During DMAC operation (Refer to "CHAPTER 13. DMA CONTROLLER.") During DRAM refresh (Refer to "CHAPTER 14. DRAM CONTROLLER.") Stop mode When states to are terminated, Watchdog timer restarts counting from the state before it stops operation. For Watchdog timer's operation when state is terminated, refer to section "15.2.3 Operation in Stop mode." 15.2.3 Operation in Stop mode In Stop mode, Watchdog timer stops operation. Immediately after Stop mode is terminated, Watchdog timer operates as follows. (Refer to section "5.3 Stop mode.") (1) When Stop mode is terminated by hardware reset Supply of and CPU starts immediately after Stop mode is terminated, and the microcomputer performs "operation after reset." (Refer to "CHAPTER 4. RESET.") The watchdog timer frequency select bit becomes "0," and Watchdog timer starts counting of f512 from "FFF16." (2) When Stop mode is terminated by interrupt request occurrence Immediately after Stop mode is terminated, Watchdog timer starts counting of f32 from "FFF16" regardless of the contents of watchdog timer frequency select bit (bit 0 at address 6116). Supply of and CPU starts when Watchdog timer's most significant bit becomes "0." (At this time, a watchdog timer interrupt request does not occur.) When supply of CPU starts, the microcomputer executes the routine of the interrupt which is used to terminate Stop mode. Watchdog timer restarts counting of the count source (f32 or f512), which was counted immediately before executing the STP instruction, from "FFF16." 15-6 7721 Group User's Manual WATCHDOG TIMER 15.3 Precautions for Watchdog timer 15.3 Precautions for Watchdog timer 1. When dummy data is written to address 6016 with the 16-bit data length, writing to address 6116 is simultaneously performed. Accordingly, when the user does not want to change a value of the watchdog timer frequency select bit (bit 0 at address 6116), write the previous value to the bit simultaneously with writing to address 6016. 2. When the STP instruction is executed, Watchdog timer stops. (Refer to section "5.3 Stop mode.") 3. Watchdog timer stops during DRAM refresh, hold state, and DMAC operation. (For Watchdog timer's structure, refer to "Figure 15.1.1.") Accordingly, when a bus request is changed in the period which is shorter than 1 cycle of the count source (Note), Watchdog timer's count may gain. (Refer to "Figure 15.3.1.") Note: f32 or f512, which is selected by the watchdog timer frequency select bit f32 or f512 Bus request Count source which is actually counted by Watchdog timer In case the bus request is changed in a period which is shorter than 1 cycle of f32 or f512 Fig. 15.3.1 Count source for Watchdog timer 7721 Group User's Manual 15-7 WATCHDOG TIMER 15.3 Precautions for Watchdog timer MEMORANDUM 15-8 7721 Group User's Manual CHAPTER 16 APPLICATION 16.1 Memory connection 16.2 Examples of using DMA controller 16.3 Comparison of sample program execution rate APPLICATION 16.1 Memory connection This chapter describes application. Application shown here is just examples. The user shall modify them according to the actual application and test them. 16.1 Memory connection This section shows examples for memory and I/O connection. Refer to "CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES" for details about the functions and operations of used pins when connecting a memory or I/O. Refer to section "Appendix 11. Electrical characteristics" for timing requirements of the microcomputer. 16.1.1 Memory connection model For the M37721, the level of the external data bus width select signal makes it possible to select the memory connection model from the four models listed in Table 16.1.1. (1) Minimum model This is a connection model of which external data bus width is 8 bits and access space is expanded up to 64 Kbytes. It is unnecessary to connect the address latch externally, so this model gives priority to cost and is most suitable when connecting the memory of which data bus width is 8 bits. (2) Medium model A This is a connection model of which external data bus width is 8 bits and access space is expanded up to 16 Mbytes. In this model, the high-order 8 bits of the external address bus (A16 to A23) are multiplexed with the external data bus. Therefore, an n-bit (n 8) address latch is required for latching n bits of the address in A16 to A23. (3) Medium model B This is a connection model of which external data bus width is 16 bits and access space is expanded up to 64 Kbytes. This model gives priority to rate performance. In this model, the middle-order 8 bits of the external address bus (A8 to A15) are multiplexed with the external data bus. Therefore, an 8bit address latch is required for latching A8 to A15. (4) Maximum model This is a connection model of which external data bus width is 16 bits and access space is expanded up to 16 Mbytes. In this model, the high- and middle-order 16 bits of the external address bus (A8 to A23) are multiplexed with the external data bus. Therefore, an 8-bit address latch for latching A8 to A15 and an n-bit (n 8) address latch for latching n bits of A16 to A23 are required. 16-2 7721 Group User's Manual APPLICATION 16.1 Memory connection Table 16.1.1 Memory connection model Access space External data bus width BYTE Maximum 64 Kbytes M37721 16 A0-A7 A8-A15 Maximum 16 Mbytes M37721 BYTE A0-A7 A8-A15 A16/D0-A23/D7 Latch n DQ E 16+n A0-A15+n 8-bit width; BYTE = "H" A0-A15 8 A16/D0-A23/D7 D0-D7 Minimum model ALE 8 D0-D7 Memory connection model M37721 Medium model A 16+n Latch 8 DQ E DQ E Memory connection model M37721 BYTE A0-A7 16 Latch 8 DQ E BYTE A0-A7 A0-A15+n A0-A15 A8/D8-A15/D15 A16/D0-A23/D7 A8/D8-A15/D15 16-bit width; BYTE = "L" n 16 A16/D0-A23/D7 ALE BHE BLE 16 ALE Latch D0-D15 BHE BLE D0-D15 Memory connection model Medium model B Memory connection model Maximum model Notes 1: Refer to "CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES" for details about the functions and operations of used pins when connecting a memory. Refer to section "Appendix 11. Electrical characteristics" for timing requirements. 2: Because the address bus can be expanded up to 24 bits when connecting a memory, strengthen the M37721's Vss and Vcc lines on the system. (Refer to section "Appendix 8. Countermeasure against noise.") 7721 Group User's Manual 16-3 APPLICATION 16.1 Memory connection 16.1.2 How to calculate timing Timings at which data is read or written when connecting a memory and precautions when connecting a memory are described below. For timing requirements of the memory and detailed account except limits described below, also refer to the memory's Data book etc. When using bus buffers, various logical circuits, etc., be sure to consider the propagation delay time etc. (1) Timing for reading data When reading data, the external data bus is placed in a floating state, and data _ read from the is external memory. This floating state is maintained after the falling edge of the E signal until an _ interval of tpzx(E-DLZ/DHZ) has passed after the rising edge of the E signal. Satisfy tsu(DL/DH-E) when inputting data read from the external memory. The following are described below: *Timing for reading data from the flash memory, SRAM, and DRAM *Calculation formulas for the external memory's access time, which are for tsu(DL/DH-E) to be satisfied ___ __ The memory output enable signal (OE) is assumed to be generated from the E signal. q Timing for reading data from flash memory and SRAM tw(EL) E External memory output enable signal (Read signal) External memory chip select signal OE CE, S ta(OE) Address ta(AD), tsu(A-DL/DH) ta(CE), ta(S) ten(OE) ten(CE), ten(S) V2 tpzx(E-DLZ/DHZ) Address Address output and Data input A8/D8-A15/D15 V1 A16/D0-A23/D7 tDF, tdis(OE) V3 Data tsu(DL/DH-E) : Specifications of the M37721 (The others are specifications of external memory.) External memory data output V1: This applies when the external data bus has a width of 16 bits (BYTE = "L"). V2: If data is output from the external memory before the falling edge of E, there is a possibility that the tail of address collides with the head of data. Refer to section "(3) Precautions on memory connection." V3: If one of the external memory's specifications is greater than tpzx(E-DLZ/DHZ) , there is a possibility that the tail of data collides wi th the head of address . Refer to section "(3) Precautions on memory connection." Note: tsu(A-DL/DH) : tsu(A-DL) or tsu(A-DH) tpzx(E-DLZ/DHZ) : tpzx(E-DLZ) or tpzx(E-DHZ) tsu(DL/DH-E) : tsu(DL-E) or tsu(DH-E) Fig. 16.1.1 Timing for reading data from flash memory and SRAM 16-4 7721 Group User's Manual APPLICATION 16.1 Memory connection ___ Address access time : ta(AD) tsu(A-DL/DH) - address latch delay time V1 OE access time : ta(OE) tw(EL) - tsu(DL/DH-E) Chip select access time : ta(S) tsu(A-DL/DH) - (address decode time V2 + address latch delay time V1) Address latch delay timeV1 : Delay time required when latching address (Unnecessary in minimum model) V2 Address decode time : Time required for validating chip select signal after decoding address Table 16.1.2 lists the calculation formulas and values for each parameter in Figure 16.1.1. Figure 16.1.2 shows the relationship between tsu(A-DL/DH) and f(XIN). Table 16.1.2 Calculation formulas and Values for each parameter in Figure 16.1.1 (unit : ns) Calculation formulas and Values Wait No Wait tw(EL) 4 ! 10 9 2 ! 10 9 -25 -25 f(XIN) f(XIN) tsu(A-DL) 5 ! 10 9 3 ! 10 9 -70 -70 tsu(A-DH) f(XIN) f(XIN) tpzx(E-DLZ) 1 ! 10 9 -20 tpzx(E-DHZ) f(XIN) tsu(DL-E) 30 tsu(DH-E) [ns] 700 600 644 555 485 430 Data setup time with address stabilized tsu(A-DL/DH) 500 400 358 305 300 200 Wait No Wait 384 346 314 287 263 230 202 263 100 0 7 8 9 10 11 224 207 193 180 180 168 157 160 144 147 138 130 117 130 106 96 87 80 72 66 60 55 50 242 12 13 14 15 16 17 18 19 20 21 22 23 24 25 [MHz] External clock input frequency f(XIN) Fig. 16.1.2 Relationship between tsu(A-DL/DH) and f(XIN) 7721 Group User's Manual 16-5 APPLICATION 16.1 Memory connection q Timing for reading data from DRAM DRAM output enable signal E (Read signal) OE tw(EL) RAS td(E-RASL) CAS td(E-CASL) Address output (MA0-MA7) Row address tOEA td(E-CA) tAA tRAC Column address tpzx(E-DLZ/DHZ) Address output and Data I/O A8/D8-A15/D15 V1 A16/D0-A23/D7 Address tCLZ tCAC tOEZ V2 DRAM data output Data tsu(DL/DH-E) V1 This applies when the external data bus has a width of 16 bits (BYTE = "L"). V2 If one of DRAM's specifications is greater than tpzx(E-DLZ/DHZ) , there is a possibility that the tail of data collides with the head of address. Refer to section "(3) Precautions on memory connection." Note: tpzx(E-DLZ/DHZ) : tpzx(E-DLZ) or tpzx(E-DHZ) tsu(DL/DH-E) : tsu(DL-E) or tsu(DH-E) : Specifications of the M37721 (The others are specifications of DRAM.) Fig. 16.1.3 Timing for reading data from DRAM CAS access time : tCAC tw(EL) - td(E-CASL) - tsu(DL/DH-E) RAS access time : tRAC tw(EL) - td(E-RASL) - tsu(DL/DH-E) Column address access time : tAA tw(EL) - td(E-CA) - tsu(DL/DH-E) ___ OE access time : tOEA tw(EL) - tsu(DL/DH-E) ____ ____ Table 16.1.3 lists the calculation formula and value for each parameter in Figure 16.1.3. Figure 16.1.4 shows the relationship between tCAC, tRAC, tAA and f(XIN). 16-6 7721 Group User's Manual APPLICATION 16.1 Memory connection Table 16.1.3 Calculation formula and Value for each parameter in Figure 16.1.3 (unit : ns) tw(EL) td(E-RASL) td(E-CASL) td(E-CA) Calculation formula and Value 4 ! 10 9 - 25 f(XIN) 30 1 ! 10 9 + 37.5 f(XIN) 1 ! 10 9 + 25 f(XIN) 1 ! 10 9 - 20 f(XIN) tpzx(E-DLZ) tpzx(E-DHZ) tsu(DL-E) 30 tsu(DH-E) Note: When accessing DRAM, Wait is always inserted regardless of the contents of the Wait bit, source's Wait bit, and destination's Wait bit. [ns] 500 486 450 451 415 RAS access time 359 380 315 324 282.5 240.5 207.5 179.5 157.5 280 243 213 187 165 137.5 146 121.5 107.5 130 94.5 278 248 222 200 181 165 150 115 137 102 125 90 CAS access time : tRAC : tCAC Column address access time : tAA 400 350 300 335.5 Access time 250 200 150 100 50 0 7 115 80 105 70 96 61 88 53 81 46 75 83.5 73.5 40 64.5 57.5 49.5 43.5 37.5 32.5 27.5 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 [MHz] External clock input frequency f(XIN) Fig. 16.1.4 Relationship between tCAC, tRAC, tAA and f(XIN) 7721 Group User's Manual 16-7 APPLICATION 16.1 Memory connection (2) Timing for writing data When writing data, _ the output data is stabilized when an interval of td(E-DLQ/DHQ) has passed after the falling edge of the E signal. This data is continuously output until when an interval of th(E-DLQ/DHQ) has _ passed after the rising edge of the E signal. Data to be written to an external memory must satisfy the data set up time (tsu(D)) (for DRAM, the data hold time (tDH)) of the external memory. The following are described below: *Timing for writing data to flash memory, SRAM, and DRAM *Calculation formulas which are for tsu(D) and tDH to be satisfied q Timing for writing data to flash memory and SRAM tw(EL) E External memory write signal External memory chip select signals W CE, S td(E-DLQ/DHQ) Address output and Data input A8/D8-A15/D15 A16/D0-A23/D7 V Address Data th(E-DLQ/DHQ) Address tsu(D) th(D) : Specifications of the M37721 (The others are specifications of external memory.) V This applies when the external data bus has a width of 16 bits (BYTE = "L"). Fig. 16.1.5 Timing for writing data to flash memory and SRAM Data setup time : tsu(D) tw(EL) - td(E-DLQ/DHQ) Table 16.1.4 lists the calculation formulas and values for each parameter in Figure 16.1.5, Figure 16.1.6 shows the relationship between tsu(D) and f(XIN). 16-8 7721 Group User's Manual APPLICATION 16.1 Memory connection Table 16.1.4 Calculation formulas and Values for each parameter in Figure 16.1.5 (unit : ns) Calculation formulas and Values Wait No Wait 4 ! 10 9 2 ! 10 9 -25 -25 f(XIN) f(XIN) 35 1 ! 10 9 -22 f(XIN) tw(EL) td(E-DLQ) td(E-DHQ) th(E-DLQ) th(E-DHQ) [ns] 600 506 500 435 379 335 298 300 220 200 100 0 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 [MHz] 185 157 135 116 101 88 268 242 220 201 Wait No Wait Data setup time tsu(D) 400 77 185 170 157 145 135 125 116 108 101 68 60 52 46 40 35 30 25 21 18 95 15 External clock input frequency f(XIN) Fig. 16.1.6 Relationship between tsu(D) and f(XIN) 7721 Group User's Manual 16-9 APPLICATION 16.1 Memory connection q Timing for writing data to DRAM tw(EL) E RAS CAS td(E-CASL) DRAM write signal W Address output (MA0-MA7) Row address td(E-DLQ/DHQ) Column address Address output and Data I/O V A8/D8-A15/D15 A16/D0-A23/D7 Address Data tDH V This applies when the external data bus has a width of 16 bits (BYTE = "L"). th(E-DLQ/DHQ) : Specifications of the M37721 (The others are specifications of DRAM.) Fig. 16.1.7 Timing for writing data to DRAM Data hold time : tDH tw(EL) - td(E-CASL) + th(E-DLQ/DHQ) Table 16.1.5 lists the calculation formula and value for each parameter in Figure 16.1.7. Figure 16.1.8 shows the relationship between tDH and f(XIN). 16-10 7721 Group User's Manual APPLICATION 16.1 Memory connection Table 16.1.5 Calculation formula and value for each parameter in Figure 16.1.7 (unit : ns) tw(EL) td(E-CASL) Calculation formula and Value 4 ! 10 9 -25 f(XIN) 80 to 115 td(E-DLQ) 35 td(E-DHQ) th(E-DLQ) 1 ! 10 9 -22 th(E-DHQ) f(XIN) Note: When accessing DRAM, Wait is always inserted regardless of the contents of the Wait bit, source's Wait bit, and destination's Wait bit. [ns] 500 486.5 415.5 400 359.5 315.5 Data hold time tDH 300 278.5 248.5 222.5 200.5 181.5 200 165.5 150.5 137.5 125.5 115.5 100 105.5 96.5 88.5 81.5 75.5 0 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 [MHz] External clock input frequency f(XIN) Fig. 16.1.8 Relationship between tDH and f(XIN) 7721 Group User's Manual 16-11 APPLICATION 16.1 Memory connection (3) Precautions on memory connection As described in to below, if specifications of the external memory do not match those of the M37721, some considerations must be incorporated into circuit design: When using an external memory that requires a long access time _ When data is output from an external memory before falling edge of the E signal When using an external memory that outputs data for more than tpzx(E-DLZ/DHZ) after rising edge of _ the E signal When using external memory that requires long access time If the M37721's tsu(DL/DH-E) cannot be satisfied because the external memory requires a long access time, try to carry out the following: q Lower f(XIN). q Select "software Wait is inserted." (Refer to section "3.2 Software Wait.") q Use Ready function. (Refer to section "3.3 Ready function.") Figure 16.1.9 shows an example of using Ready function (no software Wait). Figure 16.1.10 shows an example of using Ready function (software Wait). Ready function is valid___ the internal areas, so that the circuits in Figures 16.1.9 and 16.1.10 ___ for use the chip select signal (CS2) to specify areas where Ready function is valid. In these cases, the CS2 signal is externally generated. 16-12 7721 Group User's Manual APPLICATION 16.1 Memory connection M37721 A8-A23 (D0-D15) V1 V2 Data bus CS1 CS2 Address latch circuit A0-A7 Address decode circuit V1 to V3 : Make sure that the sum of propagation delay time is within 15 ns. V3 to V5 : Make sure that the sum of propagation delay time is within 72 ns. Address bus RDY V5 V3 AC74 E 1 1 AC32 AC32 DQ CK AC04 V4 Validate Ready function only for areas accessed by CS2. Circuit conditions : f(XIN) 15.7 MHz, no software Wait td(E1 1) tc A B Ready request is accepted at A . Termination request for Ready state is accepted at B . A , B : Judgement timing of RDY pin's input level 1 : E ("L" level) stopped by Ready function V The condition satisfy tsu(RDY- 1) 55 ns is tc 63.5 ns. (This applies when AC32's propagation delay time is within 8.5 ns.) Accordingly, when f(XIN) 15.7 MHz, this circuit example satisfies tsu(RDY- 1) 55 ns. E CS2 Q RDY tsu(RDYAC32(tPHL) 1) V Fig. 16.1.9 Example of using Ready function (no software Wait) 7721 Group User's Manual 16-13 APPLICATION 16.1 Memory connection M37721 A8-A23 (D0-D15) Address latch circuit A0-A7 Address decode circuit Data bus CS1 CS2 Address bus V1 to V3 : Make sure that the sum of propagation delay time is within 25 ns. RDY AC32 E AC04 V3 AC32 1D 1Q 1CK V1 CLR 2D 2Q 2CK Validate Ready function only for areas accessed by CS2. AC04 1 AC74 V2 Circuit conditions : f(XIN) 25 MHz, software Wait A 1 B Ready request is accepted at A . Termination request for Ready state is accepted at B . A , B : Judgement timing of RDY pin's input level 1 E : E ("L" level) stopped by software Wait 1Q : E ("L" level) stopped by Ready function 2Q CS2 RDY AC04 + AC74 + AC32's propagation delay time th( tsu(RDY1) 1-RDY) Fig. 16.1.10 Example of using Ready function (software Wait) 16-14 7721 Group User's Manual APPLICATION 16.1 Memory connection _ When data is output from external memory before falling edge of E signal _ Because the external memory outputs data before the falling edge of the E signal, there is a possibility that the tail of address collides with the head of data. In such a case, generate the __ _ external memory read signal (OE) by using E. (Refer to "Figure 16.1.11.") E External memory output enable signal (Read signal) Address output d OE Address Address External memory data output Data ta(OE) Specifications of ten(OE) external memory Note: Make sure that d 0 is satisfied when generating the external memory read signal (OE). Fig. 16.1.11 Example of making data output timing delayed _ When using external memory that outputs data for more than tpzx(E-DLZ/DHZ) after rising edge of E signal Because the external memory outputs data for more than tpzx(E-DLZ/DHZ) after the rising edge of the _ E signal, there is a possibility that the tail of data collides with the head of address. In such a case, try to carry out the following: q Cut the tail of data output from the memory by using, for example, a bus buffer. q Use the Mitsubishi's memory chips that can be connected without a bus buffer. Figures 16.1.12 to 16.1.15 show examples of using bus buffers and the timing charts. Table 16.1.6 lists the Mitsubishi's memory chips that can be connected without a bus buffer. When using one of these memory chips, timing parameters tDF and tdis(OE) listed below are guaranteed. Accordingly, ___ no bus buffer is necessary for the system where the external memory's read signal (OE) goes high _ within tpzx(E-DLZ/DHZ)-tDF (or tdis(OE)) [ns] after the rising edge of the E signal. Table 16.1.6 Mitsubishi's memory chips that can be connected without bus buffers Memory Type tDF/tdis(OE) (Maximum) Flash memory M5M28F101AP, FP, J, VP, RV-85, -10 15 ns M5M28F102AFP, J, VP-85, -10 SRAM (Guaranteed as kit.) M5M5256DP, FP, KP, VP, RV-45LL, -45XL, -55LL, -55XL, (Note) -70LL, -70XL M5M5278DP, J-12 M5M5278DP, FP, J-15, -15L M5M5278DP, FP, J-20, -20L 6 ns 7 ns 8 ns Note: tDF or tdis(OE) listed above is guaranteed when these memory chips are connected with the M37721. When the user wants specifications of these memory chips, add a comment "tDF/tdis(OE) = 15 ns, microcomputer and kit." 7721 Group User's Manual 16-15 APPLICATION 16.1 Memory connection M37721 CNVss BYTE A0-A7 AC573 D Q Address bus LE OE AC573 D ALE Q LE OE AC245 V2 A8/D8-A15/D15 A B Data bus (odd) DIR OC AC245 A16/D0-A23/D7 A B V2 Data bus (even) DIR OC E V3 AC32 AC04 R/W BHE V1 RD WO WE BLE AC32 XIN XOUT V4 Circuit condition: Software Wait 25 MHz V1: Make sure that the propagation delay time is within 20 ns. V2, V3: Make sure that the sum of output disable time in V2 and propagation delay time in V3 is within 20 ns. V4: Make sure that the propagation delay time is within 15 ns. Fig. 16.1.12 Example of using bus buffers (1) 16-16 7721 Group User's Manual APPLICATION 16.1 Memory connection tw(EL) = 135 (min.) E tpzx(E-DLZ/DHZ) = 20 (min.) A8/D8-A15/D15 A16/D0-A23/D7 A AC32(tPHL) OC(AC245), RD Data output A from external memory (AC245) AC245 (tPZH/tPZL) D AC245 (tPHZ/tPLZ) A AC32(tPLH) tw(EL) = 135 (min.) E td(E-DLQ/DHQ) = 35 (max.) A8/D8-A15/D15 A16/D0-A23/D7 A AC32(tPHL) OC(AC245), WO, WE AC245 (tPHL/tPLH) D AC245 (tPHZ/tPLZ) D A AC32(tPLH) Data output B from external memory (AC245) (Unit : ns) Fig. 16.1.13 Timing chart for circuit example using bus buffers (1) 7721 Group User's Manual 16-17 APPLICATION 16.1 Memory connection M37721 CNVss BYTE A0-A7 AC573 D Q Address bus LE OE AC573 D ALE Q LE OE AC245 V2 A8/D8-A15/D15 A B Data bus (odd) DIR OC AC245 A16/D0-A23/D7 A V2 B Data bus (even) DIR OC E These circuits make the occurrence of the write signal's rising edge earlier by 1/2 1, so that the write hold time is extended. 1D 1Q 1T AC04 1 1 2D 2T 2Q AC74 AC04 V1 R/W BHE RD WO WE BLE AC32 XIN XOUT AC32 Circuit condition : Software Wait 25 MHz V1: Make sure that the propagation delay time is within 20 ns. V2: Make sure that the output disable time is within 20 ns. Fig. 16.1.14 Example for using bus buffers (2) (connecting with memory requiring long data hold time for writing) 16-18 7721 Group User's Manual APPLICATION 16.1 Memory connection tw(EL) = 135 (min.) E, OC (AC245) tpzx(E-DLZ/DHZ) = 20 (min.) A8/D8-A15/D15 A16/D0-A23/D7 A AC32(tPHL) RD Data output A from external memory (AC245) AC245 (tPZH/tPZL) D AC245 (tPHZ/tPLZ) A AC32(tPLH) 1 1 tw(EL) = 135(min.) E, OC (AC245) 1Q (AC74) AC04(tPLH) + AC74(tPLH) 2Q (AC74) AC32 ! 2(tPLH) WO, WE 35 (max.) A D AC245 (tPHL/tPLH) D AC245 (tPHZ/tPLZ) A8/D8-A15/D15 A16/D0-A23/D7 Data output B from external memory (AC245) Write hold time (Unit : ns) Fig. 16.1.15 Timing chart for circuit example using bus buffers (2) 7721 Group User's Manual 16-19 APPLICATION 16.1 Memory connection 16.1.3 Example of memory connection Examples of the flash memory, SRAM, and DRAM connection and the timing charts are described as follows. (1) Example of flash memory connection (minimum model) M37721 BYTE A0-A15 D0-D7 BHE BLE E R/W XIN XOUT AC04 V M5M28F101AFP-10 V: Make sure that the propagation delay time is within 25 ns. Address bus A0-A15 Data bus D0-D7 A0-A15 D0-D7 Memory map Open Open WE OE CE 000016 008016 SFR area Internal RAM area 048016 External ROM area (M5M28F101AFP) SFR area 1FC016 200016 25 MHz Circuit condition : Software Wait External ROM area (M5M28F101AFP) FFFF16 Fig. 16.1.16 Example of flash memory connection (minimum model) 16-20 7721 Group User's Manual APPLICATION 16.1 Memory connection AC04(tPHL) AC04(tPLH) tpzx(E-DLZ) = 20 (min.) A th(E-R/W) = 18 (max.) CE ta(OE)V External ROM data output ta(CE)V tsu(DL-E) 30 V : Specifications of M5M28F101AFP-10 The others are specifications of M37721. tDFV = 15 (max.) (Guaranteed as kit.) D Fig. 16.1.17 Timing chart for flash memory connection example (minimum model) 7721 Group User's Manual 16-21 APPLICATION 16.1 Memory connection (2) Example of flash memory and SRAM connection (maximum model) M37721 Address bus A1-A7 BYTE A8-A16 AC573 V1 A8/D8-A15/D15 D E ALE E D8-D15 A16/D0-A18/D2 D Q V1 V2 AC139 A18 A17 A B Y0 Y1 A0-A14 A1-A15 M5M5256DP-70LL Q S A0-A14 A1-A15 S A1-A16 M5M5256DP-70LL CE WE A0-A15 M5M28F102AFP -10 D0-D7 DQ1-DQ8 OE W DQ1-DQ8 OE W D0-D15 D0-D15 OE AC573 Data bus (odd) D3-D7 R/W E BLE BHE XIN XOUT AC32V5 Data bus (even) AC04V3 AC32V4 RD WE Memory map WO 000016 008016 SFR area Internal RAM area External ROM area (M5M28F102AFP) Circuit condition : Software Wait 048016 1FC016 200016 25 MHz SFR area External ROM area (M5M28F102AFP) V1, V2: Make sure that the sum of propagation delay time is within 30 ns. V3, V4: Make sure that the sum of propagation delay time is within 20 ns. V5: Make sure that the propagation delay time is within 5 ns. 1FFFF16 2000016 External RAM area (M5M5256DP ! 2) 2FFFF16 Fig. 16.1.18 Example of flash memory and SRAM connection (maximum model) 16-22 7721 Group User's Manual APPLICATION 16.1 Memory connection td(AL-E) = 15 (min.) tw(EL) = 135 (min.) A1-A7 A8/D8-A15/D15 A16/D0-A18/D2 D3-D7 A A A AC573(tPHL/tPLH)+AC139(tPHL) A tpzx(E-DLZ/DHZ) = 20 (min.) CE, S ta(CE)V, ta(S)VV AC32(tPLH) OE AC32(tPHL) ta(OE)VV V External memory data output tsu(A-DL/DH) = 130 (max.) ta(AD) +AC573(tPHL/tPLH) V VV tDFV/tdis(OE)VV = 15 (max.) (Guaranteed as kit.) D tsu(DL/DH-E) 30 td(AL-E) = 15 (min.) tw(EL) = 135 (min.) A1-A7 A A A8/D8-A15/D15 A16/D0-A18/D2 D3-D7 A td (E-DLQ/DHQ) = 35 (max.) D tsu (D)VV 30 AC573(tPHL)+AC139(tPHL) A th(E-DLQ/DHQ) = 18 (min.) S AC32(tPHL) AC32(tPLH) WE, WO V: Specifications of M5M28F102AFP-10 V V: Specifications of M5M5256DP-70LL The others are specifications of M37721. (Unit : ns) Fig. 16.1.19 Timing chart for example of flash memory and SRAM connection (maximum model) 7721 Group User's Manual 16-23 APPLICATION 16.1 Memory connection (3) Example of DRAM connection (external bus width = 8 bits) M37721 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 RAS CAS R/W E A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 A21/D5 A22/D6 A23/D7 BYTE XIN XOUT AC32 V M5M44800CJ-7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 RAS CAS W OE DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 001FC016 001FFF16 V: Make sure that the propagation delay time is within 80 ns. Memory map SFR area Internal RAM area 00047F16 00008016 00000016 Not used SFR area Not used F0000016 DRAM area Not used F7FFFF16 (M5M44800CJ) FFFFFF16 Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = "00012" 25 MHz Fig. 16.1.20 Example of M5M44800CJ (512K ! 8 bits) connection (external bus width = 8 bits) 16-24 7721 Group User's Manual APPLICATION 16.1 Memory connection E (OE) tw(EL) = 135 (min) RAS tw(RASH) = 60 (min) td(E-RASL) = 30 (max) CAS td(E-CASL) = 77.5 (max) td(RA-RAS) = 5 (min) tw(RASL) = 120 (min) td(RAS-CAS) = 28 (min) tw(CASL) = 92.5 (min) td(CA-CAS) = 5 (min) MA0-MA9 Row address Column address tOEAV = 20 (max) td(E-CA) = 60 (max) A16/D0- A23/D7 tAAV = 35 (max) tRACV = 70 (max) tpzx(E-DLZ) = 20 (min) Address tCLZV = 5 (min) tCACV = 20 (max) Input data tsu(DL-E) 30 tOEZV = 0-20 tw(EL) = 135 (min) E tw(RASH) = 60 (min) RAS tw(RASL) = 120 (min) tw(CASL) = 55 (min) CAS td(E-CASL) = 80-115 td(R/W-E) = 20 (min) R/W AC32(tPHL) tWCSV = 0 (min) W td(RA-RAS) = 5 (min) MA0-MA9 th(RAS-RA) = 18 (min) tWCHV = 15 (min) AC32(tPHL) Row address td(CA-CAS) = 10 (min) Column address th(CAS-CA) = 60 (min) A16/D0- A23/D7 Address Data tDHV = 15 (min) th(E-DLQ) = 18 (min) V : Specifications of M5M44800CJ-7 The others are specifications of M37721. (Unit : ns) Fig. 16.1.21 Timing chart for example of M5M44800CJ (512K ! 8 bits) connection (external bus width = 8 bits) 7721 Group User's Manual 16-25 APPLICATION 16.1 Memory connection (4) Example of DRAM connection (external bus width = 8 bits) M37721 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 RAS CAS R/W E A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 A21/D5 A22/D6 A23/D7 BYTE XIN ALE XOUT AC32 AC573V2 D0 D1 D2 D3 Q4 D4 D5 D6 OE D7 LE 8 V1 M5M417800CJ-7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 RAS CAS W OE D0 D1 D2 D3 D4 D5 D6 D7 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 FFFFFF16 E0000016 001FC016 001FFF16 00000016 00008016 00047F16 V1 : Make sure that the propagation delay time is within 80 ns. V2 : Make sure that the propagation delay time is within 15 ns. Memory map SFR area Internal RAM area Not used SFR area Not used DRAM area (M5M417800CJ) Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = "00102" 25 MHz Fig. 16.1.22 Example of M5M417800CJ (2M ! 8 bits) connection (external bus width = 8 bits) 16-26 7721 Group User's Manual APPLICATION 16.1 Memory connection E (OE) tw(EL) = 135 (min) RAS tw(RASH) = 60 (min) td(E-RASL) = 30 (max) CAS td(E-CASL) = 77.5 (max) td(RA-RAS) = 5 (min) tw(RASL) = 120 (min) td(RAS-CAS) = 28 (min) tw(CASL) = 92.5 (min) td(CA-CAS) = 5 (min) MA0-MA9 Row address Column address tOEAV = 20 (max) tAAV = 35 (max) tRACV = 70 (max) tpzx(E-DLZ) = 20 (min) td(E-CA) = 60 (max) A16/D0- A23/D7 Address tCLZV = 5 (min) td(AH-E) = 15 (min) tCACV = 20 (max) Input data tsu(DL-E) 30 tOEZV = 0-15 A10 (M5M417800AJ) AC573 tASR = 0 (min) tw(EL) = 135 (min) E tw(RASH) = 60 (min) RAS tw(RASL) = 120 (min) CAS td(E-CASL) = 80-115 td(R/W-E) = 20 (min) R/W AC32(tPHL) tWCSV = 0 (min) W td(RA-RAS) = 5 (min) MA0-MA9 th(RAS-RA) = 18 (min) tw(CASL) = 55 (min) AC32(tPHL) tWCHV = 10 (min) Row address td(CA-CAS) = 10 (min) Column address th(CAS-CA) = 60 (min) A16/D0- A23/D7 Address Data tDHV = 15 (min) th(E-DLQ) = 18 (min) V : Specifications of M5M417800CJ-7 The others are specifications of M37721. (Unit : ns) Fig. 16.1.23 Timing chart for example of M5M417800CJ (2M ! 8 bits) connection (external bus width = 8 bits) 7721 Group User's Manual 16-27 APPLICATION 16.1 Memory connection (5) Example of DRAM connection (external bus width = 8 bits) 10 4 M37721 M5M44400CJ-7 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 RAS CAS R/W E A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 A21/D5 A22/D6 A23/D7 XIN XOUT FFFFFF16 AC32 V A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 RAS CAS W OE DQ1 DQ2 DQ3 DQ4 DQ1 DQ2 DQ3 DQ4 F0000016 RAS CAS W E MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 M5M44400CJ-7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 RAS CAS W OE V : Make sure that the propagation delay time is within 80 ns. Memory map 00000016 00008016 00047F16 SFR area Internal RAM area Not used 001FC016 001FFF16 SFR area Not used DRAM area BYTE (M5M44400CJ ! 2) Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = "00012" 25 MHz Fig. 16.1.24 Example of M5M44400CJ (1M ! 4 bits) connection (external bus width = 8 bits) 16-28 7721 Group User's Manual APPLICATION 16.1 Memory connection E (OE) tw(EL) = 135 (min) RAS tw(RASH) = 60 (min) td(E-RASL) = 30 (max) CAS td(E-CASL) = 77.5 (max) td(RA-RAS) = 5 (min) tw(RASL) = 120 (min) td(RAS-CAS) = 28 (min) tw(CASL) = 92.5 (min) td(CA-CAS) = 5 (min) MA0-MA9 Row address Column address tOEAV = 20 (max) tAAV = 35 (max) td(E-CA) = 60 (max) A16/D0- A23/D7 tpzx(E-DLZ) = 20 (min) tRACV = 70 (max) Address tCLZV = 5 (min) tCACV = 20 (max) Input data tsu(DL-E) 30 tOEZV = 0-20 tw(EL) = 135 (min) E tw(RASH) = 60 (min) tw(RASL) = 120 (min) RAS tw(CASL) = 55 (min) CAS td(E-CASL) = 80-115 td(R/W-E) = 20 (min) R/W AC32(tPHL) tWCSV = 0 (min) W td(RA-RAS) = 5 (min) MA0-MA9 th(RAS-RA) = 18 (min) tWCHV = 15 (min) AC32(tPHL) Row address td(CA-CAS) = 10 (min) Column address th(CAS-CA) = 60 (min) A16/D0- A23/D7 Address Data tDHV = 15 (min) th(E-DLQ) = 18 (min) V : Specifications of M5M44400CJ-7 The others are specifications of M37721. (Unit : ns) Fig. 16.1.25 Timing chart for example of M5M44400CJ (1M ! 4 bits) connection (external bus width = 8 bits) 7721 Group User's Manual 16-29 APPLICATION 16.1 Memory connection (6) Example of DRAM connection (external bus width = 16 bits) M37721 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 RAS CAS BLE BHE ST0 ST1 E R/W A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 A21/D5 A22/D6 A23/D7 A8/D8 A9/D9 A10/D10 A11/D11 A12/D12 A13/D13 A14/D14 A15/D15 BYTE XIN XOUT AC32 V1 M5M418160CJ-7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 RAS AC157 1A 1B 2A 2B V2 V1 : Make sure that the propagation delay time is within 20 ns. V2 : Make sure that the propagation delay time is within 7.5 ns. Memory map 00000016 00008016 SFR area Internal RAM area Not used 1Y 2Y LCAS UCAS 00047F16 001FC016 001FFF16 SELECT ST OE W SFR area Not used DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 E0000016 DRAM area (M5M418160CJ) FFFFFF16 25 MHz Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = "0010 2" Fig. 16.1.26 Example of M5M418160CJ (1M ! 16 bits) connection (external bus width = 16 bits) 16-30 7721 Group User's Manual APPLICATION 16.1 Memory connection E (OE) tw(EL) = 135 (min) RAS tw(RASH) = 60 (min) td(E-RASL) = 30 (max) CAS td(E-CASL) = 77.5 (max) td(RA-RAS) = 5 (min) tw(RASL) = 120 (min) td(RAS-CAS) = 28 (min) tw(CASL) = 92.5 (min) td(CA-CAS) = 5 (min) MA0-MA9 Row address tOEAV td(E-CA) = 60 (max) Column address = 20 (max) tpzx(E-DLZ/DHZ) = 20 (min) tAAV = 35 (max) tRACV = 70 (max) A16/D0-A23/D7, A8/D8-A15/D15 Address tCLZV = 5 (min) + AC157 (tPHL) td(BLE/BHE-E) = 20 (min) tCACV = 20 (max) + AC157 (tPHL) Input data tsu(DL/DH-E) 30 tOEZV = 0-15 BLE/BHE E tw(RASH) = 60 (min) tw(RASL) = 120 (min) RAS tw(EL) = 135 (min) tw(CASL) = 55 (min) CAS td(E-CASL) = 80-115 td(R/W-E) = 20 (min) R/W AC32(tPHL) tWCSV = 0 (min) W td(RA-RAS) = 5 (min) MA0-MA9 th(RAS-RA) = 18 (min) tWCHV = 10 (min) AC32(tPHL) Row Address td(CA-CAS) = 10 (min) Column address th(CAS-CA) = 60 (min) A16/D0-A23/D7, A8/D8-A15/D15 Address td(BLE/BHE-E) = 20 (min) Data tDHV = 15 (min) + AC157(tPHL) th(E-DLQ/DHQ) = 18 (min) BLE/BHE V : Specifications of M5M418160CJ-7 The others are specifications of M37721. (Unit : ns) Fig. 16.1.27 Timing chart for example of M5M418160CJ (1M ! 16 bits) connection (external bus width = 16 bits) 7721 Group User's Manual 16-31 APPLICATION 16.1 Memory connection (7) Example of DRAM connection (external bus width = 16 bits) M37721 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 M5M44170CJ-7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 RAS CAS OE WL R/W BLE BHE A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 A21/D5 A22/D6 A23/D7 AC32 V1 D0 D1 D2 D3 D4 D5 D6 D7 Q1 Q2 WH D0 D1 D2 D3 D4 D5 D6 D7 V2 V1 : Make sure that the propagation delay time is within 40 ns. V2 : Make sure that the propagation delay time is within 15 ns. RAS CAS E 00000016 LW 00008016 UW DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 00047F16 Memory map SFR area Internal RAM area Not used 001FC016 001FFF16 SFR area OE LE AC573 8 Not used BYTE ALE A8/D8 A9/D9 A10/D10 A11/D11 A12/D12 A13/D13 A14/D14 A15/D15 XOUT DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 F0000016 F7FFFF16 DRAM area (M5M44170CJ) Not used FFFFFF16 XIN 25 MHz Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = "00012" Fig. 16.1.28 Example of M5M44170CJ (256K ! 16 bits) connection (external bus width = 16 bits) 16-32 7721 Group User's Manual APPLICATION 16.1 Memory connection E (OE) tw(EL) = 135 (min) RAS tw(RASH) = 60 (min) td(E-RASL) = 30 (max) CAS td(E-CASL) = 77.5 (max) td(RA-RAS) = 5 (min) tw(RASL) = 120 (min) td(RAS-CAS) = 28 (min) tw(CASL) = 92.5 (min) td(CA-CAS) = 5 (min) MA0-MA7 Row address Column address tOEAV = 20 (max) td(E-CA) = 60 (max) A16/D0-A23/D7, A8/D8-A15/D15 tAAV = 35 (max) tRACV = 70 (max) tpzx(E-DLZ/DHZ) = 20 (min) Address tCLZV = 5 (min) td(AH-E) = 15 (min) tCACV = 20 (max) Input data tsu(DL/DH-E) 30 tOEZV = 0-20 A8, A9 (M5M44170AJ) AC573 tASR = 0 (min) tw(EL) = 135 (min) E tw(RASH) = 60 (min) tw(RASL) = 120 (min) RAS tw(CASL) = 55 (min) CAS td(E-CASL) = 80-115 td(R/W-E) = 20 (min) R/W AC32(tPHL) ! 2 tWCSV = 0 (min) WL/WH td(RA-RAS) = 5 (min) MA0-MA9 th(RAS-RA) = 18 (min) tWCHV = 15 (min) AC32(tPHL) ! 2 Row address td(CA-CAS) = 10 (min) Column address th(CAS-CA) = 60 (min) A16/D0-A23/D7, A8/D8-A15/D15 Address td(BLE/BHE-E) = 20 (min) Data tDHV = 15 (min) th(E-DLQ/DHQ) = 18 (min) BLE/BHE V : Specification of M5M44170CJ-7 The others are specifications of M37721. (Unit : ns) Fig. 16.1.29 Timing chart for example of M5M44170CJ (256K ! 16 bits) connection (external bus width = 16 bits) 7721 Group User's Manual 16-33 APPLICATION 16.1 Memory connection (8) Example of DRAM connection (external bus width = 16 bits) 10 4 M37721 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 RAS CAS E WL R/W BLE BHE AC32 V1 A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 A21/D5 A22/D6 A23/D7 ALE A8/D8 A9/D9 A10/D10 A11/D11 A12/D12 BYTE XIN A13/D13 A14/D14 A15/D15 XOUT AC573 D0 D1 D2 D3 Q4 D4 D5 D6 OE D7 LE V2 M5M417800CJ-7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 RAS CAS OE W M5M417800CJ-7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 RAS CAS OE W V1 : Make sure that the propagation delay time is within 40 ns. V2 : Make sure that the propagation delay time is within 15 ns. Memory map 00000016 00008016 00047F16 WH SFR area Internal RAM area Not used 001FC016 D0 D1 D2 D3 D4 D5 D6 D7 8 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 D8 D9 D10 D11 D12 D13 D14 D15 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 001FFF16 SFR area Not used E0000016 DRAM area (M5M417800CJ ! 2) FFFFFF16 Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = "00102" 25 MHz Fig. 16.1.30 Example of M5M417800CJ (2M ! 8 bits) connection (external bus width = 16 bits) 16-34 7721 Group User's Manual APPLICATION 16.1 Memory connection E (OE) tw(EL) = 135 (min) RAS tw(RASH) = 60 (min) td(E-RASL) = 30 (max) CAS td(E-CASL) = 77.5 (max) td(RA-RAS) = 5 (min) tw(RASL) = 120 (min) td(RAS-CAS) = 28 (min) tw(CASL) = 92.5 (min) td(CA-CAS) = 5 (min) MA0-MA9 Row address Column address tOEAV = 20 (max) tAAV = 35 (max) td(E-CA) = 60 (max) A16/D0-A23/D7, A8/D8-A15/D15 tRACV = 70 (max) tpzx(E-DLZ/DHZ) = 20 (min) Address td(AH-E) = 15 (min) tCLZV = 5 (min) tCACV = 20 (max) Input data tsu(DL/DH-E) 30 tOEZV = 0-15 A10 (M5M417800AJ) AC573 tASR = 0 (min) tw(EL) = 135 (min) E tw(RASH) = 60 (min) tw(RASL) = 120 (min) RAS tw(CASL) = 55 (min) CAS td(E-CASL) = 80-115 td(R/W-E) = 20 (min) R/W AC32(tPHL) tWCSV = 0 (min) W td(RA-RAS) = 5 (min) MA0-MA9 th(RAS-RA) = 18 (min) tWCHV = 10 (min) AC32(tPHL) Row address td(CA-CAS) = 10 (min) Column address th(CAS-CA) = 60 (min) A16/D0-A23/D7, A8/D8-A15/D15 Address Data tDHV = 15 (min) th(E-DLQ/DHQ) = 18 (min) V : Specifications of M5M417800CJ-7 The others are specifications of M37721. (Unit : ns) Fig. 16.1.31 Timing chart for example of M5M417800CJ (2M ! 8 bits) connection (external bus width = 16 bits) 7721 Group User's Manual 16-35 APPLICATION 16.1 Memory connection (9) Example of DRAM connection (external bus width = 16 bits) M5M44400CJ-7 M37721 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 RAS CAS OE W DQ1 DQ2 DQ3 DQ4 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 RAS CAS OE W DQ1 DQ2 DQ3 DQ4 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 RAS CAS OE W DQ1 DQ2 DQ3 DQ4 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 RAS CAS OE W DQ1 DQ2 DQ3 DQ4 V : Make sure that the propagation delay time is within 40 ns. RAS CAS E R/W BLE BHE A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 A21/D5 A22/D6 A23/D7 A8/D8 A9/D9 A10/D10 A11/D11 A12/D12 A13/D13 BYTE XIN A14/D14 A15/D15 XOUT Memory map 00000016 00008016 00047F16 SFR area Internal RAM area Not used WL WH V AC32 001FC016 001FFF16 SFR area Not used E0000016 DRAM area (M5M4400CJ ! 4) A8/D8 A9/D9 A10/D10 A11/D11 25 MHz Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = "0010 2" Fig. 16.1.32 Example of M5M44400CJ (1M ! 4 bits) connection (external bus width = 16 bits) 16-36 7721 Group User's Manual A12/D12 A13/D13 A14/D14 A15/D15 FFFFFF16 A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 A21/D5 A22/D6 A23/D7 APPLICATION 16.1 Memory connection E (OE) tw(EL) = 135 (min) RAS tw(RASH) = 60 (min) td(E-RASL) = 30 (max) CAS td(E-CASL) = 77.5 (max) td(RA-RAS) = 5 (min) tw(RASL) = 120 (min) td(RAS-CAS) = 28 (min) tw(CASL) = 92.5 (min) td(CA-CAS) = 5 (min) MA0-MA9 Row address Column address tOEAV = 20 (max) tAAV = 35 (max) td(E-CA) = 60 (max) A16/D0-A23/D7, A8/D8-A15/D15 tRACV = 70 (max) tpzx(E-DLZ/DHZ) = 20 (min) Address tCLZV = 5 (min) tCACV = 20 (max) Input data tsu(DL/DH-E) 30 tOEZV = 0-20 tw(EL) = 135 (min) E tw(RASH) = 60 (min) tw(RASL) = 120 (min) RAS tw(CASL) = 55 (min) CAS td(E-CASL) = 80-115 td(R/W-E) = 20 (min) R/W AC32(tPHL) ! 2 tWCSV = 0 (min) WL/WH td(RA-RAS) = 5 (min) MA0-MA9 th(RAS-RA) = 18 (min) tWCHV = 10 (min) AC32(tPHL) ! 2 Row address td(CA-CAS) = 10 (min) Column address th(CAS-CA) = 60 (min) A16/D0-A23/D7, A8/D8-A15/D15 Address td(BLE/BHE-E) = 20 (min) Data tDHV = 15 (min) th(E-DLQ/DHQ) = 18 (min) BLE/BHE V : Specifications of M5M44400CJ-7 The others are specifications of M37721. (Unit : ns) Fig. 16.1.33 Timing chart for example of M5M44400CJ (1M ! 4 bits) connection (external bus width = 16 bits) 7721 Group User's Manual 16-37 APPLICATION 16.1 Memory connection (10) Example of DRAM connection (external bus width = 16 bits) M37721 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 RAS CAS BLE BHE ST0 ST1 1A 1B 2A 2B 2Y SELECT ST E R/W A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 A21/D5 A22/D6 A23/D7 A8/D8 A9/D9 A10/D10 A11/D11 A12/D12 A13/D13 A14/D14 A15/D15 XOUT AC32 V1 1Y M5M44260CJ-7 A0 A1 A2 A3 A4 A5 A6 A7 A8 RAS V1 : Make sure that the propagation delay time is within 20 ns. V2 : Make sure that the propagation delay time is within 7.5 ns. AC157V2 LCAS UCAS 00000016 00008016 OE W DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 001FC016 001FFF16 00047F16 Memory map SFR area Internal RAM area Not used SFR area Not used F0000016 F7FFFF16 BYTE DRAM area (M5M44260CJ) XIN Not used FFFFFF16 25 MHz Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = "00012" Fig. 16.1.34 Example of M5M44260CJ (256K ! 16 bits) connection (external bus width = 16 bits) 16-38 7721 Group User's Manual APPLICATION 16.1 Memory connection E (OE) tw(EL) = 135 (min) RAS tw(RASH) = 60 (min) td(E-RASL) = 30 (max) CAS td(E-CASL) = 77.5 (max) td(RA-RAS) = 5 (min) tw(RASL) = 120 (min) td(RAS-CAS) = 28 (min) tw(CASL) = 92.5 (min) td(CA-CAS) = 5 (min) MA0-MA8 Row address Column address tOEAV = 20 (max) tAAV = 35 (max) tRACV = 70 (max) td(E-CA) = 60 (max) A16/D0-A23/D7, A8/D8-A15/D15 tpzx(E-DLZ/DHZ) = 20 (min) Address td(BLE/BHE-E) = 20 (min) tCLZV = 5 (min) + AC157 (tPHL) tCACV = 20 (max) + AC157 (tPHL) Input data tsu(DL/DH-E) 30 tOEZV = 0-20 BLE/BHE E tw(RASH) = 60 (min) tw(RASL) = 120 (min) RAS tw(EL) = 135 (min) tw(CASL) = 55 (min) CAS td(E-CASL) = 80-115 td(R/W-E) = 20 (min) R/W AC32(tPHL) tWCSV = 0 (min) W td(RA-RAS) = 5 (min) MA0-MA8 th(RAS-RA) = 18 (min) tWCHV = 15 (min) AC32(tPHL) Row Address td(CA-CAS) = 10 (min) Column address th(CAS-CA) = 60 (min) A16/D0-A23/D7, A8/D8-A15/D15 Address td(BLE/BHE-E) = 20 (min) Data tDHV = 15 (min) + AC157(tPHL) th(E-DLQ/DHQ) = 18 (min) BLE/BHE V : Specifications of M5M44260CJ-7 The others are specification of M37721. (Unit : ns) Fig. 16.1.35 Timing chart for example of M5M44260CJ (256K ! 16 bits) connection (external bus width = 16 bits) 7721 Group User's Manual 16-39 APPLICATION 16.1 Memory connection 16.1.4 Example of I/O expansion (1) Example of port expansion circuit using M66010FP Figure 16.1.36 shows an example of a port expansion circuit using the M66010FP. Make sure that the frequency of Serial I/O transfer clock must be 1.923 MHz or less. About Serial I/O control in this expansion example is described below. In this example, 8-bit data transmission/reception is performed 3 times by using UART0, so that 24bit port expansion is realized. Setting of UART0 is described below: q Clock synchronous serial I/O mode: Transmission/Reception enable state q Internal clock is selected. Transfer clock frequency is 1.66 MHz. q LSB first The control procedure is described below: Output "L" level from port P45. (Expanded I/O ports of the M66010FP enter a floating state by this signal. ) Output "H" level from port P45. Output "L" level from port P44. Transmit/Receive 24-bit data by using UART0. Output "H" level from port P44. Figure 16.1.37 shows the serial transfer timing between the M37721 and the M66010FP. 16-40 7721 Group User's Manual APPLICATION 16.1 Memory connection M37721 TxD0 RxD0 BYTE CLK0 P44 P45 RTS0 A0-A7 A8/D8-A15/D15 A16/D0-A23/D7 ALE E 1 M66010FP DI DO CLK CS S D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 Open Vcc Expanded input ports GND R/W BHE BLE XIN XOUT 25 MHz Circuit conditions: *UART0 used in clock synchronous serial I/O mode *Internal clock selected f2 *Frequency of transfer clock = = 1.5625 MHz 2 (3 + 1) Fig. 16.1.36 Example of port expansion circuit using M66010FP 7721 Group User's Manual 16-41 16-42 P45 S APPLICATION Expanded I/O ports are released from floating state. Data of shift register 2 is output to expanded I/O ports. 16.1 Memory connection P44 CS Data of expanded I/O ports is output to shift register 1. Serial data is input to shift register 2. DO2 DO5 DO7 DO20 DO8 DO6 DO3 DO4 DO21 DO22 DO23 DO24 CLK0 CLK TXD0 DI DO1 Data of shift register 1 is output in serial. DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI20 DI21 DI22 DI23 DI24 RXD0 DO DI1 Fig. 16.1.37 Serial transfer timing between M37721 and M66010FP DO1 DO2 DO24 7721 Group User's Manual Expanded I/O port D1 DI1 Expanded I/O port D2 DI2 to Expanded I/O port D24 DI24 V Output structure of expanded I/O ports is N-channel open-drain output. : M37721's pin name The others are M66010FP's pin's names or operations. APPLICATION 16.2 Examples of using DMA controller 16.2 Examples of using DMA controller 16.2.1 Example of Centronics interface configuration The following is an example of Centronics interface configurated by using DMA0, Timers A2 and A3. (1) Specifications *Octal latch's contents are transferred to the data buffer (RAM) by using DMA0. The trigger is the ____ STB signal. (Refer to "Figure 16.2.1.") ____ *"L" level width of the ACK_________ signal is generated by using Timer A2; one-shot pulse mode; the trigger is the rising edge of the DMAACK0 signal. (Refer to "Figure 16.2.2.") ____ *Timer A3 generates the time from when the ACK signal rises until the BUSY signal falls; one-shot _________ pulse mode; the trigger is the rising edge of the DMAACK0 signal. (Refer to "Figure 16.2.2.") *P43 is used for BUSY signal generation. When outputting "H" level, the next transfer can wait. In that case, the contents of the preceding transfer are hold in the octal latch. *When the data buffer is filled (in other words, DMA transfer is completed), a DMA interrupt occurs. 7721 Group User's Manual 16-43 APPLICATION 16.2 Examples of using DMA controller M37721 Octal latch Data AC574 OC CS RD STB D-F/F BUSY QS DT TA3OUT (one-shot output) TA3IN DMAACK0 TA2IN P43 ACK TA2OUT (one-shot output) XIN XOUT 25 MHz DMAREQ0 T Data bus Fig. 16.2.1 Example of Centronics interface configuration DMAACK0 TA2OUT T3 TA3OUT ACK BUSY T2 T2 : Timer A2's set time T3 : Timer A3's set time ____ Fig. 16.2.2 Relationship between ACK and BUSY 16-44 7721 Group User's Manual APPLICATION 16.2 Examples of using DMA controller (2) Initial setting example for relevant register b7 b0 1 Port P4 register (Address A16) P43 output : H level b7 b0 1 Port P5 register (Address B16) TA3OUT output : H level (D-F/F initialized) b7 b0 1 Port P4 direction register (Address C16) P43 : Output mode b7 b0 0 1 0 Port P5 direction register (Address D16) TA2IN pin : Input mode TA3OUT pin : Output mode (D-F/F initialized) TA3IN pin : Input mode b7 b0 0 Port P9 direction register (Address 1516) DMAREQ0 pin : Input mode b7 b0 0 1 0 0 0 10 1 DMA0 mode register L (Address 1FCC16) Transfer unit : 8 bits 2-bus cycle transfer Cycle-steal transfer mode Transfer source address direction : Fixed Transfer destination address direction : Forward b7 b0 0 0 0 0 0 0 ! 0 DMA0 mode register H (Address 1FCD16) Transfer source Wait Transfer destination Wait Single transfer mode ! : It may be "0" or "1." Fig. 16.2.3 Initial setting example for relevant register (1) 7721 Group User's Manual 16-45 APPLICATION 16.2 Examples of using DMA controller b23 b16 b15 b8 b7 b0 Source address register 0 (Addresses 1FC216 to 1FC016) Octal latch's address b23 b16 b15 b8 b7 b0 Destination address register 0 (Addresses 1FC616 to 1FC416) Data buffer's start address b23 b16 b15 b8 b7 b0 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) Data buffer size (unit : byte) b7 b0 0 1 1 11 0 Timer A2 mode register (Address 5816) One-shot pulse mode Trigger : Rising edge of TA2IN pin's input signal Count source b7 b0 0 1 1 11 0 Timer A3 mode register (Address 5916) One-shot pulse mode Trigger : Rising edge of TA3IN pin's input signal Count source b15 b8 b7 b0 Timer A2 register (Addresses 4B16, 4A16) ACK signal's "L" level time (T2 in Figure 16.2.2) b15 b8 b7 b0 Timer A3 register (Addresses 4D16, 4C16) Period from falling edge of ACK signal until falling edge of BUSY signal (T3 in Figure 16.2.2) Fig. 16.2.4 Initial setting example for relevant register (2) 16-46 7721 Group User's Manual APPLICATION 16.2 Examples of using DMA controller b7 b0 1 0 0 00 1 DMA0 control register (Address 1FCE16) DMA request source : External source (DMAREQ0) Edge sense selected DMAACK0 pin : Valid b7 b0 0 DMA0 interrupt control register (Address 6C16) Interrupt priority level : any of "0012" to "1112" b7 b0 1 1 Count start register (Address 4016) Timer A2 count start Timer A3 count start b7 b0 0 DMAC control register L (Address 6816) DMA0 request flag is set to "0." b7 b0 1 DMAC control register H (Address 6916) DMA0 enabled b7 b0 0 Port P4 register (Address A16) P43 output : L level Fig. 16.2.5 Initial setting example for relevant register (3) 7721 Group User's Manual 16-47 APPLICATION 16.2 Examples of using DMA controller 16.2.2 Example of stepping motor control The following is an example where the slow-up or slow-down control for the stepping motor is performed by using DMA1, DMA2, and RTP0. (1) Specifications *DMA1 transfers the stepping motor's phase output data from the phase output data table to the RTP0 pulse output data register. (Refer to "Figure 16.2.6" and "Table 16.2.1.") *DMA2 transfers the step time for slow up or slow down from the timer A0 set value data table to the timer A0 register. (Refer to "Figure 16.2.6.") After slow up or slow down is completed, a DMA2 interrupt occurs. *Phase output is performed by RTP0; pulse output mode 0 (Refer to "Figures 16.2.6 and 16.2.7.") *After slow up or slow down is completed, the motor operates with the definite rate. M37721 ROM M Stepping motor Motor driver Phase output data table RTP0 DMAC1 Bus DMAC2 Timer A0 Timer A0 set value data table Fig. 16.2.6 Example of stepping motor control 16-48 7721 Group User's Manual APPLICATION 16.2 Examples of using DMA controller Table 16.2.1 Example of phase output data table 1-2 phase 2-2 phase 0 1 2 3 4 5 6 7 0011 1001 1100 0110 0011 1001 1100 0110 0011 0001 1001 1000 1100 0100 0110 0010 Phase Step 0 1 2 3 4 5 6 7 RTP03 2-2 phase 1-2 phase RTP02 RTP01 RTP00 RTP03 RTP02 RTP01 RTP00 Fig. 16.2.7 Example of phase output 7721 Group User's Manual 16-49 APPLICATION 16.2 Examples of using DMA controller (2) Initial setting example for relevant register b7 b0 0 0 0 10 1 DMA1 mode register L (Address 1FDC16) Transfer unit : 8 bits 2-bus cycle transfer Cycle-steal transfer mode Transfer source address direction : At regular turning ; "012" (Forward) At reverse turning ; "102" (Backward) Transfer destination address direction : Fixed b7 b0 0 1 1 0 0 0!0 DMA1 mode register H (Address 1FDD16) Transfer source Wait No transfer destination Wait Repeat transfer mode b23 b16 b15 b8 b7 b0 Source address register 1 (Addresses 1FD216 to 1FD016) Phase output data table's start address b23 b16 b15 b8 b7 b0 0016 0016 1A16 Destination address register 1 (Addresses 1FD616 to 1FD416) Pulse output data register 0's address b23 b16 b15 b8 b7 b0 Transfer counter register 1 (Addresses 1FDA16 to 1FD816) Phase output data table's data number b7 b0 00 0 0 1 1 DMA1 control register (Address 1FDE16) DMA request source : Timer A0 DMAACK1 pin : Invalid b7 b0 0 0 0 DMA1 interrupt control register (Address 6D16) Interrupt disabled ! : It may be "0" or "1." Fig. 16.2.8 Initial setting example for relevant register (1) 16-50 7721 Group User's Manual APPLICATION 16.2 Examples of using DMA controller b7 b0 0 0 0 10 0 DMA2 mode register L (Address 1FEC16) Transfer unit : 16 bits 2-bus cycle transfer Cycle-steal transfer mode Transfer source address direction : At slow up; "012" (Forward) At slow down; "102" (Backward) Transfer destination address direction : Fixed b7 b0 0 0 1 0 0 0 ! 0 DMA2 mode register H (Address 1FED16) Transfer source Wait No transfer destination Wait Single transfer mode b23 b16 b15 b8 b7 b0 Source address register 2 (Addresses 1FE216 to 1FE016) Timer A0 set value data table's start address b23 b16 b15 b8 b7 b0 0016 0016 4616 Destination address register 2 (Addresses 1FE616 to 1FE416) Timer A0 register's address b23 b16 b15 b8 b7 b0 Transfer counter register 2 (Addresses 1FEA16 to 1FE816) Data number of Timer A0 set value data table b7 b0 00 0 0 1 1 DMA2 control register (Address 1FEE16) DMA request source : Timer A0 DMAACK2 pin : Invalid b7 b0 0 DMA2 interrupt control register (Address 6E16) Interrupt priority level : any of "0012" to "1112" ! : It may be "0" or "1." Fig. 16.2.9 Initial setting example for relevant register (2) 7721 Group User's Manual 16-51 APPLICATION 16.2 Examples of using DMA controller b7 b0 1 11 1 Port P6 register (Address E16) RTP00/P60-RTP03/P63 initial output : H level b7 b0 1 11 1 Port P6 direction register (Address 1016) RTP00/P60-RTP03/P63 pin : Output mode b7 b0 Pulse output data register 0 (Address 1A16) First phase output data b7 b0 0 0!0 0 0 TImer A0 mode register (Address 5616) Count source b7 b0 0 0 1 Real-time output control register (Address 6216) RTP0 Pulse mode 0 b15 b8 b7 b0 Timer A0 register (Addresses 4716, 4616) First step time b7 b0 1 Count start register (Address 4016) Timer A0 count start b7 b0 0 0 DMAC control register L (Address 6816) DMA1 request bit DMA2 request bit are set to "0." b7 b0 1 1 DMAC control register H (Address 6916) DMA1 enabled DMA2 enabled ! : It may be "0" or "1." Fig. 16.2.10 Initial setting example for relevant register (3) 16-52 7721 Group User's Manual APPLICATION 16.2 Examples of using DMA controller 16.2.3 Example of dynamic lighting for LED The following is an example of dynamic lighting for LED by using DMA3 and Timer B0. (1) Specifications *The eight 7-segment LEDs are lighted up; port P6 outputs the segment data; port P7 outputs the digit data. (Refer to "Figure 16.2.11.") *The display data and the segment data are transferred from the data buffer to the port P6 and P7 registers by DMA3. *Digit switch interval is generated by Timer B0. *16 bytes of RAM are used as the data buffer. 1-digit display data consists of 2 bytes; the digit data is placed in the high-order byte; the segment data is placed in the low-order byte. (Refer to "Table 16.2.2.") When the digit data and segment data are "0," the LED is lighted up (ON): when they are "1," the light goes out (OFF). Assuming that the segment pattern is generated by another processing. M37721 7-segment LED ! 8 Data buffer P67 LED driver P60 P77 LED driver P70 Fig. 16.2.11 Example of dynamic lighting for LED Table 16.2.2 Data buffer Digit data 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 Notes 1: This applies in the following: *when the digit data is "0," the light goes out. *when the digit data is "1," the LED is lighted up. 2: Assuming that the segment pattern is generated by another processing. 7721 Group User's Manual Data buffer Segment pattern Segment pattern of the contents to be displayed in each digit 16-53 APPLICATION 16.2 Examples of using DMA controller b7 b0 0 0 0 1 0 10 0 DMA3 mode register L (Address 1FFC16) Transfer unit : 16 bits 2-bus cycle transfer Cycle-steal transfer mode Transfer source address direction : Forward Transfer destination address direction : Fixed b7 b0 0 1 1 1 0 0 !0 DMA3 mode register H (Address 1FFD16) No transfer source Wait No transfer destination Wait Repeat transfer mode b23 b16 b15 b8 b7 b0 Source address register 3 (Addresses 1FF216 to 1FF016) Data buffer's start address b23 b16 b15 b8 b7 b0 0016 0016 0E16 Destination address register 3 (Addresses 1FF616 to 1FF416) Port P6, P7 register's address b23 b16 b15 b8 b7 b0 0016 0016 1016 Transfer counter register 3 (Addresses 1FFA16 to 1FF816) Data number (unit : byte) b7 b0 00 1 0 0 0 DMA3 control register (Address 1FFE16) DMA request source : Timer B0 DMAACK3 pin : Invalid b7 b0 0 0 0 DMA3 interrupt control register (Address 6F16) Interrupt disabled ! : It may be "0" or "1." Fig. 16.2.12 Initial setting example for relevant register (1) 16-54 7721 Group User's Manual APPLICATION 16.2 Examples of using DMA controller b7 b0 0 0 0 00 00 0 Port P6 register (Address E16) Output : L level (Lights go out.) b7 b0 0 0 0 00 00 0 Port P7 register (Address F16) Output : L level (All digits OFF) b7 b0 1 1 1 11 11 1 Port P6 direction register (Address 1016) Output mode b7 b0 1 1 1 11 11 1 Port P7 direction register (Address 1116) Output mode b15 b8 b7 b0 Timer B0 register (Addresses 5116, 5016) Digit switch interval b7 b0 ! !!0 0 Timer B0 mode register (Address 5B16) Timer mode Count source b7 b0 0 0 0 Timer B0 interrupt control register (Address 7A16) Interrupt disabled b7 b0 1 Count start register (Address 4016) Timer B0 count started b7 b0 0 DMAC control register L (Address 6816) DMA3 request bit : "0" b7 b0 1 DMAC control register H (Address 6916) DMA3 enabled ! : It may be "0" or "1." Fig. 16.2.13 Initial setting example for relevant register (2) 7721 Group User's Manual 16-55 APPLICATION 16.3 Comparison of sample program execution rate 16.3 Comparison of sample program execution rate Sample program execution rates are compared in this paragraph. The execution time ratio depends on the program or the usage conditions. 16.3.1 Differences depending on data bus width and software Wait Internal areas are always accessed with data bus of which width is 16 bits and no software Wait. In the external areas, the external data bus width and software Wait are selectable. Table 16.3.1 lists the sample program (Refer to "Figure 16.3.1.") execution time ratio depending on these selection and usable memory areas. Table 16.3.1 Sample program execution time ratio (external data bus width and software Wait) Memory area External data bus Sample program execution time ratio Software Wait Sample A Sample B ROM width (unit : bit) RAM None 1.00 1.00 16 Inserted 1.17 1.10 External Internal None 1.19 1.08 8 Inserted 1.67 1.46 None 1.00 1.00 16 Inserted 1.25 1.17 Internal External None 1.19 1.13 8 Inserted 1.78 1.65 V Calculated value 0.92 0.90 Calculated value V : The value is calculated from the shortest execution cycle number of each instruction described in "7700 Family Software Manual." 16-56 7721 Group User's Manual APPLICATION 16.3 Comparison of sample program execution rate Sample A SEP LDA.B STA STA STA LDX.B ITALIC: LDA TAY AND.B STA TYA AND.B ORA STA TYA AND.B ORA STA TYA AND.B ORA STA DEX BPL M,X A,#0 A,DEST+64 A,DEST+65 A,DEST+66 #63 A,SOUR,X A,#00000011B A,DEST,X A,#00001100B A,DEST+1,X A,DEST+1,X A,#00110000B A,DEST+2,X A,DEST+2,X A,#11000000B A,DEST+3,X A,DEST+3,X ITALIC Sample B SEP CLM .DATA .INDEX LDY LOOP0: LDX LOOP1: ASL SEM .DATA ROL ROL CLM .DATA ROR DEX DEX DEX BNE STA SEM .DATA STA CLM .DATA DEY DEY DEY BNE X 16 8 #69 #69 SOUR,X 8 SOUR+2,X B 16 A LOOP1 A,DEST,Y 8 B,DEST+2,Y 16 LOOP0 V SOUR, DEST : Work area (Direct page area : Access this area by using the following modes.) *Direct addressing mode *Direct Indexed X addressing mode *Absolute Indexed Y addressing mode Fig. 16.3.1 Sample program list 7721 Group User's Manual 16-57 APPLICATION 16.3 Comparison of sample program execution rate 16.3.2 Comparison between software Wait (f(XIN) = 20 MHz) and software Wait + Ready (f(XIN) = 25 MHz) Figure 16.3.3 shows the execution time ratio when sample programs in Figure 16.3.1 are executed on the two conditions in Table 16.3.2. Figure 16.3.2 shows the memory assignment at execution rate comparison. The execution time ratio depends on the program or the usage conditions. Table 16.3.2 Comparison conditions Item Processor mode f(XIN) External data bus width Software Wait Ready Program area Work area Condition Microprocessor mode 20 MHz 16 bits Inserted Invalid External EPROM Internal or External SRAM Condition Microprocessor mode 25 MHz 16 bits Inserted Valid only for external EPROM area External EPROM Internal or External SRAM M37721 memory map SFR area Internal SRAM Specify either area as work area Area where software Wait is valid External SRAM Program area External EPROM Condition Ready valid area Insert Wait which is equivalent to 2 cycles of at access (Software Wait included) Fig. 16.3.2 Memory assignment at execution rate comparison 16-58 7721 Group User's Manual APPLICATION 16.3 Comparison of sample program execution rate Figure 16.3.3 shows that there is almost no difference between conditions and about the execution time. The bus buffers become unnecessary when using the specified memory. (Refer to "Table 16.1.6.") Considering this, the case where software Wait is inserted with f(XIN) = 20 MHz (condition ) is superior in the cost performance. Sample A excution time ratio 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 Work area = Internal RAM Work area = External RAM 1.00 1.04 1.10 1.00 1.01 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 Sample B excution time ratio 1.00 1.05 1.00 1.03 Work area = Internal RAM Work area = External RAM : Condition : Condition Fig. 16.3.3 Execution time ratio 7721 Group User's Manual 16-59 APPLICATION 16.3 Comparison of sample program execution rate MEMORANDUM 16-60 7721 Group User's Manual APPENDIX Appendix 1. Memory assignment of 7721 Group Appendix 2. Memory assignment in SFR area Appendix 3. Control registers Appendix 4. Package outline Appendix 5. E x a m p l e s o f h a n d l i n g unused pins Appendix 6. Machine instructions Appendix 7. Hexadecimal instruction code table Appendix 8. Countermeasure against noise Appendix 9. 7721 Group Q & A Appendix 10. Differences between 7721 Group and 7720 Group Appendix 11. Electrical characteristics Appendix 12. Standard characteristics APPENDIX Appendix 1. Memory assignment of 7721 Group Appendix 1. Memory assignment of 7721 Group Microprocessor mode M37721S2BFP 00000016 00007F16 00008016 SFR area (512 bytes) 00027F16 Internal RAM area (512 bytes) 00047F16 Case of internal RAM area select bit = "1" Case of internal RAM area select bit = "0" M37721S1BFP SFR area 00000216 Internal RAM area (512 bytes) (Note 2) SFR area External area 00000916 External area External area Bank 016 001FC016 SFR area 001FFF16 SFR area Notes 1: Interrupt vector table is assigned to addresses FFCE16 to FFFF16. Make sure to set a ROM to this area. 2: For the M37721S1BFP, fix the internal RAM area select bit to "0." 00FFFF16 01000016 Bank 116 External area (Note 1) External area (Note 1) 01FFFF16 FF000016 Bank FF16 FFFFFF16 Fig. 1 Memory assignment (microprocessor mode) 17-2 7721 Group User's Manual APPENDIX Appendix 2. Memory assignment in SFR area Appendix 2. Memory assignment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. 0 1 ? : Always "0" at reading. : Always "1" at reading. : Always undefined at reading. 0 : "0" immediately after reset. Fix this bit to "0." Address Register name 016 116 216 316 416 516 616 716 816 916 Port P4 register A16 Port P5 register B16 C16 Port P4 direction register D16 Port P5 direction register Port P6 register E16 Port P7 register F16 1016 Port P6 direction register 1116 Port P7 direction register 1216 Port P8 register Port P9 register 1316 1416 Port P8 direction register 1516 Port P9 direction register Port P10 register 1616 1716 1816 Port P10 direction register 1916 1A16 Pulse output data register 0 1B16 1C16 Pulse output data register 1 1D16 1E16 A-D control register 1F16 A-D sweep pin select register Access characteristics State immediately after reset b0 b7 ? ? ? ? ? ? ? ? ? ? b7 b0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW WO WO RW RW 0 ? 0 ? 0 0 ? ? 0 00 0016 ? ? 0016 0016 ? ? 0016 0016 ? ? 0016 ? ? ? ? ? 00 ?? 0 0 0 0 0 0 0 ? ? ? ? 1 ? 1 7721 Group User's Manual 17-3 APPENDIX Appendix 2. Memory assignment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after a reset 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. 0 : Always "0" at reading. : Always "1" at reading. : Always undefined at reading. ? 1 0 : "0" immediately after reset. Fix this bit to "0." Address 2016 2116 2216 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 2C16 2D16 2E16 2F16 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C16 3D16 3E16 3F16 Register name b7 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 UART0 transmit/receive mode register UART0 baud rate register UART0 transmit buffer register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 baud rate register UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register Access characteristics RO RO RO RO RO RO RO RO RW WO WO b0 b7 State immediately after reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0016 ? ? ? ?1 00 ? 00 0016 ? ? ? ?1 00 ? 00 b0 WO RO RO RO RO RW WO WO RO RO RO RO 0 0 0 WO RW RW RO RW ? 0 ? 0 ? 0 0 0 0 RW RW RO RW ? 0 ? 0 ? 0 0 0 0 0 1 0 0 0 ? 0 0 0 0 1 0 0 0 ? 17-4 7721 Group User's Manual APPENDIX Appendix 2. Memory assignment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. 0 : Always "0" at reading. : Always "1" at reading. ? : Always undefined at reading. 1 0 : "0" immediately after reset. Fix this bit to "0." 0 Address Register name b7 Count start register Access characteristics b0 State immediately after reset b7 b0 4016 4116 4216 One-shot start register 4316 Up-down register 4416 4516 4616 Timer A0 register 4716 4816 Timer A1 register 4916 4A16 Timer A2 register 4B16 4C16 Timer A3 register 4D16 4E16 Timer A4 register 4F16 5016 Timer B0 register 5116 5216 Timer B1 register 5316 5416 Timer B2 register 5516 5616 Timer A0 mode register 5716 Timer A1 mode register 5816 Timer A2 mode register 5916 Timer A3 mode register 5A16 Timer A4 mode register 5B16 Timer B0 mode register 5C16 Timer B1 mode register 5D16 Timer B2 mode register 5E16 Processor mode register 0 5F16 Processor mode register 1 RW WO WO RW RW RW RW (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) (Note 2) RW RW RW RW RW RW RW RW RW RW (Note 3) (Note 3) (Note 3) ? 0 0 0 RW 0 0 0 0 0 0 RW RW RW RW WO RW RW RW 0 0 0 0 0 0 0 0 ? ? ? 0 ? 0016 ? 00 ? 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 00 00 0016 0016 0016 ?0 ?0 ?0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 (Note 4) 0 0 0 0 ? Notes 1: The access characteristics at addresses 4A16 to 4F16 vary according to Timer A's operating mode. (Refer to "CHAPTER 8. TIMER A.") 2: The access characteristics at addresses 5016 to 5316 vary according to Timer B's operating mode. (Refer to "CHAPTER 9. TIMER B.") 3: The access characteristics for bit 5 at addresses 5B16 and 5C16 vary according to Timer B's operating mode. Bit 5 at address 5D16 is invalid. (Refer to "CHAPTER 9. TIMER B.") 4: Bit 1 at address 5F16 becomes "0" immediately after reset. For the M37721S1BFP, fix this bit to "0." 7721 Group User's Manual 17-5 APPENDIX Appendix 2. Memory assignment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. R O : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. 0 : Always "0" at reading. 1 : Always "1" at reading. ? : Always undefined at reading. 0 : "0" immediately after reset. Fix this bit to "0." 0 Address Register name Watchdog timer register b7 Access characteristics (Note 5) b0 b7 State immediately after reset ?(Note 6) ? 00 ? 00 ? ? ? 0? 00 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 b0 6016 6116 Watchdog timer frequency select register 6216 Real-time output control register 6316 DRAM control register 6416 6516 Refresh timer 6616 6716 DM AC control register L 6816 DM AC control register H 6916 6A16 6B16 DMA0 interrupt control register 6C16 DMA1 interrupt control register 6D16 DMA2 interrupt control register 6E16 DMA3 interrupt control register 6F16 7016 A-D conversion interrupt control register 7116 UART0 transmit interrupt control register 7216 UART0 receive interrupt control register 7316 UART1 transmit interrupt control register 7416 UART1 receive interrupt control register Timer A0 interrupt control register 7516 Timer A1 interrupt control register 7616 Timer A2 interrupt control register 7716 Timer A3 interrupt control register 7816 Timer A4 interrupt control register 7916 Timer B0 interrupt control register 7A16 Timer B1 interrupt control register 7B16 Timer B2 interrupt control register 7C16 INT0 interrupt control register 7D16 INT1 interrupt control register 7E16 INT2 interrupt control register 7F16 RW RW RW WO (Note 7) RW 00 RW 00 0 0 0 0 0 0 0 0 0 RW WO RW 0 0 0 0 0 0 ? 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Notes 5: By writing dummy data to address 6016, the value "FFF16" is set to the watchdog timer. The dummy data is not retained anywhere. 6: The value "FFF16" is set to the watchdog timer. (Refer to "CHAPTER 15. WATCHDOG TIMER.") 7: It is possible to read the bit state at reading. When writing "0" to this bit, this bit becomes "0." But when writing "1" to this bit, this bit does not change. 17-6 7721 Group User's Manual APPENDIX Appendix 2. Memory assignment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. 0 : Always "0" at reading. 1 : Always "1" at reading. : Always undefined at reading. ? 0 : "0" immediately after reset. Fix this bit to "0." 0 Address 1FC016 1FC116 1FC216 1FC316 1FC416 1FC516 1FC616 1FC716 1FC816 1FC916 1FCA16 1FCB16 1FCC16 1FCD16 1FCE16 1FCF16 1FD016 1FD116 1FD216 1FD316 1FD416 1FD516 1FD616 1FD716 1FD816 1FD916 1FDA16 1FDB16 1FDC16 1FDD16 1FDE16 1FDF16 Register name b7 Access characteristics RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW b0 b7 State immediately after reset ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 0 ? 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 0 ? 0 0 0 0 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b0 Source address register 0 Destination address register 0 Transfer counter register 0 DMA0 mode register L DMA0 mode register H DMA0 control register 0 0 0 Source address register 1 Destination address register 1 Transfer counter register 1 DMA1 mode register L DMA1 mode register H DMA1 control register 0 0 0 7721 Group User's Manual 17-7 APPENDIX Appendix 2. Memory assignment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. 0 1 ? : Always "0" at reading. : Always "1" at reading. : Always undefined at reading. 0 : "0" immediately after reset. Fix this bit to "0." Address 1FE016 1FE116 1FE216 1FE316 1FE416 1FE516 1FE616 1FE716 1FE816 1FE916 1FEA16 1FEB16 1FEC16 1FED16 1FEE16 1FEF16 1FF016 1FF116 1FF216 1FF316 1FF416 1FF516 1FF616 1FF716 1FF816 1FF916 1FFA16 1FFB16 1FFC16 1FFD16 1FFE16 1FFF16 Register name Access characteristics RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 0 ? 0 0 ? 0 0 0 0 0 0 ? 0 0 ? 0 0 ? 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 State immediately after reset ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 b7 b0 b7 b0 Source address register 2 Destination address register 2 Transfer counter register 2 DMA2 mode register L DMA2 mode register H DMA2 control register Source address register 3 Destination address register 3 Transfer counter register 3 DMA3 mode register L DMA3 mode register H DMA3 control register 17-8 7721 Group User's Manual APPENDIX Appendix 3. Control registers Appendix 3. Control registers The control registers allocated in the SFR area are shown on the following pages. Below is the structure diagram for all registers. V1 b7 b6 b5 b4 b3 b2 b1 b0 !0 XXX register (Address XX16) V2 V3 At reset Bit 0 1 Bit name ... select bit ... select bit 0 : ... 1 : ... Functions RW RW WO 0 Undefined 0 : ... 1 : ... The value is "0" at reading. 0 : ... 1 : ... 2 3 4 ... flag Fix this bit to "0." This bit is invalid in ... mode. 0 0 0 Undefined RO RW RW - 7 to 5 Nothing is assigned. V4 Blank 0 1 ! V2 0 1 Undefined V3 RW RO WO : "0" immediately after reset. : "1" immediately after reset. : Undefined immediately after reset. : Set to "0" or "1" according to the usage. : Set to "0" at writing. : Set to "1" at writing. : Invalid depending on the mode or state. It may be "0" or "1." : Nothing is assigned. V1 -- : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. Accordingly, the written value may be "0" or "1." : The written value becomes valid. It is impossible to read the bit state. The value is undefined at reading. However, when ["0" is at reading"] is indicated in the "Function" or "Note" column, the bit is always "0" at reading. (See V4 above.) : It is impossible to read the bit state. The value is undefined at reading. However, when ["0" is at reading"] is indicated in the "Function" or "Note" column, the bit is always "0" at reading. (See V4 above.) The written value becomes invalid. Accordingly, the written value may be "0" or "1." 7721 Group User's Manual 17-9 APPENDIX Appendix 3. Control registers Port Pi register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi register (i = 4 to 10) (Addresses A16, B16, E16, F16, 1216, 1316, 1616) Bit 0 1 2 3 4 5 6 7 Bit name Port Pi0's pin Port Pi1's pin Port Pi2's pin Port Pi3's pin Port Pi4's pin Port Pi5's pin Port Pi6's pin Port Pi7's pin Functions Data is input from or output to a pin by reading from or writing to the corresponding bit. 0 : "L" level 1 : "H" level At reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined RW RW RW RW RW RW RW RW RW Note: For bits 0 to 2 of the port P4 register, nothing is assigned and these bits are fixed to "0" at reading. Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (i = 4 to 10) (Addresses C16, D16, 1016, 1116, 1416, 1516, 1816) Bit 0 1 2 3 4 5 6 7 Bit name Port Pi0 direction bit Port Pi1 direction bit Port Pi2 direction bit Port Pi3 direction bit Port Pi4 direction bit Port Pi5 direction bit Port Pi6 direction bit Port Pi7 direction bit Functions 0 : Input mode (The port functions as an input port) 1 : Output mode (The port functions as an output port) At reset RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Note: For bits 0 to 2 of the port P4 direction register, nothing is assigned and these bits are fixed to "0" at reading. 17-10 7721 Group User's Manual APPENDIX Appendix 3. Control registers Pulse output data register 0 b7 b6 b5 b4 b3 b2 b1 b0 Pulse output data register 0 (Address 1A16) Bit 0 1 2 3 7 to 4 Bit name RTP00 pulse output data bit RTP01 pulse output data bit RTP02 pulse output data bit (Valid in pulse mode 0) RTP03 pulse output data bit (Valid in pulse mode 0) Nothing is assigned. Functions 0 : "L" level output 1 : "H" level output At reset Undefined Undefined Undefined RW WO WO WO WO Undefined Undefined Note: Use the LDM or STA instruction for writing to this register Pulse output data register 1 b7 b6 b5 b4 b3 b2 b1 b0 Pulse output data register 1 (Address 1C16) Bit 0, 1 2 3 4 5 6 7 Bit name Nothing is assigned. RTP02 pulse output data bit (Valid in pulse mode 1) RTP03 pulse output data bit (Valid in pulse mode 1) RTP10 pulse output data bit RTP11 pulse output data bit RTP12 pulse output data bit RTP13 pulse output data bit Functions At reset Undefined RW 0 : "L" level output 1 : "H" level output Undefined WO WO WO WO WO WO Undefined Undefined Undefined Undefined Undefined Note: Use the LDM or STA instruction for writing to this register. 7721 Group User's Manual 17-11 APPENDIX Appendix 3. Control registers A-D control register b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (Address 1E16) Bit 0 1 Bit name Analog input select bits (Valid in one-shot and repeat modes) (Note 1) b2 b1 b0 Functions 0 0 0 : AN0 selected 0 0 1 : AN1 selected 0 1 0 : AN2 selected 0 1 1 : AN3 selected 1 0 0 : AN4 selected 1 0 1 : AN5 selected 1 1 0 : AN6 selected 1 1 1 : AN7 selected (Note 2) b4 b3 At reset Undefined RW RW Undefined RW RW 2 A-D operation mode select bit Undefined 3 4 5 6 7 Trigger select bit A-D conversion start bit A-D conversion frequency ( AD) select bit 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 : Internal trigger 1 : External trigger 0 : Stop A-D conversion 1 : Start A-D conversion 0 : f2 divided by 4 1 : f2 divided by 2 0 0 0 0 0 RW RW RW RW RW Notes 1: These bits are invalid in the single sweep and repeat sweep mode. (They may be either "0" or "1.") 2: When selecting an external trigger, the AN7 pin cannot be used as an analog input pin. 3: Writing to each bit (except bit 6) of the A-D control register must be performed while the A-D converter halts. A-D sweep pin select register b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select register (Address 1F16) Bit 0 1 Bit name A-D sweep pin select bits (Valid in single sweep and repeat sweep modes) (Note 1) b1 b0 Functions 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) (Note 2) At reset RW RW RW 1 1 Undefined 7 to 2 Nothing is assigned. - Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either "0" or "1.") 2: When selecting an external trigger, the AN7 pin cannot be used as an analog input pin. 3: Writing to each bit of the A-D sweep pin select register must be performed while the A-D converter halts. A-D register i b7 b0 A-D register i (i = 0 to 7) (Addresses 2016, 2216, 2416, 2616, 2816, 2A16, 2C16, 2E16) Bit Functions At reset Undefined RW RO 7 to 0 Reads an A-D conversion result. 17-12 7721 Group User's Manual APPENDIX Appendix 3. Control registers UARTi transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) Bit 0 Bit name Serial I/O mode select bits b2 b1 b0 Functions 0 0 0 : Serial I/O disabled (P8 functions as a programmable I/O port.) 0 0 1 : Clock synchronous serial I/O mode 0 1 0 : Do not select. 0 1 1 : Do not select. 1 0 0 : UART mode (Transfer data length = 7 bits) 1 0 1 : UART mode (Transfer data length = 8 bits) 1 1 0 : UART mode (Transfer data length = 9 bits) 1 1 1 : Do not select. 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode terminated (Invalid) 1 : Sleep mode selected At reset RW RW 0 1 0 RW 2 0 RW 3 4 5 Internal/External clock select bit Stop bit length select bit (Valid in UART mode) (Note) Odd/Even parity select bit (Valid in UART mode when parity enable bit is "1") (Note) Parity enable bit (Valid in UART mode) (Note) Sleep select bit (Valid in UART mode) (Note) 0 0 0 RW RW RW 6 7 0 0 RW RW Note: Bits 4 to 6 are invalid in the clock synchronous serial I/O mode. (They may be either "0" or "1.") Additionally, fix bit 7 to "0." UARTi baud rate register b7 b0 UART0 baud rate register (Address 3116) UART1 baud rate register (Address 3916) Bit Functions At reset Undefined RW WO 7 to 0 Can be set to "0016" to "FF16." Assuming that the set value = n, BRGi divides the count source frequency by (n + 1). Note: Writing to this register must be performed while the transmission/reception halts. Use the LDM or STA instruction for writing to this register. 7721 Group User's Manual 17-13 APPENDIX Appendix 3. Control registers UARTi transmit buffer register (b15) b7 (b8) b0 b7 b0 UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16) Bit Functions At reset Undefined Undefined RW WO 8 to 0 Transmit data is set. 15 to 9 Nothing is assigned. - Note: Use the LDM or STA instruction for writing to this register. UARTi transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) Bit 0 Bit name BRG count source select bits b1 b0 Functions 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 0 : CTS function selected 1 : RTS function selected 0 : Data present in transmit register (During transmission) 1 : No data present in transmit register (Transmission completed) At reset RW RW RW RW RO 0 1 2 3 CTS/RTS select bit Transmit register empty flag 0 0 1 7 to 4 Nothing is assigned. Undefined - 17-14 7721 Group User's Manual APPENDIX Appendix 3. Control registers UARTi transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) Bit 0 1 Bit name Transmit enable bit Transmit buffer empty flag Functions 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register (Note 1) 0 : No overrun error 1 : Overrun error detected At reset RW RW RO 0 1 2 Receive enable bit 0 0 RW RO 3 Receive complete flag 4 5 6 7 Overrun error flag 0 0 0 0 RO RO RO RO Framing error flag (Notes 1, 2) 0 : No framing error 1 : Framing error detected (Valid in UART mode) (Notes 1, 2) 0 : No parity error Parity error flag (Valid in UART mode) 1 : Parity error detected (Notes 1, 2) 0 : No error Error sum flag 1 : Error detected (Valid in UART mode) Notes 1: Bit 4 is cleared to "0" when the receive enable bit is cleared to "0" or when the serial I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) are cleared to "0002." Bits 5 and 6 are cleared to "0" when one of the following is performed: *Clearing the receive enable bit to "0" *Reading the low-order byte of the UARTi receive buffer register (addresses 3616, 3E16) out *Clearing the serial I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) to "0002" Bit 7 is cleared to "0" when all of bits 4 to 6 become "0." 2: Bits 5 to 7 are invalid in the clock synchronous serial I/O mode. UARTi receive buffer register (b15) b7 (b8) b0 b7 b0 UART0 receive buffer register (Addresses 3716, 3616) UART1 receive buffer register (Addresses 3F16, 3E16) Bit Functions At reset Undefined RW RO 8 to 0 Receive data is read out from here. 15 to 9 Nothing is assigned. The value is "0" at reading. 0 - 7721 Group User's Manual 17-15 APPENDIX Appendix 3. Control registers Count start register b7 b6 b5 b4 b3 b2 b1 b0 Count start register (Address 4016) Bit 0 1 2 3 4 5 6 7 Bit name Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit Functions 0 : Stop counting 1 : Start counting At reset RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 One-shot start register b7 b6 b5 b4 b3 b2 b1 b0 00 One-shot start register (Address 4216) Bit 0 1 2 3 4 Bit name Functions At reset RW WO WO WO WO WO Fix these bits to "0." The value is "0" at reading. 0 0 Timer A2 one-shot start bit Timer A3 one-shot start bit Timer A4 one-shot start bit 1 : Start outputting one-shot pulse (valid when internal trigger is selected.) The value is "0" at reading. 0 0 0 Undefined 7 to 5 Nothing is assigned. - 17-16 7721 Group User's Manual APPENDIX Appendix 3. Control registers Up-down register b7 b6 b5 b4 b3 b2 b1 b0 00 Up-down register (Address 4416) Bit 0 1 2 3 4 5 Bit name Fix these bits to "0." Functions At reset RW RW RW RW RW RW WO 0 0 Timer A2 up-down bit Timer A3 up-down bit Timer A4 up-down bit 0 : Countdown 1 : Countup This function is valid when the contents of the up-down register is selected as the updown switching factor. 0 0 0 0 6 Timer A2 two-phase pulse signal 0 : Two-phase pulse signal processing function disabled processing select bit (Note) 1 : Two-phase pulse signal processing function enabled Timer A3 two-phase pulse signal processing select bit When not using the two-phase pulse signal processing function, set the bit Timer A4 two-phase pulse signal to "0." processing select bit (Note) The value is "0" at reading. (Note) 0 WO 7 0 WO Note: Use the LDM or STA instruction for writing to bits 5 to 7. 7721 Group User's Manual 17-17 APPENDIX Appendix 3. Control registers Timer Ai register (b15) b7 (b8) b0 b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Bit Functions At reset Undefined RW RW (Note 1) 15 to 0 These bits have different functions according to the operating mode. Notes 1: The access characteristics for the timer A2 register, timer A3 register, and timer A4 register differ according to Timer A's operating mode. 2: Read from or write to this register in a unit of 16 bits. Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Bit 0 Bit name Operating mode select bits b1 b0 Functions 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot pulse mode 1 1 : Pulse width modulation (PWM) mode At reset RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 These bits have different functions according to the operating mode. 17-18 7721 Group User's Manual APPENDIX Appendix 3. Control registers Timer Mode (b15) b7 (b8) b0 b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Bit Functions RW RW At reset Undefined 15 to 0 These bits can be set to "000016" to "FFFF16." Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Note: Read from or write to this register in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 000000 Timer A0 mode register (Address 5616) Timer A1 mode register (Address 5716) Bit 0 1 2 3 4 5 6 7 Bit name Fix these bits to "0." Functions At reset RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 Count source select bits b7 b6 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 0 0 b7 b6 b5 b4 b3 b2 b1 b0 0 00 Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) Bit 0 1 2 Bit name Operating mode select bits b1 b0 Functions 0 0 : Timer mode At reset RW RW RW RW 0 0 Pulse output function select bit 0 : No pulse output (TAjOUT pin functions as a programmable I/O port.) 1 : Pulse output (TAjOUT pin functions as a pulse output pin.) b4 b3 0 3 Gate function select bits 0 RW 4 0 0 : No gate function 0 1 : (TAjIN pin functions as a programmable I/O port.) 1 0 : Counter counts only while TAjIN pin's input signal is at "L" level. 1 1 : Counter counts only while TAjIN pin's input signal is at "H" level. 0 RW 5 6 7 Fix this bit to "0" in timer mode. Count source select bits b7 b6 0 0 0 RW RW RW 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 7721 Group User's Manual 17-19 APPENDIX Appendix 3. Control registers Event counter mode (b15) b7 (b8) b0 b7 b0 Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) At reset Undefined Bit Functions RW RW 15 to 0 These bits can be set to "000016" to "FFFF16." Assuming that the set value = n, the counter divides the count source frequency by (n + 1) during countdown, or by (FFFF16 - n + 1) during countup. When reading, the register indicates the counter value. Note: Read from or write to this register in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 !!0 01 Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) Bit 0 1 2 Bit name Operating mode select bits b1 b0 Functions 0 1 : Event counter mode At reset RW RW RW RW 0 0 Pulse output function select bit 0 : No pulse output (TAjOUT pin functions as a programmable I/O port.) 1 : Pulse output (TAjOUT pin functions as a pulse output pin.) 0 : Counts at falling edge of external signal 1 : Counts at rising edge of external signal 0 : Contents of up-down register 1 : Input signal to TAjOUT pin 0 3 4 5 6 7 Count polarity select bit Up-down switching factor select bit 0 0 0 0 0 RW RW RW RW RW Fix this bit to "0" in event counter mode. These bits are invalid in event counter mode. 17-20 7721 Group User's Manual APPENDIX Appendix 3. Control registers One-shot pulse mode (b15) b7 (b8) b0 b7 b0 Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Bit Functions At reset Undefined RW WO 15 to 0 These bits can be set to "000116" to "FFFF16." Assuming that the set value = n, the "H" level width of the one-shot pulse output from the TAjOUT pin is expressed as follows : n fi. fi: Frequency of count source (f2 , f16, f64, or f512) Note: Use the LDM or STA instruction for writing to this register. Read from or write to this register in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 0 110 Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) Bit 0 1 2 3 Bit name Operating mode select bits b1 b0 Functions 1 0 : One-shot pulse mode At reset RW RW RW RW RW 0 0 Fix this bit to "1" in one-shot pulse mode. Trigger select bits b4 b3 0 0 4 0 0 : Writing "1" to one-shot start register 0 1 : (TAjIN pin functions as a programmable I/O port.) 1 0 : Falling edge of TAjIN pin's input signal 1 1 : Rising edge of TAjIN pin's input signal 0 RW 5 6 7 Fix this bit to "0" in one-shot pulse mode. Count source select bits b7 b6 0 0 0 RW RW 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 RW 7721 Group User's Manual 17-21 APPENDIX Appendix 3. Control registers Pulse width modulation (PWM) mode (b15) b7 (b8) b0 b7 b0 Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) At reset Bit Functions RW 15 to 0 These bits can be set to "000016" to "FFFE16." Undefined WO Assuming that the set value = n, the "H" level width of the PWM pulse output from the n TAjOUT pin is expressed as follows: fi n16 - 1 ) (PWM pulse period = fi fi: Frequency of count source (f2, f16, f64, or f512) Note: Use the LDM or STA instruction for writing to this register. Read from or write to this register in a unit of 16 bits. (b15) b7 (b8) b0 b7 b0 Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Functions Bit At reset Undefined RW WO 7 to 0 These bits can be set to "0016" to "FF16." Assuming that the set value = m, PWM pulse's period output from the TAjOUT pin is 8 expressed as follows: (m + 1)(2 - 1) fi 15 to 8 These bits can be set to "0016" to "FE16." Assuming that the set value = n, the "H" level width of the PWM pulse output from the TAjOUT pin is expressed as follows: n(m + 1) fi Undefined WO fi: Frequency of count source (f2, f16, f64, or f512) Note: Use the LDM or STA instruction for writing to this register. Read from or write to this register in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 111 Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) Bit 0 1 2 3 Bit name Operating mode select bits b1 b0 Functions 1 1 : PWM mode At reset RW RW RW RW RW 0 0 Fix this bit to "1" in PWM mode. Trigger select bits b4 b3 0 0 0 : Writing "1" to count start register 0 1 : (TAj IN pin functions as a programmable I/O port.) 1 0 : Falling edge of TAjIN pin's input signal 1 1 : Rising edge of TAjIN pin's input signal 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator b7 b6 0 4 5 6 7 16/8-bit PWM mode select bit Count source select bits 0 RW 0 0 0 RW RW RW 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 17-22 7721 Group User's Manual APPENDIX Appendix 3. Control registers Timer Bi register (b15) b7 (b8) b0 b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) Bit Functions At reset RW 15 to 0 These bits have different functions according Undefined RW to the operating mode. (Note 1) Notes 1: The access characteristics for the timer B0 register and timer B1 register differ according to Timer B's operating mode. 2: Read from or write to this register in a unit of 16 bits. Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Bit 0 Bit name Operating mode select bits b1 b0 Functions 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/Pulse width measurement mode 1 1 : Do not select. At reset RW RW 0 1 0 RW 2 3 4 5 6 7 These bits have different functions according to the operating mode. 0 0 RW RW Nothing is assigned. These bits have different functions according to the operating mode. Undefined Undefined - RO (Note) RW RW 0 0 Note: Bit 5 is invalid in the timer and event counter modes; its value is undefined at reading. 7721 Group User's Manual 17-23 APPENDIX Appendix 3. Control registers Timer mode (b15) b7 (b8) b0 b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) Bit Functions At reset RW RW 15 to 0 These bits can be set to "000016" to "FFFF16." Undefined Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Note: Read from or write to this register in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 ! !!0 0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Bit 0 1 2 3 4 5 6 7 Bit name Operating mode select bits b1 b0 Functions 0 0 : Timer mode At reset RW RW RW RW RW 0 0 These bits are invalid in timer mode. 0 0 Nothing is assigned. This bit is invalid in timer mode; its value is undefined at reading. Count source select bits b7 b6 Undefined Undefined - RO RW RW 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 0 0 17-24 7721 Group User's Manual APPENDIX Appendix 3. Control registers Event counter mode (b15) b7 (b8) b0 b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Bit Functions At reset Undefined RW RW 15 to 0 These bits can be set to "000016" to "FFFF16." Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Note: Read from or write to this register in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 !!! 01 Timer Bj mode register (j = 0, 1) (Addresses 5B16, 5C16) Bit 0 1 2 Bit name Operating mode select bits b1 b0 Functions 0 1 : Event counter mode At reset RW RW RW RW 0 0 Count polarity select bits b3 b2 0 3 0 0 : Count at falling edge of external signal 0 1 : Count at rising edge of external signal 1 0 : Counts at both falling and rising edges of external signal 1 1 : Do not select. Nothing is assigned. This bit is invalid in event counter mode; its value is undefined at reading. These bits are invalid in event counter mode. 0 RW 4 Undefined -- 5 6 7 Undefined RO RW RW 0 0 7721 Group User's Manual 17-25 APPENDIX Appendix 3. Control registers Pulse period/pulse width measurement mode (b15) b7 (b8) b0 b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Bit Functions At reset Undefined RW RO 15 to 0 The measurement result of pulse period or pulse width is read out. Note: Read from this register in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 10 Timer Bj mode register (j = 0, 1) (Addresses 5B16, 5C16) Bit 0 1 2 Bit name Operating mode select bits b1 b0 Functions 1 0 : Pulse period/Pulse width measurement mode b3 b2 At reset RW RW RW RW 0 0 0 Measurement mode select bits 3 0 0 : Pulse period measurement (Interval between falling edges of measurement pulse) 0 1 : Pulse period measurement (Interval between rising edges of measurement pulse) 1 0 : Pulse width measurement (Interval from a falling edge to a rising edge, and from a rising edge to a falling edge of measurement pulse) 1 1 : Do not select. 0 RW 4 5 6 7 Nothing is assigned. Timer Bj overflow flag (Note) Count source select bits 0 : No overflow 1 : Overflowed b7 b6 Undefined Undefined - RO RW RW 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 0 0 Note: The timer Bj overflow flag is cleared to "0" at the next count timing of the count source when a value is written to the timer Bj mode register with the count start bit = "1." 17-26 7721 Group User's Manual APPENDIX Appendix 3. Control registers Processor mode register 0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 Processor mode register 0 (Address 5E16) Bit 0 1 2 Bit name Fix this bit to "0." Nothing is assigned. The value is "1" at reading. Wait bit Functions At reset RW RW - RW 0 1 0 : Software Wait is inserted when accessing external area. 1 : No software Wait is inserted when accessing external area. The microcomputer is reset by writing "1" to this bit. The value is "0" at reading. b5 b4 0 3 Software reset bit 0 WO 4 5 6 7 Interrupt priority detection time select bits 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : Do not select. 0 0 0 RW RW RW RW Fix this bit to "0." Stack bank select bit 0 : Bank 016 1 : Bank FF16 0 Processor mode register 1 b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 1 (Address 5F16) Bit 0 1 Bit name Nothing is assigned. Internal RAM area select bit (Notes 1, 2) Functions At reset RW - RW - Undefined 0 : 512 bytes (addresses 8016 to 27F16) 1 : 1024 bytes (addresses 8016 to 47F16) 0 Undefined 7 to 2 Nothing is assigned. Notes 1: For the M37721S1BFP, fix bit 1 to "0." 2: For the M37721S2BFP, set bit 1 before setting the stack pointer. 7721 Group User's Manual 17-27 APPENDIX Appendix 3. Control registers Watchdog timer register b7 b0 Watchdog timer register (Address 6016) Bit 7 to 0 Functions Initializes Watchdog timer. When dummy data is written to this register, Watchdog timer's value is initialized to "FFF16." (Dummy data: 0016 to FF16) At reset Undefined RW - Watchdog timer frequency select register b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer frequency select register (Address 6116) Bit 0 Bit name Watchdog timer frequency select 0 : f512 1 : f32 bit Functions At reset RW RW 0 Undefined 7 to 1 Nothing is assigned. - 17-28 7721 Group User's Manual APPENDIX Appendix 3. Control registers Real-time output control register b7 b6 b5 b4 b3 b2 b1 b0 Real-time output control register (Address 6216) Bit 0 1 2 Bit name Waveform output select bits Functions See the following Table. At reset RW RW RW RW 0 0 Pulse output mode select bit 0 : Pulse mode 0 1 : Pulse mode 1 0 7 to 3 Nothing is assigned. The value is "0" at reading. Undefined - Note: When using the P60-P67 pins as the pulse output pins for real-time output, set the corresponding bits of the port P6 direction register (address 1016) to "1." b1 b0 00 P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 01 P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 10 P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 11 P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Port Port RTP RTP When pulse mode 0 is selected Port RTP Port RTP When pulse mode 1 is selected P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Port P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Port P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 RTP P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 RTP Port RTP Port RTP Port : This functions as a programmable I/O port. RTP : This functions as a pulse output pin. 7721 Group User's Manual 17-29 APPENDIX Appendix 3. Control registers DRAM control register b7 b6 b5 b4 b3 b2 b1 b0 DRAM control register (Address 6416) Bit 0 Bit name b3 b2 b1 b0 Functions 0 0 0 0 : No DRAM area 0 0 0 1 : F0000016-FFFFFF16 (1 Mbyte) 0 0 1 0 : E0000016-FFFFFF16 (2 Mbytes) 0 0 1 1 : D0000016-FFFFFF16 (3 Mbytes) 0 1 0 0 : C0000016-FFFFFF16 (4 Mbytes) 0 1 0 1 : B0000016-FFFFFF16 (5 Mbytes) 0 1 1 0 : A0000016-FFFFFF16 (6 Mbytes) 0 1 1 1 : 90000016-FFFFFF16 (7 Mbytes) 1 0 0 0 : 80000016-FFFFFF16 (8 Mbytes) 1 0 0 1 : 70000016-FFFFFF16 (9 Mbytes) 1 0 1 0 : 60000016-FFFFFF16 (10 Mbytes) 1 0 1 1 : 50000016-FFFFFF16 (11 Mbytes) 1 1 0 0 : 40000016-FFFFFF16 (12 Mbytes) 1 1 0 1 : 30000016-FFFFFF16 (13 Mbytes) 1 1 1 0 : 20000016-FFFFFF16 (14 Mbytes) 1 1 1 1 : 10000016-FFFFFF16 (15 Mbytes) At reset RW RW DRAM area select bits 0 1 0 RW 2 0 RW 3 0 RW 6 to 4 7 Nothing is assigned. The value is "0" at reading. DRAM validity bit (Note) 0 : Invalid (P104-P107 pins function as programmable input ports. A0- A7 pins function as address output pins. Refresh timer stops counting.) 1 : Valid (P104-P107 pins function as CAS, RAS, MA8, and MA9. A0-A7 function as MA0-MA7. Refresh timer starts counting.) 0 0 - RW Note: Set the refresh timer (address 6616) before setting this bit to "1." Refresh timer b7 b0 Refresh timer (Address 6616) Bit Functions At reset Undefined RW WO 7 to 0 These bits can be set to "0116" to "FF16." Assuming that the set value = n, this register divides f16 by (n + 1). Note: Use the LDM or STA instruction for writing to this register. Do not set this register to "0016." 17-30 7721 Group User's Manual APPENDIX Appendix 3. Control registers DMAC control register L b7 b6 b5 b4 b3 b2 b1 b0 DMAC control register L (Address 6816) Bit 0 1 Bit name Priority select bit TC pin validity bit 0 : Fixed 1 : Rotating Functions At reset RW RW RW 0 0 0 : Invalid (P103 pin functions as a programmable I/O port (CMOS).) 1 : Valid (P103 pin functions as TC pin (Nchannel open-drain).) 3, 2 4 5 6 7 Nothing is assigned. DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit 0 : No request 1 : Requested (Note 1) Undefined 0 0 0 0 - RW RW RW RW Notes 1. The state of bits 4 to 7 are not changed when writing "1" to these bits. 2. *When writing to this register while any of DMAi enable bits (bits 4 to 7 at address 6916) is "1," set m flag to "1" and use the LDM or STA instruction. When DMAi request bit (bits 4 to 7 at address 6816) must not be changed, set DMAi request bit to "1." *When writing to this register while all of DMAi enable bits (bits 4 to 7 at address 6916) are "0," m flag may be "0" or "1." Use the LDM or STA instruction for writing to this register. When DMAi request bit (bits 4 to 7 at address 6816) must not be changed, set DMAi request bit to "1." DMAC control register H b7 b6 b5 b4 b3 b2 b1 b0 DMAC control register H (Address 6916) Bit 0 1 2 3 4 5 6 7 Bit name Software DMA0 request bit Software DMA1 request bit Software DMA2 request bit Software DMA3 request bit DMA0 enable bit DMA1 enable bit DMA2 enable bit DMA3 enable bit 0 : Disabled 1 : Enabled Functions 1 : DMA request (Valid when software DMA source is selected.) The value is "0" at reading. At reset RW WO WO WO WO RW RW RW RW 0 0 0 0 0 0 0 0 Note: When any of bits 4 to 7 is set to "1," use the CLB or SEB instruction for writing to this register. 7721 Group User's Manual 17-31 APPENDIX Appendix 3. Control registers Interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 DMA0 to DMA3, A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2 interrupt control registers (Addresses 6C16 to 7C16) Bit 0 Bit name Interrupt priority level select bits b2 b1 b0 Functions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested At reset RW RW 0 1 0 RW 2 0 RW 3 Interrupt request bit 0 Undefined RW 7 to 4 Nothing is assigned. - b7 b6 b5 b4 b3 b2 b1 b0 INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16) Bit 0 Bit name Interrupt priority level select bits b2 b1 b0 Functions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested 0 : Interrupt request bit is set to "1" at "H" level when level sense is selected; this bit is set to "1" at falling edge when edge sense is selected. 1 : Interrupt request bit is set to "1" at "L" level when level sense is selected; this bit is set to "1" at rising edge when edge sense is selected. 0 : Edge sense 1 : Level sense At reset RW RW 0 1 0 RW 2 0 RW 3 4 Interrupt request bit (Note) Polarity select bit 0 0 RW RW 5 7, 6 Level sense/Edge sense select bit Nothing is assigned. 0 Undefined RW - Note: The interrupt request bits of INT0 to INT2 interrupts are invalid when the level sense is selected. 17-32 7721 Group User's Manual APPENDIX Appendix 3. Control registers Source address register i b23 b16 b15 b8 b7 b0 Source address register 0 (Addresses 1FC216 to 1FC016) Source address register 1 (Addresses 1FD216 to 1FD016) Source address register 2 (Addresses 1FE216 to 1FE016) Source address register 3 (Addresses 1FF216 to 1FF016) Bit Functions At reset Undefined RW RW 23 to 0 These bits have different functions according to the operating mode. Note: When writing to this register, write to all 24 bits. Destination address register i b23 b16 b15 b8 b7 b0 Destination address register 0 (Addresses 1FC616 to 1FC416) Destination address register 1 (Addresses 1FD616 to 1FD416) Destination address register 2 (Addresses 1FE616 to 1FE416) Destination address register 3 (Addresses 1FF616 to 1FF416) Bit Functions At reset Undefined RW RW 23 to 0 These bits have different functions according to the operating mode. Note: When writing to this register, write to all 24 bits. Transfer counter register i b23 b16 b15 b8 b7 b0 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) Bit Functions At reset Undefined RW RW 23 to 0 These bits have different functions according to the operating mode. Note: When writing to this register, write to all 24 bits. Do not write "00000016" to this register. 7721 Group User's Manual 17-33 APPENDIX Appendix 3. Control registers Single transfer mode b23 b16 b15 b8 b7 b0 Source address register 0 (Addresses 1FC216 to 1FC016) Source address register 1 (Addresses 1FD216 to 1FD016) Source address register 2 (Addresses 1FE216 to 1FE016) Source address register 3 (Addresses 1FF216 to 1FF016) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the transfer start address of the source. These bits can be set to "00000016" to "FFFFFF16." [Read] The read value indicates the source address of data which is next transferred. Note: When writing to this register, write to all 24 bits. b23 b16 b15 b8 b7 b0 Destination address register 0 (Addresses 1FC616 to 1FC416) Destination address register 1 (Addresses 1FD616 to 1FD416) Destination address register 2 (Addresses 1FE616 to 1FE416) Destination address register 3 (Addresses 1FF616 to 1FF416) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the transfer start address of the destination. These bits can be set to "00000016" to "FFFFFF16." [Read] The read value indicates the destination address of data which is next transferred. Note: When writing to this register, write to all 24 bits. b23 b16 b15 b8 b7 b0 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the byte number of the transfer data. These bits can be set to "00000116" to "FFFFFF16." [Read] The read value indicates remaining byte number of the transfer data. Note: When writing to this register, write to all 24 bits. Do not set this register to "00000016." 17-34 7721 Group User's Manual APPENDIX Appendix 3. Control registers Repeat transfer mode b23 b16 b15 b8 b7 b0 Source address register 0 (Addresses 1FC216 to 1FC016) Source address register 1 (Addresses 1FD216 to 1FD016) Source address register 2 (Addresses 1FE216 to 1FE016) Source address register 3 (Addresses 1FF216 to 1FF016) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the transfer start address of the source. These bits can be set to "00000016" to "FFFFFF16." [Read] The read value indicates the source address of data which is next transferred. Note: When writing to this register, write to all 24 bits. b23 b16 b15 b8 b7 b0 Destination address register 0 (Addresses 1FC616 to 1FC416) Destination address register 1 (Addresses 1FD616 to 1FD416) Destination address register 2 (Addresses 1FE616 to 1FE416) Destination address register 3 (Addresses 1FF616 to 1FF416) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the transfer start address of the destination. These bits can be set to "00000016" to "FFFFFF16." [Read] The read value indicates the destination address of data which is next transferred. Note: When writing to this register, write to all 24 bits. b23 b16 b15 b8 b7 b0 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the byte number of the transfer data. These bits can be set to "00000116" to "FFFFFF16." [Read] The read value indicates the remaining byte number of the block which is being transferred. Note: When writing to this register, write to all 24 bits. Do not write "00000016" to this register. 7721 Group User's Manual 17-35 APPENDIX Appendix 3. Control registers Array chain transfer mode b23 b16 b15 b8 b7 b0 Source address register 0 (Addresses 1FC216 to 1FC016) Source address register 1 (Addresses 1FD216 to 1FD016) Source address register 2 (Addresses 1FE216 to 1FE016) Source address register 3 (Addresses 1FF216 to 1FF016) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the start address of transfer parameter memory. These bits can be set to "00000016" to "FFFFFF16." [Read] *After a value is written to this register and until transfer starts, the read value indicates the written value (the start address of the transfer parameter memory). *After tranfer starts, the read value indicates the source address of data which is next transferred. Note: When writing to this register, write to all 24 bits. b23 b16 b15 b8 b7 b0 Destination address register 0 (Addresses 1FC616 to 1FC416) Destination address register 1 (Addresses 1FD616 to 1FD416) Destination address register 2 (Addresses 1FE616 to 1FE416) Destination address register 3 (Addresses 1FF616 to 1FF416) Bit Functions At reset Undefined RW RW 23 to 0 Need not to set. [Read] After transfer starts, the read value indicates the destination address of data which is next transferred. b23 b16 b15 b8 b7 b0 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the number of transfer blocks. These bits can be set to "00000116" to "FFFFFF16." [Read] *After a value is written to this register and until transfer starts, the read value indicates the written value (the transfer block number) . *After transfer starts, the read value indicates the remaining byte number of the block which is being transferred. Note: When writing to this register, write to all 24 bits. Do not write "00000016" to this register. 17-36 7721 Group User's Manual APPENDIX Appendix 3. Control registers Link array chain transfer mode b23 b16 b15 b8 b7 b0 Source address register 0 (Addresses 1FC216 to 1FC016) Source address register 1 (Addresses 1FD216 to 1FD016) Source address register 2 (Addresses 1FE216 to 1FE016) Source address register 3 (Addresses 1FF216 to 1FF016) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the start address of transfer parameter memory of block which is first transferred. These bits can be set to "00000016" to "FFFFFF16." [Read] *After a value is written to this register and until transfer starts, the read value indicates the written value (the start address of the transfer parameter memory of block which is first transferred). *After transfer starts, the read value indicates the source address of data which is next transferred. Note: When writing to this register, write to all 24 bits. b23 b16 b15 b8 b7 b0 Destination address register 0 (Addresses 1FC616 to 1FC416) Destination address register 1 (Addresses 1FD616 to 1FD416) Destination address register 2 (Addresses 1FE616 to 1FE416) Destination address register 3 (Addresses 1FF616 to 1FF416) Bit Functions At reset Undefined RW RW 23 to 0 Need not to set. [Read] After transfer starts, the read value indicates the destination address of data which is next transferred. b23 b16 b15 b8 b7 b0 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) Bit Functions At reset Undefined RW RW 23 to 0 [Write] Set the dummy data. These bits can be set to "00000116" to "FFFFFF16." [Read] *After a value is written to this register and until transfer starts, the read value indicates the written value (dummy data). *After transfer starts, the read value indicates the remaining byte number of the block which is being transferred. Note: When writing to this register, write to all 24 bits. Do not write "00000016" to this register. 7721 Group User's Manual 17-37 APPENDIX Appendix 3. Control registers DMAi mode register L b7 b6 b5 b4 b3 b2 b1 b0 0 DMA0 mode register L (Address 1FCC16) DMA1 mode register L (Address 1FDC16) DMA2 mode register L (Address 1FEC16) DMA3 mode register L (Address 1FFC16) Bit 0 1 2 3 4 5 6 7 Transfer destination address direction select bits Bit name Number-of-unit-transfer-bits select bit (Note) Transfer method select bit Transfer mode select bit Fix this bit to "0." Transfer source address direction select bits b5b4 Functions 0 : 16 bits 1 : 8 bits 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer 0 : Burst transfer mode 1 : Cycle-steal transfer mode At reset RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. b7b6 0 0 0 0 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. Note: When the external data bus has a width of 8 bits and 1-bus cycle transfer is selected, set bit 0 to "1." DMAi mode register H b7 b6 b5 b4 b3 b2 b1 b0 00 DMA0 mode register H (Address 1FCD16) DMA1 mode register H (Address 1FDD16) DMA2 mode register H (Address 1FED16) DMA3 mode register H (Address 1FFD16) Bit 0 1 2 3 4 5 6 7 Bit name Transfer direction select bit (Used in 1-bus cycle transfer) (Note 1) I/O connection select bit (Valid in 1-bus cycle transfer) Fix these bits to "0." Functions 0 : From memory to I/O 1 : From I/O to memory Refer to "Fig.13.2.7." At reset RW RW RW 0 0 0 0 RW RW RW RW RW RW Transfer source wait bit (Note 2) 0 : Wait 1 : No Wait Transfer destination wait bit (Note 2) Continuous transfer mode select b7b6 0 0 : Single transfer bits 0 1 : Repeat transfer 1 0 : Array chain transfer 1 1 : Link array chain transfer 0 0 0 0 Notes 1: Set bit 0 to "0" in 2-bus cycle transfer. 2: Bits 4 and 5 are valid to the external and internal areas. However, DRAM area is always handled with "Wait" regardless of the contents of these bits. The wait bit (bit 2 at address 5E16) is invalid in DMA transfer. 17-38 7721 Group User's Manual APPENDIX Appendix 3. Control registers DMAi control register b7 b6 b5 b4 b3 b2 b1 b0 DMA0 control register (Address 1FCE16) DMA1 control register (Address 1FDE16) DMA2 control register (Address 1FEE16) DMA3 control register (Address 1FFE16) Bit 0 Bit name DMA request source select bits (Note) b3b2b1b0 Functions 0 0 0 0 : Do not select. 0 0 0 1 : External source (DMAREQi) 0 0 1 0 : Software DMA source 0 0 1 1 : Timer A0 0 1 0 0 : Timer A1 0 1 0 1 : Timer A2 0 1 1 0 : Timer A3 0 1 1 1 : Timer A4 1 0 0 0 : Timer B0 1 0 0 1 : Timer B1 1 0 1 0 : Timer B2 1 0 1 1 : UART0 receive 1 1 0 0 : UART0 transmit 1 1 0 1 : UART1 receive 1 1 1 0 : UART1 transmit 1 1 1 1 : A-D conversion 0 : Edge sense (Falling edge) 1 : Level sense ("L" level) At reset RW RW 0 1 0 RW 2 0 RW 3 0 RW 4 Edge sense/Level sense select bit (Used when external source and burst transfer mode are selected) (Note) DMAACKi validity bit 0 RW 5 0 : Invalid (The pin functions as a programmable I/O port.) 1 : Valid (The pin functions as DMAACKi.) 0 RW 7, 6 Nothing is assigned. Undefined - Note: When a certain source other than an external source is selected by bits 0 to 3 or when the cycle-steal transfer mode is selected, set bit 4 to "0." Level sense can be selected only when both of the external source and the burst transfer mode are selected. 7721 Group User's Manual 17-39 APPENDIX Appendix 4. Package outline Appendix 4. Package outline 17-40 7721 Group User's Manual APPENDIX Appendix 5. Examples of handling unused pins Appendix 5. Examples of handling unused pins Examples of handling unused pins are described below. These descriptions are just examples. The user shall modify them according to the actual application and test them. Table 1 Examples of handling unused pins Pins P43 to P47, P5 to P10 Handling example Connect these pins to the Vcc or Vss pin via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Notes 1, 2). Leave this pin open. Leave this pin open. Connect these pins to the Vcc pin via resistors (These pins are pulled high.) (Note 2) Connect this pin to the Vcc pin or Vss pin. Connect this pin to the Vcc pin. ____ BLE, BHE, ALE, 1, ST0, ST1 XOUT (Note 3) _____ ____ ____ HOLD, RDY CNVss AVcc Connect these pins to the Vss pin. AVss, VREF Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Accordingly, set these ports to the output mode immediately after reset. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 3: This applies when a clock externally generated is input to the XIN pin. q When setting ports to input mode q When setting ports to output mode P43-P47, P5-P10 ST0 ST1 BLE BHE ALE 1 P43-P47, P5-P10 ST0 ST1 BLE BHE ALE 1 Left open Left open Left open Fig. 2 Examples of handling unused pins M37721 M37721 XOUT Left open VCC XOUT Left open VCC HOLD RDY AVCC CNVSSV AVSS VREF VSS V CNVss pin can be connected to Vcc pin. HOLD RDY AVCC CNVSSV AVSS VREF VSS 7721 Group User's Manual 17-41 APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing modes Symbol Functions Details IMP op IMM A DIR DIR,b DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 69 2 2 42 4 3 69 29 2 2 42 4 3 29 65 4 2 42 6 3 65 25 4 2 42 6 3 25 0A 2 1 06 7 2 75 5 2 42 7 3 75 35 5 2 42 7 3 35 16 7 2 72 6 2 61 7 2 71 8 2 42 8 3 42 9 3 42 10 3 72 61 71 32 6 2 21 7 2 31 8 2 42 8 3 42 9 3 42 10 3 32 21 31 ADC ACC,CACC+M+C (Notes 1,2) Adds the carry, the accumulator and the memory contents.The result is entered into the accumulator. When the D flag is "0," binary additions is done, and when the D flag is "1," decimal addition is done. Obtains the logical product of the contents of the accumulator and the contents of the memory . The result is entered into the accumulator. ACCACCM AND (Notes 1,2) ASL (Note 1) m=0 C b15 *** b0 0 m=1 C b7 *** b0 0 Shifts the accumulator or the memory contents one bit to the left. "0" is entered into bit 0 of the accumulator or the memory. The contents of bit 15 ( bit 7 when the m flag is "1") of the accumulator or memory before shift is entered into the C flag. Tests the specified bit of the memory. Branches when all the contents of the specified bit is "0." Tests the specified bit of the memory. Branches when all the contents of the specified bit is "1." Branches when the contents of the C flag is "0." 42 4 2 0A Mb=0? BBC (Notes 3,5) Mb=1? BBS (Notes 3,5) BCC (Note 3) BCS (Note 3) BEQ (Note 3) BMI (Note 3) BNE (Note 3) BPL (Note 3) BRA (Note 4) C=0? C=1? Branches when the contents of the C flag is "1." Z=1? Branches when the contents of the Z flag is "1." N=1? Branches when the contents of the N flag is "1." Z=0? Branches when the contents of the Z flag is "0." N=0? Branches when the contents of the N flag is "0." PCPCoffset PGPG+1 (when carry occurs) PGPG-1 (when borrow occurs) PCPC+2 M(S)PG SS-1 M(S)PCH SS-1 M(S)PCL SS-1 M(S)PSH SS-1 M(S)PSL SS-1 I1 PCLADL PCHADH PG0016 V=0? Jumps to the address indicated by the program counter plus the offset value. BRK Executes software interruption. 00 15 2 BVC (Note 3) BVS (Note 3) CLB (Note 5) CLC CLI CLM CLP Branches when the contents of the V flag is "0." V=1? Branches when the contents of the V flag is "1." Mb0 Makes the contents of the specified bit in the memory "0." 14 8 3 C0 I0 m0 PSb0 Makes the contents of the C flag "0." Makes the contents of the I flag "0." Makes the contents of the m flag "0." Specifies the bit position in the processor status register by the bit pattern of the second byte in the instruction, and sets "0" in that bit. Makes the contents of the V flag "0." Compares the contents of the accumulator with the contents of the memory. 18 2 1 58 2 1 D8 2 1 C2 4 2 CLV V0 B8 2 1 C9 2 2 42 4 3 C9 C5 4 2 42 6 3 C5 D5 5 2 42 7 3 D5 D2 6 2 C1 7 2 D1 8 2 42 8 3 42 9 3 42 10 3 C1 D2 D1 CMP ACC-M (Notes 1,2) 17-42 7721 Group User's Manual APPENDIX Appendix 6. Machine instructions Addressing modes L(DIR) L(DIR),Y op Processor status register STK REL DIR,b,R ABS,b,R SR (SR),Y BLK 10 9 8 7 6 5 4 3 2 1 0 IPL N Vmx D I ZC ABS ABS,b ABS,X ABS,Y ABL ABL,X (ABS) L(ABS) (ABS,X) n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 7D 6 3 79 6 3 6F 6 4 7F 7 4 42 8 4 42 8 4 42 8 5 42 9 5 7D 79 6F 7F 3D 6 3 39 6 3 2F 6 4 3F 7 4 42 8 4 42 8 4 42 8 5 42 9 5 3D 39 2F 3F 1E 8 3 63 5 2 73 8 2 42 7 3 42 10 3 63 73 23 5 2 33 8 2 42 7 3 42 10 3 23 33 67 10 2 77 11 2 6D 4 3 42 12 3 42 13 3 42 6 4 77 6D 67 27 10 2 37 11 2 2D 4 3 42 12 3 42 13 3 42 6 4 37 2D 27 0E 7 3 * * * NV * * * * ZC * **N* * * * *Z* ***N** * * * ZC 34 7 4 3C 8 5 * ** * *** **** 24 7 4 2C 8 5 *** ** * ***** 90 4 2 *** **** **** B0 4 2 **** ** ***** F0 4 2 * **** ** **** 30 4 2 ***** ****** D0 4 2 ** *** * * **** 10 4 2 **** ** ***** 80 4 2 **** ** **** * 82 4 3 ****** **** * 50 4 2 **** ** ***** 70 4 2 **** ******* IC 9 4 ***** ****** *** ** *****0 * * *0** ***** **** *0 *** ** * * * Specified flag becomes "0." *** C7 10 2 D7 11 2 CD 4 3 42 12 3 42 13 3 42 6 4 C7 D7 CD DD 6 3 D9 6 3 CF 6 4 DF 7 4 42 8 4 42 8 4 42 8 5 42 9 5 DD D9 CF DF C3 5 2 D3 8 2 42 7 3 42 10 3 C3 D3 * *0* ***** **N* * * * *ZC 7721 Group User's Manual 17-43 APPENDIX Appendix 6. Machine instructions Addressing modes Symbol Functions Details IMP op IMM A DIR DIR,b DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y n # op n # op n # op n # op n # op n # op n # op n # op n # op n # E0 2 2 E4 4 2 CPX (Note 2) CPY (Note 2) DEC (Note 1) X-M Compares the contents of the index register X with the contents of the memory. Compares the contents of the index register Y with the contents of the memory. Decrements the contents of the accumlator or memory by 1. Y-M C0 2 2 C4 4 2 ACCACC-1 or MM-1 1A 2 1 C6 7 2 42 4 2 1A D6 7 2 DEX DEY DIV (Notes 2,10) XX-1 YY-1 A(quotient)B,A/M B(remainder) Decrements the contents of the index register X by 1. Decrements the contents of the index register Y by 1. The numeral that places the contents of accumlator B to the higher order and the contents of accumulator A to the lower order is divided by the contents of the memory. The quotient is entered into accumulator A and the remainder into accumulator B. Logical exclusive sum is obtained of the contents of the accumulator and the contents of the memory. The result is placed into the accumulator. CA 2 1 88 2 1 89 27 3 29 89 29 3 25 89 30 3 35 89 31 3 89 32 3 89 33 3 32 21 31 EOR (Notes 1,2) ACCACCM 49 2 2 42 4 3 49 45 4 2 42 6 3 45 3A 2 1 E6 7 2 42 4 2 3A 55 5 2 42 7 3 55 F6 7 2 52 6 2 41 7 2 51 8 2 42 8 3 42 9 3 42 10 3 51 52 41 INC (Note 1) ACCACC+1 or MM+1 Increments the contents of the accumulator or memory by 1. INX INY JMP XX+1 YY+1 ABS PCLADL PCHADH ABL PCLADL PCHADH PGADG (ABS) PCL(ADH, ADL) PCH(ADH,ADL+1) L(ABS) PCL(ADH, ADL) PCH(ADH, ADL+1) PG(ADH, ADL+2) (ABS, X) PCL(ADH, ADL+X) PCH(ADH, ADL+X +1) Increments the contents of the index register X by 1. Increments the contents of the index register Y by 1. Places a new address into the program counter and jumps to that new address. E8 2 1 C8 2 1 JSR ABS M(S)PCH SS-1 M(S)PCL SS-1 PCLADL PCHADH ABL M(S)PG SS-1 M(S)PCH SS-1 M(S)PCL SS-1 PCLADL PCHADH PGADG (ABS, X) M(S)PCH SS-1 M(S)PCL SS-1 PCL(ADH, ADL+X) PCH(ADH, ADL+X +1) Saves the contents of the program counter (also the contents of the program bank register for ABL) into the stack, and jumps to the new address. 17-44 7721 Group User's Manual APPENDIX Appendix 6. Machine instructions Addressing modes L(DIR) L(DIR),Y op Processor status register STK REL DIR,b,R ABS,b,R SR (SR),Y BLK 10 9 8 7 6 5 4 3 2 1 0 IPL N Vmx D I ZC * * * * ZC ABS ABS,b ABS,X ABS,Y ABL ABL,X (ABS) L(ABS) (ABS,X) n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # EC 4 3 ** *N* CC 4 3 * * *N * * * * *ZC CE 7 3 DE 8 3 ***N* * * * *Z* ** * N* * * ***N* 89 35 3 89 36 3 89 29 4 27 2D 37 89 31 4 89 31 4 89 31 5 89 32 5 39 3D 2F 3F 89 30 3 89 33 3 23 33 * **Z* * * *Z* * * *NV * * ** ZC 47 10 2 57 11 2 4D 4 3 42 12 3 42 13 3 42 6 4 57 47 4D EE 7 3 5D 6 3 59 6 3 4F 6 4 5F 7 4 42 8 4 42 8 4 42 8 5 42 9 5 59 5D 4F 5F FE 8 3 43 5 2 53 8 2 42 7 3 42 10 3 43 53 ***N* * * * *Z* * * *N * * * **Z* * * *N * ***N* 4C 2 3 5C 4 4 6C 4 3 DC 8 3 7C 6 3 ** *** * * * *Z* ** * **Z* * **** 20 6 3 22 8 4 FC 8 3 ** ** ** ***** 7721 Group User's Manual 17-45 APPENDIX Appendix 6. Machine instructions Addressing modes Symbol Functions Details IMP op IMM A DIR DIR,b DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y n # op n # op n # op n # op n # op n # op n # op n # op n # op n # A9 2 2 42 4 3 A9 A5 4 2 42 6 3 A5 64 4 3 B5 5 2 42 7 3 B5 74 5 3 B2 6 2 A1 7 2 B1 8 2 42 8 3 42 9 3 42 10 3 A1 B1 B2 LDA (Notes 1,2) ACCM Enters the contents of the memory into the accummulator. LDM (Note 5) LDT MIMM Enters the immediate vaiue into the memory. DTIMM Enters the immediate value into the data bank regiater. 89 5 3 C2 A2 2 2 A6 4 2 B6 5 2 LDX (Note 2) LDY (Note 2) LSR (Note 1) XM Enters the contents of the memory into index register X. YM Enters the contents of the memory into index register Y. Shifts the contents of the accumulator or the contents of the memory one bit to the right. The bit 0 of the accumulator or the memory is entered into the C flag. "0" is entered into bit 15 (bit 7 when the m flag is "1.") Multiplies the contents of accumulator A and the contents of the memory. The higher order of the result of operation are entered into accumulator B, and the lower order into accumulator A. Transmits the data block. The transmission is done from the lower order address of the block. A0 2 2 A4 4 2 4A 2 1 46 7 2 B4 5 2 56 7 2 m=0 0 b15 *** b0 C m=1 0 b7 *** b0 C B, AAVM 42 4 2 4A 89 16 3 09 89 18 3 05 89 19 3 15 89 20 3 89 21 3 89 22 3 01 11 12 MPY (Notes 2,11) MVN (Note 8) MVP (Note 9) Mn+iMm+i Mn-iMm-i Transmits the data block. Transmission is done form the higher order address of the data block. NOP ORA (Notes 1,2) PCPC+1 ACCACCVM Advances the program counter, but pertorms nothing else. EA 2 1 Logical sum per bit of the contents of the accumulator and the contents of the memory is obtained. The result is entered into the accumulator. 09 2 2 42 4 3 09 05 4 2 42 6 3 05 15 5 2 42 7 3 15 12 6 2 01 7 2 11 8 2 42 8 3 42 9 3 42 10 3 12 01 11 PEA M(S)IMM2 SS-1 M(S)IMM1 SS-1 M(S)M((DPR)+IMM +1) SS-1 M(S)M((DPR)+IMM) SS-1 EARPC+IMM2,IMM1 M(S)EARH SS-1 M(S)EARL SS-1 m=0 M(S)AH SS-1 M(S)AL SS-1 m=1 M(S)AL SS-1 The 3rd and the 2nd bytes of the instruction are saved into the stack, in this order. PEI Specifies 2 sequential bytes in the direct page in the 2nd byte of the instruction, and saves the contents into the stack. PER Regards the 2nd and 3rd bytes of the instruction as 16-bit numerals, adds them to the program counter, and saves the result into the stack. PHA Saves the contents of accumulator A into the stack. PHB m=0 M(S)BH SS-1 M(S)BL SS-1 m=1 M(S)BL SS-1 Saves the contents of accumuator B into the stack. 17-46 7721 Group User's Manual APPENDIX Appendix 6. Machine instructions Addressing modes L(DIR) L(DIR),Y op Processor status register STK REL DIR,b,R ABS,b,R SR (SR),Y BLK 10 9 8 7 6 5 4 3 2 1 0 IPL N Vmx D I ZC * **Z* ABS ABS,b ABS,X ABS,Y ABL ABL,X (ABS) L(ABS) (ABS,X) n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # BD 6 3 B9 6 3 AF 6 4 BF 7 4 42 8 4 42 8 4 42 8 5 42 9 5 BD B9 AF BF 9E 6 4 A3 5 2 B3 8 2 42 7 3 42 10 3 A3 B3 A7 10 2 B7 11 2 AD 4 3 42 12 3 42 13 3 42 6 4 A7 B7 AD 9C 5 4 ** *N* * ***** ****** ** *** ****** AE 4 3 BE 6 3 ** *N* * * **Z* AC 4 3 4E 7 3 BC 6 3 5E 8 3 * * *N* * * **Z* ***0* * * * *ZC 89 24 3 89 25 3 89 18 4 17 07 0D 89 20 4 89 20 4 89 20 5 89 21 5 1F 1D 19 0F 89 19 3 89 22 3 03 13 ** *N* * * * *Z0 54 7 3 + i !7 2 ****** ***** 44 9 3 * * * * * + i !7 2 ****** ** 07 10 2 17 11 2 0D 4 3 42 12 3 42 13 3 42 6 4 07 17 0D 1D 6 3 19 6 3 0F 6 4 1F 7 4 42 8 4 42 8 4 42 8 5 42 9 5 1D 19 0F 1F F4 5 3 03 5 2 13 8 2 42 7 3 42 10 3 03 13 ** ** ** * * ***** ***Z* *N* * *** * ***** D4 6 2 ** **** ***** 62 5 3 * *** *** **** 48 4 1 ** *** ****** 42 6 2 48 ***** * ***** 7721 Group User's Manual 17-47 APPENDIX Appendix 6. Machine instructions Addressing modes Symbol Functions Details IMP op IMM A DIR DIR,b op DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y n # op n # op n # op n # n # op n # op n # op n # op n # op n # PHD M(S)DPRH SS-1 M(S)DPRL SS-1 M(S)PG SS-1 M(S)PSH SS-1 M(S)PSL SS-1 M(S)DT SS-1 x=0 M(S)XH SS-1 M(S)XL SS-1 x=1 M(S)XL SS-1 Saves the contents of the direct page register into the stack. PHG Saves the contents of the program bank register into the stack. Saves the contents of the program status register into the stack. PHP PHT Saves the contents of the data bank register into the stack. PHX Saves the contents of the index register X into the stack. PHY x=0 M(S)YH SS-1 M(S)YL SS-1 x=1 M(S)YL SS-1 Saves the contents of the index register Y into the stack. PLA m=0 SS+1 ALM(S) SS+1 AHM(S) m=1 SS+1 ALM(S) Restores the contents of the stack on the accumulator A. PLB m=0 SS+1 BLM(S) SS+1 BHM(S) m=1 SS+1 BLM(S) Restores the contents of the stack on the accumulator B. PLD SS+1 DPRLM(S) SS+1 DPRHM(S) SS+1 PSLM(S) SS+1 PSHM(S) SS+1 DTM(S) x=0 SS+1 XLM(S) SS+1 XHM(S) x=1 SS+1 XLM(S) Restores the contents of the stack on the direct page register. PLP Restores the contents of the stack on the processor status register. PLT Restores the contents of the stack on the data bank register. Restores the contents of the stack on the index register X. PLX 17-48 7721 Group User's Manual APPENDIX Appendix 6. Machine instructions Addressing modes L(DIR) L(DIR),Y op Processor status register STK REL DIR,b,R ABS,b,R SR (SR),Y BLK 10 9 8 7 6 5 4 3 2 1 0 IPL NVm x D IZ C * **** ABS ABS,b ABS,X ABS,Y ABL ABL,X (ABS) L(ABS) (ABS,X) n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 0B 4 1 ****** 4B 3 1 ****** ****** * * **** **** 08 4 1 8B 3 1 ****** * **** DA 4 1 ****** * **** 5A 4 1 ****** * **** 68 5 1 * * *N * * * * *Z* 42 7 2 68 * * *N * * * * *Z* 2B 5 1 ****** * **** 28 6 1 Value saved in stack. AB 6 1 * * *N * * * * *Z* FA 5 1 * * *N * * * * *Z* 7721 Group User's Manual 17-49 APPENDIX Appendix 6. Machine instructions Addressing modes Symbol Functions Details IMP op IMM A DIR DIR,b op DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y n # op n # op n # op n # n # op n # op n # op n # op n # op n # PLY x=0 SS+1 YLM(S) SS+1 YHM(S) x=1 SS+1 YLM(S) Restores the contents of the stack on the index register Y. PSH (Note 6) M(S)A, B, X*** Saves the registers among accumulator, index register, direct page register, data bank register, program bank register, or processor status register, specified by the bit pattern of the second byte of the instruction into the stack. Restores the contents of the stack to the registers among accumulator, index register, direct page register, data bank register, or processor status register, specified by the bit pattern of the second byte of the instruction. Rotates the contents of the accumulator A, n bits to the left. 89 6 3 49 + i PUL (Note 7) A, B, X***M(S) RLA (Note 13) m=0 n bit rotate left b15 *** b0 m=1 n bit rotate left b7 *** b0 ROL (Note 1) m=0 b15 *** b0 C m=1 b7 *** b0 C Links the accumulator or the memory to C flag, and rotates result to the left by 1 bit. 2A 2 1 26 7 2 42 4 2 2A 36 7 2 ROR (Note 1) m=0 C b15 *** b0 m=1 C b7 *** b0 Links the accumulator or the memory to C flag, and rotates result to the right by 1 bit. 6A 2 1 66 7 2 42 4 2 6A 76 7 2 RTI SS+1 PSLM(S) SS+1 PSHM(S) SS+1 PCLM(S) SS+1 PCHM(S) SS+1 PGM(S) SS+1 PCLM(S) SS+1 PCHM(S) SS+1 PGM(S) SS+1 PCLM(S) SS+1 PCHM(S) ACC, CACC-M-C Returns from the interruption routine. 40 11 1 RTL Returns from the subroutine. The contents of the program 6B 8 1 bank register are also restored. RTS Returns from the subroutine. The contents of the program 60 5 1 bank register are not restored. SBC (Notes 1,2) Subtracts the contents of the memory and the borrow from the contents of the accumulator. E9 2 2 42 4 3 E9 E5 4 2 42 6 3 E5 F5 5 2 42 7 3 F5 F2 6 2 E1 7 2 F1 8 2 42 8 3 42 9 3 42 10 3 F2 E1 F1 17-50 7721 Group User's Manual APPENDIX Appendix 6. Machine instructions Addressing modes L(DIR) L(DIR),Y op Processor status register STK REL DIR,b,R ABS,b,R SR (SR),Y BLK 10 9 8 7 6 5 4 3 2 1 0 IPL NVm x D IZ C ABS ABS,b ABS,X ABS,Y ABL ABL,X (ABS) L(ABS) (ABS,X) n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 7A 5 1 * * *N * * * * *Z* EB 12 2 + ****** * **** 2i1+i2 FB 14 2 3i1+4i2 + If restored the contents of PS, it becomes its value. And the other cases are no change. ****** * **** 2E 7 3 3E 8 3 * * * N * * * * *ZC 6E 7 3 7E 8 3 * * * N * * * * *ZC Value saved in stack. ****** * ** ** ****** * ** ** E7 10 2 F7 11 2 ED 4 3 42 12 3 42 13 3 42 6 4 E7 F7 ED FD 6 3 F9 6 3 EF 6 4 FF 7 4 42 8 4 42 8 4 42 8 5 42 9 5 FD F9 EF FF E3 5 2 F3 8 2 42 7 3 42 10 3 F3 E3 * * * NV * * * *ZC 7721 Group User's Manual 17-51 APPENDIX Appendix 6. Machine instructions Addressing modes Symbol Functions Details IMP op IMM A DIR DIR,b op DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y n # op n # op n # op n # n # op n # op n # op n # op n # op n # SEB (Note 5) SEC SEI SEM SEP Mb1 Makes the contents of the specified bit in the memory "1." 04 8 3 C1 I1 m1 PSb1 Makes the contents of the C flag "1." Makes the contents of the I flag "1." Makes the contents of the m flag "1." Set the specified bit of the processor status register's lower byte (PSL) to "1." Stores the contents of the accumulator into the memory. 38 2 1 78 2 1 F8 2 1 E2 3 2 STA (Note 1) MACC 85 4 2 42 6 3 85 95 5 2 42 7 3 95 92 7 2 81 7 2 91 7 2 42 9 3 42 9 3 42 9 3 92 81 91 STP STX STY TAD MX MY DPRA Stops the oscillation of the oscillator. Stores the contents of the index register X into the memory. Stores the contents of the index register Y into the memory. DB 3 1 86 4 2 84 4 2 94 5 2 96 5 2 Transmits the contents of the accumulator A to the direct 5B 2 1 page register. Transmits the contents of the accumulator A to the stack pointer. 1B 2 1 TAS TAX SA XA Transmits the contents of the accumulator A to the index AA 2 1 register X. Transmits the contents of the accumulator A to the index A8 2 1 register Y. Transmits the contents of the accumulator B to the direct 42 4 2 page register. 5B Transmits the contents of the accumulator B to the stack 42 4 2 pointer. 1B Transmits the contents of the accumulator B to the index 42 4 2 register X. AA Transmits the contents of the accumulator B to the index 42 4 2 register Y. A8 Transmits the contents of the direct page register to the 7B 2 1 accumulator A. Transmits the contents of the direct page register to the 42 4 2 accumulator B. 7B Transmits the contents of the stack pointer to the accumulator A. Transmits the contents of the stack pointer to the accumulator B. 3B 2 1 42 4 2 3B TAY YA TBD DPRB TBS SB TBX TBY XB YB TDA ADPR TDB BDPR AS BS TSA TSB TSX TXA XS AX Transmits the contents of the stack pointer to the index BA 2 1 register X. Transmits the contents of the index register X to the accumulator A. Transmits the contents of the index register X to the accumulator B. Transmits the contents of the index register X to the stack pointer. 8A 2 1 TXB TXS BX SX 42 4 2 8A 9A 2 1 TXY YX Transmits the contents of the index register X to the index 9B 2 1 register Y. Transmits the contents of the index register Y to the ac- 98 2 1 cumulator A. Transmits the contents of the index register Y to the accumulator B. 42 4 2 98 TYA AY TYB BY TYX WIT XAB XY Transmits the contents of the index register Y to the index BB 2 1 register X. Stops the internal clock. CB 3 1 A B Exchanges the contents of the accumulator A and the con- 89 6 2 tents of the accumulator B. 28 17-52 7721 Group User's Manual APPENDIX Appendix 6. Machine instructions Addressing modes L(DIR) L(DIR),Y op Processor status register STK REL DIR,b,R ABS,b,R SR (SR),Y BLK 10 9 8 7 6 5 4 3 2 1 0 IPL NVm x D IZ C * **** ABS ABS,b ABS,X ABS,Y ABL ABL,X (ABS) L(ABS) (ABS,X) n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 0C 9 4 ****** ****** ****** *****1 * * * ***1 *1** **** * * * Specified flag * * * * * * * * becomes "1." 87 10 2 97 11 2 8D 5 3 42 12 3 42 13 3 42 7 4 97 87 8D 9D 5 3 99 5 3 8F 6 4 9F 7 4 42 7 4 42 7 4 42 8 5 42 9 5 9D 99 9F 8F 83 5 2 93 8 2 42 7 3 42 10 3 83 93 ****** 8E 5 3 8C 5 3 ****** ****** ****** * * * * **** **** **** **** ****** * **** ****** * **** * * *N * * * * *Z* * * *N * * * * *Z* ****** * **** ****** * **** * * * N * * * * *Z* * * * N * * * * *Z* * * * N * * * * *Z* * * * N * * * * *Z* * * * N * * * * *Z* * * * N * * * * *Z* * * * N * * * * *Z* * * * N * * * * *Z* * * * N * * * * *Z* ****** * **** * * * N * * * * *Z* * * * N * * * * *Z* * * * N * * * * *Z* * * * N * * * * *Z* ****** * **** * * *N * * * * *Z* 7721 Group User's Manual 17-53 APPENDIX Appendix 6. Machine instructions The number of cycles shown in the table is described in the case of the fastest mode for each instruction. The number of cycles shown in the table is calculated for DPRL=0. The number of cycles in the addressing mode concerning the DPR when DPRL 0 must be incremented by 1. The number of cycles shown in the table differs according to the bytes fetched into the instruction queue buffer, or according to whether the memory read/write address is odd or even. It also differs when the external region memory is accessed by BYTE="H." Notes 1. The operation code at the upper row is used for accumulator A, and the operation at the lower row is used for accumulator B. 2. When setting flag m=0 to handle the data as 16-bit data in the immediate addressing mode, the number of bytes increments by 1. 3. The number of cycles increments by 2 when branching. 4. The operation code on the upper row is used for branching in the range of -128 to +127, and the operation code on the lower row is used for branching in the range of -32768 to +32767. 5. When handling 16-bit data with flag m=0, the byte in the table is incremented by 1. 6. Type of register Number of cycles A 2 B 2 X 2 Y 2 DPR 2 DT 1 PG 1 PS 2 The number of cycles corresponding to the register to be pushed are added. The number of cycles when no pushing is done is 12. i1 indicates the number of registers among A, B, X, Y, DPR, and PS to be saved, while i2 indicates the number of registers among DT and PG to be saved. 7. Type of register Number of cycles A 3 B 3 X 3 Y 3 DPR 4 DT 3 PS 3 The number of cycles corresponding to the register to be pulled are added. The number of cycles when no pulling is done is 14. i1 indicates the number of registers among A, B, X, Y, DT, and PS to be restored, while i2=1 when DPR is to be restored. 8. The number of cycles is the case when the number of bytes to be transferred is even. When the number of bytes to be transferred is odd, the number is calculated as; 7 + (i/2) ! 7 + 4 Note that, (i/2) shows the integer part when i is divided by 2. 9. The number of cycles is the case when the number of bytes to be transferred is even. When the number of bytes to be transferred is odd, the number is calculated as; 9 + (i/2) ! 7 + 5 Note that, (i/2) shows the integer part when i is divided by 2. 10. The number of cycles is the case in the 16-bit / 8-bit operation. The number of cycles is incremented by 16 for 32-bit / 16bit operation. 11. The number of cycles is the case in the 8-bit ! 8-bit operation. The number of cycles is incremented by 8 for 16-bit ! 16bit operation. 12. When setting flag x=0 to handle the data as 16-bit data in the immediate addressing mode, the number of bytes increments by 1. 13. When flag m is 0, the byte in the table is incremented by 1. 17-54 7721 Group User's Manual APPENDIX Appendix 6. Machine instructions Symbols in machine instructions table Symbol IMP IMM A DIR DIR, b DIR, X DIR, Y (DIR) (DIR,X) (DIR), Y L (DIR) L (DIR),Y ABS ABS, b ABS, X ABS, Y ABL ABL, X (ABS) L (ABS) (ABS, X) STK REL DIR, b, REL ABS, b, REL SR (SR), Y BLK C Z I D x m V N IPL Description Implied addressing mode Immediate addressing mode Accumulator addressing mode Direct addressing mode Direct bit addressing mode Direct indexed X addressing mode Direct indexed Y addressing mode Direct indirect addressing mode Direct indexed X indirect addressing mode Direct indirect indexed Y addressing mode Direct indirect long addressing mode Direct indirect long indexed Y addressing mode Absolute addressing mode Absolute bit addressing mode Absolute indexed X addressing mode Absolute indexed Y addressing mode Absolute long addressing mode Absolute long indexed X addressing mode Absolute indirect addressing mode Absolute indirect long addressing mode Absolute indexed X indirect addressing mode Stack addressing mode Relative addressing mode Direct bit relative addressing mode Absolute bit relative addressing mode Stack pointer relative addressing mode Stack pointer relative indirect indexed Y addressing mode Block transfer addressing mode Carry flag Zero flag Interrupt disable flag Decimal operation mode flag Index register length selection flag Data length selection flag Overflow flag Negative flag Processor interrupt priority level Addition Subtraction Multiplication Division Logical AND Logical OR Symbol Description Exclusive OR Negation Movement to the arrow direction Accumulator Accumulator's upper 8 bits Accumulator's lower 8 bits Accumulator A Accumulator A's upper 8 bits Accumulator A's lower 8 bits Accumulator B Accumulator B's upper 8 bits Accumulator B's lower 8 bits Index register X Index register X's upper 8 bits Index register X's lower 8 bits Index register Y Index register Y's upper 8 bits Index register Y's lower 8 bits Stack pointer Program counter Program counter's upper 8 bits Program counter's lower 8 bits Program bank register Data bank register Direct page register Direct page register's upper 8 bits Direct page register's lower 8 bits Processor status register Processor status register's upper 8 bits Processor status register's lower 8 bits Processor status register's b-th bit Contents of memory at address indicated by stack pointer b-th memory location Value of 24-bit address's upper 8-bit (A23-A16) Value of 24-bit address's middle 8-bit (A15-A8) Value of 24-bit address's lower 8-bit (A7-A0) Operation code Number of cycle Number of byte Number of transfer byte or rotation Number of registers pushed or pulled - ACC ACCH ACCL A AH AL B BH BL X XH XL Y YH YL S PC PCH PCL PG DT DPR DPRH DPRL PS PSH PSL PSb M(S) Mb ADG ADH ADL op n # i i1, i2 + - V / 7721 Group User's Manual 17-55 APPENDIX Appendix 7. Hexadecimal instruction code table Appendix 7. Hexadecimal instruction code table INSTRUCTION CODE TABLE-1 D3-D0 Hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 D7-D4 0 1 ORA 2 3 ORA A,SR 4 SEB DIR,b CLB 5 ORA A,DIR ORA A,DIR,X AND A,DIR AND 6 ASL DIR ASL 7 ORA 8 9 ORA A ASL B C SEB D ORA E ASL ABS ASL F ORA A,ABL ORA 0000 0 BRK A,(DIR,X) ORA ORA A,L(DIR) ORA ORA PHP A,IMM ORA CLC A,(DIR),Y A,(DIR) A,(SR),Y DIR,b DIR,X A,L(DIR),Y ROL DIR ROL AND PLP A,L(DIR) AND SEC A,(DIR),Y A,(DIR) A,(SR),Y DIR,b,R A,DIR,X EOR EOR Note 1 EOR MVP A,SR EOR MVN A,(DIR),Y A,(DIR) A,(SR),Y ADC ADC PER A,(DIR,X) ADC ADC A,SR ADC DIR LDM A,DIR ADC DIR ROR A,L(DIR) ADC SEI A,(DIR),Y A,(DIR) A,(SR),Y DIR,X A,DIR,X STA A,(DIR,X) STA BRA REL STA STA A,SR STA STY DIR STY STA A,DIR STA DIR,X A,L(DIR),Y STX STA DEY DIR STX A,L(DIR) STA TYA A,(DIR),Y A,(DIR) A,(SR),Y DIR,X A,DIR,X LDA A,(DIR,X) LDA LDX IMM LDA LDA A,SR LDA LDY DIR LDY LDA A,DIR LDA DIR,Y A,L(DIR),Y LDX LDA TAY DIR LDX A,L(DIR) LDA CLV A,(DIR),Y A,(DIR) A,(SR),Y DIR,X A,DIR,X CMP A,(DIR,X) CMP CLP IMM CMP CMP A,SR CMP PEI A,(DIR),Y A,(DIR) A,(SR),Y A,DIR,X CPX DIR PEA SBC A,DIR SBC A,DIR,X DIR,X A,L(DIR),Y INC DIR INC SBC A,L(DIR) SBC SEM INX SBC A,(DIR,X) SBC SEP IMM SBC SBC A,SR SBC CPY DIR CMP A,DIR CMP DIR,Y A,L(DIR),Y DEC CMP INY DIR DEC A,L(DIR) CMP CLM A,ABS,Y SBC A,IMM SBC A,ABS,Y PLX NOP A,ABS,Y CMP DEX A,IMM CMP PHX A,ABS,Y LDA TAX A,IMM LDA TSX A,ABS,Y Note 2 STA TXS TXA LDM A,DIR,X ADC DIR,X A,L(DIR),Y ROR ADC PLA A,IMM ADC PLY A A,DIR EOR DIR LSR A,L(DIR) EOR CLI A,ABS,Y ADC ROR EOR DIR,X A,L(DIR),Y LSR EOR PHA A,IMM EOR PHY A A,ABS,Y EOR A LSR A,ABS,Y AND A,IMM AND A ROL AND A,(DIR,X) AND JSR ABL AND AND A,SR AND BBS DIR,b,R BBC A DEC PHD ABS,b A,ABS CLB TAS ABS,b A,ABS,X ABS,X A,ABL,X BBS PLD A INC TSA ABS,b,R A,ABS,X ABS,X A,ABL,X JMP PHG ABS JMP TAD ABL JMP RTL (ABS) A,ABS JMP TDA (ABS,X) A,ABS,X ABS,X A,ABL,X STY PHT ABS LDM TXY ABS LDY PLT ABS LDY TYX ABS,X A,ABS,X ABS,Y A,ABL,X CPY WIT ABS JMP STP L(ABS) A,ABS,X ABS,X A,ABL,X CPX PSH ABS JSR PUL SBC A,ABS SBC INC ABS INC SBC A,ABL SBC A,ABS CMP ABS DEC A,ABL CMP CMP DEC CMP A,ABS LDA ABS LDX A,ABL LDA A,ABS,X ABS,X A,ABL,X LDA LDX LDA A,ABS STA ABS LDM A,ABL STA STA STX STA ADC ABS ROR A,ABL ADC A,ABS,X ABS,X A,ABL,X ADC ROR ADC A,ABS EOR ABS LSR A,ABL EOR EOR LSR EOR ABS,b,R A,ABS BBC AND ABS ROL A,ABL AND AND ROL AND ORA 0001 1 BPL JSR 0010 2 ABS 0011 3 BMI 0100 4 RTI A,(DIR,X) EOR 0101 5 BVC 0110 6 RTS 0111 7 BVS BRA 1000 8 REL 1001 9 BCC LDY 1010 A IMM 1011 B BCS CPY 1100 C IMM 1101 D BNE CPX 1110 E IMM BEQ 1111 F A,(DIR),Y A,(DIR) A,(SR),Y DIR,X A,L(DIR),Y (ABS,X) A,ABS,X ABS,X A,ABL,X Notes 1: 4216 specifies the contents of the INSTRUCTION CODE TABLE-2. About the second word's codes, refer to the INSTRUCTION CODE TABLE-2. 2: 8916 specifies the contents of the INSTRUCTION CODE TABLE-3. About the second word's codes, refer to the INSTRUCTION CODE TABLE-2. 17-56 7721 Group User's Manual APPENDIX Appendix 7. Hexadecimal instruction code table INSTRUCTION CODE TABLE-2 (The first word's code of each instruction is 4216) D3-D0 Hexadecimal notation 0 B,(DIR,X) ORA 0001 1 B,(DIR),Y B,(DIR) B,(SR),Y AND 0010 2 B,(DIR,X) AND 0011 3 B,(DIR),Y B,(DIR) B,(SR),Y EOR 0100 4 B,(DIR,X) EOR 0101 5 B,(DIR),Y B,(DIR) B,(SR),Y ADC 0110 6 B,(DIR,X) ADC 0111 7 B,(DIR),Y B,(DIR) B,(SR),Y STA 1000 8 B,(DIR,X) STA 1001 9 B,(DIR),Y B,(DIR) B,(SR),Y LDA 1010 A B,(DIR,X) LDA 1011 B B,(DIR),Y B,(DIR) B,(SR),Y CMP 1100 C B,(DIR,X) CMP 1101 D B,(DIR),Y B,(DIR) B,(SR),Y SBC 1110 E B,(DIR,X) SBC 1111 F SBC SBC B,SR SBC B,DIR,X SBC B,DIR SBC B,DIR,X B,L(DIR),Y 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 D7-D4 0 1 ORA 2 3 ORA B,SR 4 5 ORA B,DIR ORA B,DIR,X AND B,DIR AND B,DIR,X EOR B,DIR EOR B,DIR,X ADC B,DIR ADC B,DIR,X STA B,DIR STA B,DIR,X LDA B,DIR LDA B,DIR,X CMP B,DIR CMP 6 7 ORA B,L(DIR) ORA B,L(DIR),Y 8 9 ORA B,IMM ORA B,ABS,Y AND B,IMM AND B,ABS,Y EOR A ASL B DEC B C D ORA B,ABS ORA E F ORA B,ABL ORA B,ABL,X AND B,ABL AND B,ABL,X EOR B,ABL EOR B,ABL,X ADC B,ABL ADC B,ABL,X STA B,ABL STA B,ABL,X LDA B,ABL LDA B,ABL,X CMP B,ABL CMP B,ABL,X SBC B,ABL SBC B,ABL,X 0000 ORA ORA TBS B ROL B INC TSB B,L(DIR),Y B,ABS,X AND B,ABS AND B,ABS,X EOR B,ABS EOR TBD B,ABS,X AND B,SR AND AND AND B,L(DIR) AND B LSR B EOR B,SR EOR EOR EOR PHB B,L(DIR) EOR B,L(DIR),Y B,IMM EOR B,ABS,Y ADC PLB B,IMM ADC ADC B,SR ADC ADC ADC B,L(DIR) ADC B,L(DIR),Y ROR B TDB ADC B,ABS ADC B,ABS,X STA B,ABS,Y TXB STA B,SR STA STA STA B,L(DIR) STA TYB B,L(DIR),Y B,ABS STA B,ABS,Y LDA TBY B,IMM LDA B,ABS,Y CMP B,IMM CMP B,ABS,Y SBC B,IMM SBC B,ABS,Y TBX STA B,ABS,X LDA B,ABS LDA B,ABS,X CMP B,ABS CMP B,ABS,X SBC B,ABS SBC B,ABS,X LDA B,SR LDA LDA LDA B,L(DIR) LDA B,L(DIR),Y CMP B,SR CMP CMP CMP B,L(DIR) CMP SBC B,L(DIR) SBC B,L(DIR),Y B,(DIR),Y B,(DIR) B,(SR),Y 7721 Group User's Manual 17-57 APPENDIX Appendix 7. Hexadecimal instruction code table INSTRUCTION CODE TABLE-3 (The first word's code of each instruction is 8916) D3-D0 Hexadecimal notation 0 (DIR,X) MPY 0001 1 (DIR),Y (DIR) DIV 0010 2 (DIR,X) DIV 0011 3 (DIR),Y (DIR) 0100 4 IMM 0101 5 (SR),Y DIR,X L(DIR),Y ABS,Y RLA ABS,X ABL,X DIV SR DIV DIR DIV L(DIR) DIV (SR),Y DIV DIR,X DIV L(DIR),Y DIV XAB IMM DIV ABS DIV ABL DIV ABS,Y DIV ABS,X DIV ABL,X DIV MPY SR MPY DIR MPY L(DIR) MPY IMM MPY ABS MPY ABL MPY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 D7-D4 0 1 MPY 2 3 MPY 4 5 MPY 6 7 MPY 8 9 MPY A B C D MPY E F MPY 0000 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B LDT 1100 C IMM 1101 D 1110 E 1111 F 17-58 7721 Group User's Manual APPENDIX Appendix 8. Countermeasure against noise Appendix 8. Countermeasure against noise General countermeasure examples against noise are described below. Although the effect of these countermeasure depends on each system, refer to the following when an noise-related problem occurs. 1. Short wiring length The wiring on a printed circuit board may function as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less possibility of noise insertion into the microcomputer. ______ (1) Wiring for RESET pin ______ Make the length of wiring connected to the RESET pin as short as possible. ______ In particular, connect a capacitor between the RESET pin and the Vss pin with the shortest possible wiring (within 20 mm). ______ Reason: If noise is input to the RESET pin, the microcomputer restarts operation before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise M37721 M37721 Reset circuit Vss RESET Reset circuit Vss RESET Vss Vss Not acceptable Fig. 3 Wiring for RESET pin ______ Acceptable (2) Wiring for clock input/output pins q Make the length of wiring connected to the clock input/output pins as short as possible. q Make the length of wiring between the grounding lead of the capacitor, which is connected to the oscillator, and the Vss pin of the microcomputer, as short as possible (within 20 mm). q Separate the Vss pattern for oscillation from all other Vss patterns. (Refer to "Figure 11.") Reason: The microcomputer's operation synchronizes with a clock generated by the oscillation circuit. If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a malfunction or a program runaway. Also, if the noise causes a potential difference between the Vss level of the microcomputer and the Vss level of an oscillator, the correct clock will not be input in the microcomputer. Noise M37721 M37721 XIN XOUT Vss XIN XOUT Vss Not acceptable Acceptable Fig. 4 Wiring for clock input/output pins 7721 Group User's Manual 17-59 APPENDIX Appendix 8. Countermeasure against noise (3) Wiring for CNVss pin Connect CNVss pin to the Vss pin with the shortest possible wiring. Reason: The processor mode of the microcomputer is influenced by a potential at the CNVss pin when the CNVss pin and the Vcc or Vss pin are connected. If the noise causes a potential difference between the CNVss pin and the Vss or Vcc pin, the processor mode may become unstable. This may cause a microcomputer malfunction or a program runaway. M37721 Noise M37721 CNVss Vss CNVss Vss Not Acceptable Acceptable When connecting th e C NVss and Vcc pins, connect them in the shortest possible distance, also. Fig. 5 Wiring for CNVss pin 2. Connection of bypass capacitor between Vss and Vcc lines Connect an approximate 0.1 F bypass capacitor as follows: q Connect a bypass capacitor between the Vss and Vcc pins, at equal lengths. q The wiring connecting the bypass capacitor between the Vss and Vcc pins should be as short as possible. q Use thicker wiring for the Vss and Vcc lines than that for the other signal lines. Bypass capacitor Wiring pattern Wiring pattern Vss Vcc M37721 Fig. 6 Bypass capacitor between Vss and Vcc lines 17-60 7721 Group User's Manual APPENDIX Appendix 8. Countermeasure against noise 3. Wiring for analog input pins, analog power source pins, etc. (1) Processing for analog input pins q Connect a resistor to the analog signal line, which is connected to an analog input pin, in series. Additionally, connect the resistor to the microcomputer as close as possible. q Connect a capacitor between the analog input pin and the AVss pin, as close to the AVss pin as possible. Reason: A signal which is input to the analog input pin is usually an output signal from a sensor. The sensor, which detects changes in status, is installed far from the microcomputer's printed circuit board. Therefore, this long wiring between them becomes an antenna which picks up noise and feeds it into the microcomputer's analog input pin. If a capacitor between an analog input pin and the AVss pin is grounded far away from the AVss pin, noise on the GND line may enter the microcomputer through the capacitor. Noise (Note 2) Acceptable M37721 ANi RI Thermistor Not CI acceptable Acceptable AVss Reference values RI : Approximate 100 to 1000 CI : Approximate 100 pF to 1000 pF Notes 1 : Design an external circuit for the ANi pin so that charge/discharge is available within 1 cycle of AD. 2 : This resistor and thermistor are used to divide resistance. Fig. 7 Countermeasure example against noise for analog input pin using thermistor 7721 Group User's Manual 17-61 APPENDIX Appendix 8. Countermeasure against noise (2) Processing for analog power source pins, etc. q Use independent power sources for the Vcc, AVcc and VREF pins. q Insert capacitors between the AVcc and AVss pins, and between the VREF and AVss pins. Reasons: Prevents the A-D converter from noise on the Vcc line. M37721 AVcc VREF C1 AVss ANi (sensor, etc.) C2 Note : Connect capacitors using the thickest, shortest wiring possible. Reference values C1 0.47 F C2 0.47 F Fig. 8 Processing for analog power source pins, etc. 17-62 7721 Group User's Manual APPENDIX Appendix 8. Countermeasure against noise 4. Oscillator protection The oscillator, which generates the basic clock for the microcomputer operations, must be protected from the affect of other signals. (1) Distance oscillator from signal lines with large current flows Install the microcomputer, especially the oscillator, as far as possible from signal lines which handle currents larger than the microcomputer current value tolerance. Reason: The microcomputer is used in systems which contain signal lines for controlling motors, LEDs, thermal heads, etc. Noise occurs due to mutual inductance when a large current flows through the signal lines. M37721 Mutual inductance M XIN XOUT Vss Large current Fig. 9 Wiring for signal lines where large current flows (2) Distance oscillator from signal lines with frequent potential level changes q Install an oscillator and its wiring pattern away from signal lines where potential levels change frequently. q Do not cross these signal lines over the clock-related or noise-sensitive signal lines. Reason: Signal lines with frequently changing potential levels may affect other signal lines at a rising or falling edge. In particular, if the lines cross over a clock-related signal line, clock waveforms may be deformed, which causes a microcomputer malfunction or a program runaway. M37721 Do not cross. V XIN XOUT Vss V I/O pin for signal with frequently changing potential levels Fig. 10 Wiring for signal lines where potential levels frequently change (3) Oscillator protection using Vss pattern Print a Vss pattern on the bottom (soldering side) of a double-sided printed circuit board, under the oscillator mount position. Connect the Vss pattern to the Vss pin of the microcomputer with the shortest possible wiring, separating it from other Vss patterns. An example of Vss pattern on the underside of an oscillator. M37721 Mounted pattern example of oscillator unit. XIN XOUT Vss Separate Vss lines for oscillation and supply. Fig. 11 Vss pattern underneath mounted oscillator 7721 Group User's Manual 17-63 APPENDIX Appendix 8. Countermeasure against noise 5. Setup for I/O ports Setup I/O ports by hardware and software as follows: Data bus Direction register Noise Port latch Port Fig. 12 Setup for I/O ports 6. Reinforcement of the power source line q For the Vss and Vcc lines, use thicker wiring than that of other signal lines. q When using a multilayer printed circuit board, the Vss and Vcc patterns must each be one of the middle layers. q The following is necessary for double-sided printed circuit boards: *On one side, the microcomputer is installed at the center, and the Vss line is looped or meshed around it. The vacant area is filled with the Vss line. *On the opposite side, the Vcc line is wired the same as the Vss line. *The power source lines of external devices which are connected by bus to the microcomputer must be connected to the microcomputer's power source lines with the shortest possible wiring. Reasons: With external devices connected to the microcomputer, the levels of many of the signal lines (total external address buses: 24 bits) may change simultaneously, causing noise on the power source line. 17-64 7721 Group User's Manual APPENDIX Appendix 9. 7721 Group Q & A Appendix 9. 7721 Group Q & A Information which may be helpful in fully utilizing the 7721 Group is provided in Q & A format. In Q & A, as a rule, one question and its answer are summarized within one page. The upper box on each page is a question, and a box below the question is its answer. (If a question or an answer extends to two or more pages, there is a page number at the lower right corner.) At the upper right corner of each page, the main function related to the contents of description in that page is listed. 7721 Group User's Manual 17-65 APPENDIX Appendix 9. 7721 Group Q & A SFR Q Is there any SFR to which a certain instruction cannot be used for writing ? A (1) Use the LDM or STA instruction to write to the registers or the bits listed below. Do not use read-modify-write instructions (i.e., CLB, SEB, ASL, ASR, DEC, INC, LSR, ROL, and ROR). Pulse output data register 0, 1 (addresses 1A16, 1C16) UART0, 1 baud rate register (addresses 3116, 3916) UART0, 1 transmit buffer register (addresses 3316, 3216, 3B16, 3A16) Timer A2-A4 two-phase pulse signal processing select bit (bits 5-7 at address 4416) Timer A2-A4 register (addresses 4A16-4F16 ; one-shot pulse mode or pulse width modulation mode) Refresh timer (address 6616) (2) Use the SEB or CLB instruction to write to the following register. DMAC control register H (address 6916 ; when any of bits 4 to 7 = "1") 17-66 7721 Group User's Manual APPENDIX Appendix 9. 7721 Group Q & A Reset, STP instruction, WIT instruction Q Is it possible to distinguish power-on reset from hardware reset for terminating the stop or wait mode ? A The contents of the internal RAM is undefined after power-on reset. On the other hand, the contents of the internal RAM are retained when performing hardware reset in the stop or wait mode with Vcc 2 V. Accordingly, write a certain data to the internal RAM before executing STP or WIT instruction, and judge by checking the contents of the internal RAM after hardware reset. 7721 Group User's Manual 17-67 APPENDIX Appendix 9. 7721 Group Q & A Interrupt Q If an interrupt request (b) occurs while executing an interrupt routine (a), is it true that the main routine is not executed at all from when the execution of the interrupt routine (a) is completed until the execution of the INTACK sequence for the next interrupt (b) starts? Sequence of execution RTI instruction Interrupt routine (a) ? Main routine INTACK sequence for interrupt (b) Conditions: q I is cleared to "0" by executing the RTI instruction. q Iinterrupt priority level of interrupt (b) is higher than IPL of main routine. q Interrupt priority detection time is 2 cycles of . A Sampling for interrupt requests is performed by sampling pulses generated synchronously with the CPU's op-code fetch cycles. for the RTI instruction is gener(1) If the next interrupt request (b) occurs before sampling pulse ated, the microcomputer executes the INTACK sequence for (b) without executing the main routine (not even one instruction). It is because that sampling is completed while executing the RTI instruction. Interrupt request (b) Sampling pulse RTI instruction Interrupt routine (a) INTACK sequence for interrupt (b) (2) If the next interrupt request (b) occurs immediately after sampling pulse is generated, the microcomputer executes one instruction of the main routine before executing the INTACK sequence for (b). It is because that the interrupt request is sampled by the next sampling pulse . Interrupt request (b) Sampling pulse RTI instruction One instruction executed Interrupt routine (a) Main routine INTACK sequence for interrupt (b) 17-68 7721 Group User's Manual APPENDIX Appendix 9. 7721 Group Q & A Interrupt Q Suppose that there is a routine which should not accept one certain interrupt request. (The other interrupt request are acceptable). Although when the interrupt priority level select bits for the above interrupt are set to "0002," in other words, when this interrupt is set to be disabled, this interrupt request is actually accepted immediately after change of the priority level. Why did this occur and what should I do about it? Interrupt request is accepted in this interval : LDM #00H, XXXIC ; Writes "0002" to interrupt priority level select bits. ; Clears interrupt request bit to "0." LDA A,DATA ; Instruction at the beginning of the routine which should not accept one certain interrupt request. : ; A As for the change of the interrupt priority level, when the following are met, the microcomputer may pretend to accept an interrupt request immediately after this interrupt is set to be disabled: *The next instruction (in the above example, it is the LDA instruction) is already stored into a instruction queue buffer for the BIU. *Conditions for accepting the instruction which should not be accepted are satisfied immediately before the next instruction in the instruction queue buffer is executed. When writing to a memory or an I/O, the CPU passes the address and data to the BIU. Then, the CPU executes the next instruction in the instruction queue buffer while the BIU is writing data into the actual address. Detection of interrupt priority level is performed at the beginning of each instruction. In the above case, the CPU executes the next instruction before the BIU completes the change of the interrupt priority level. Therefore, when the interrupt priority level is detected synchronously with the execution of the next instruction, the interrupt priority level before the change is detected and its interrupt request is accepted. Interrupt request generated Sequence of execution Interrupt priority detection time CPU operation BIU operation Previous instruction executed LDM instruction executed LDA instruction executed Interrupt request accepted (Instruction prefetched) Interrupt priority level select bits set Change of interrupt priority levels completed (1/2) 7721 Group User's Manual 17-69 APPENDIX Appendix 9. 7721 Group Q & A Interrupt A To prevent this problem, after change of the interrupt priority level is completed, use software to execute the routine that should not accept a certain interrupt request. The following shows a sample program. [ Sample program ] After an instruction which writes "0002" to the interrupt priority level select bits, fill the instruction queue buffer with the NOP instruction to make the next instruction not to be executed before the writing is completed. : LDM #00H, XXXIC NOP NOP NOP LDA A,DATA : ; Sets the interrupt priority level select bits to "0002." ; ; ; ; Instruction at the beginning of the routine that should not accept a certain interrupt request (2/2) 17-70 7721 Group User's Manual APPENDIX Appendix 9. 7721 Group Q & A Interrupt Q (1) Which timing of clock 1 is the external interrupts (input signals to the INTi pin) detected? ____ (2) How can four or more external interrupt input pins (INTi) be used? ____ A (1) In both the edge sense and level sense, external interrupt requests occur when the input ____ signal to the INTi pin changes its level. This is independent of clock 1. In the edge sense, the interrupt request bit is set to "1" at this time. (2) There are two methods: one uses external interrupt's level sense, and the other uses the timer's event counter mode. Method using external interrupt's level sense As for hardware, input a logical sum of multiple interrupt signals (e.g., `a', `b', and `c') to the ____ INTi pin, and input each signal to each corresponding port. ___ As for software, check the ports' input levels in the INTi interrupt routine in order to detect which signal (`a', `b', or `c') was input. M37721 Port Port Port a b c INTi Method using timer's event counter mode As for hardware, input interrupt signals to the TAiIN pins or TBiIN pins. As for software, set the timer's operating mode to the event counter mode. Then, set a value "000016" into the timer register and select the valid edge. The timer's interrupt request occurs when an interrupt signal (selected valid edge) is input. 7721 Group User's Manual 17-71 APPENDIX Appendix 9. 7721 Group Q & A Stack, DRAM Q What are there the stack bank select bit (bit 7 at address 5E16) for? A It is supposed that DRAM is used as the stack area. When connecting DRAM, the stack pointer addressing mode or stack operation instruction etc. can be used. It is because all of 64 Kbytes can be used as the stack area when bank FF16 which is assigned to DRAM is set as the stack area. (The internal RAM also functions as the temporary area or the register file which is accessed frequently because the internal RAM can be accessed with no Wait. Accordingly, it is expected that the capacity will lack to be used as the stack area. As for the M37721, DRAM area can be set as the stack area because cheap DRAM can be connected.) Use bank 0 which is assigned to the internal RAM area as the stack area when DRAM is not connected or the internal RAM is sufficient to be used as the stack area. 17-72 7721 Group User's Manual APPENDIX Appendix 9. 7721 Group Q & A DRAM, WIT instruction Q Are there methods to refresh DRAM in the wait mode? 7721 Group User's Manual 17-73 APPENDIX Appendix 9. 7721 Group Q & A A In the wait mode, DRAM refresh function does not operate, but the watchdog timer, timer A, and timer B operate. Accordingly, DRAM can be refreshed by using these timers and ports. (1) Method using watchdog timer Return from the wait mode by the watchdog timer interrupt. Control ports P104, P105 by ____ ____ software and perform the CAS-before-RASrefresh. Interval of watchdog timer interrupt f(XIN) f32 selected f512 selected 25 MHz 2.621 ms 41.943 ms 16 MHz 4.096 ms 65.536 ms Example 1: A case in 1024 refresh cycles, every 16.4 ms, f(XIN) = 16 MHz, watchdog timer count source = f32 *DRAM refresh is performed 256 times. This refresh is performed by every watchdog timer interrupt. (See flow chart .) Flow chart Main routine Watchdog timer interrupt routine Watchdog timer frequency "1" select bit (bit 0 at address 6116) Watchdog timer count source: f32 selected Bit 4 of port P10 register "0" (address 1616) Port P104 (CAS): "L" level output Bits 4, 5 of port P10 register "1" (address 1616) Ports P104, P105: "H" level output Bits 4, 5 of port P10 direction "1" register (address 1816) Bit 5 of port P10 register "0" (address 1616) Port P105 (RAS): "L" level output Bit 4 of port P10 register "1" (address 1616) Port P104 (CAS): "H" level output DRAM validity bit "0" (bit 7 at address 6416) DRAMC stopped Bit 5 of port P10 register "1" (address 1616) (RAS): Port P105 (RAS) "H" level output WIT instruction Wait mode 256 times ? Y Wait mode completed ? N N RTI Y Note: By using 1 bit of RAM, judge whether this interrupt is for return from the wait mode or for refresh. Return to main routine (1/2) 17-74 7721 Group User's Manual APPENDIX Appendix 9. 7721 Group Q & A DRAM, WIT instruction A (2) Method using timer A or timer B Return from the wait mode by a timer A ( or timer B) interrupt every definite time. Control ____ ____ ports P104, P105 by software and perform the CAS-before-RAS-refresh. Example 2: A case in 512 refresh cycles, every 64 ms, f(XIN) = 25 MHz, timer A0 used *DRAM refresh is performed 512 times by timer A0 interrupts. This interrupt occurs every 64 ms. (See flow chart .) Flow chart Main routine Timer A0 interrupt routine Bits 4, 5 of port P10 register "1" (address 1616) Bit 4 of port P10 register "0" (address 1616) Port P104 (CAS): "L" level output Bits 4, 5 of port P10 direction "1" register (address 1816) Ports P104, P105: "H" level output Bit 5 of port P10 register "0" (address 1616) Port P105 (RAS): "L" level output DRAM validity bit "0" (bit 7 at address 6416) DRAMC stopped Bit 4 of port P10 register "1" (address 1616) Port P104 (CAS): "H" level output Timer A0 mode "110000002" register (address 5616) f512 counted Bit 5 of port P10 register "1" (address 1616) Port P105 (RAS): "H" level output Timer A0 register 3124 (addresses 4716, 4616) Timer value set: One cycle = 64 ms 512 times ? Y N Interrupt priority level set: Timer A0 interrupt "XXXX00012" Level 1 or more (Interrupt control register (address 7516) enabled) Timer A0 count start "1" Timer A0 count started bit (bit 0 at address 4016) RTI Return to main routine Interrupt enable flag I "0" Interrupt enabled WIT instruction Wait mode Wait mode completed ? N Y Note: By using 1 bit of RAM, judge whether this interrupt is for return from the wait mode or for refresh. (2/2) 7721 Group User's Manual 17-75 APPENDIX Appendix 9. 7721 Group Q & A DRAM Q How is the program execution time affected when using DRAM ? A When the M37721 uses DRAM, the execution time is affected as follows: *CPU stops and DRAM refresh cycle is inserted. *1-bus cycle becomes 3 when accessing DRAM. (1) Refresh method of the M37721's DRAMC is the dispersion refresh and 5 cycles of are necessary for one refresh. The rate occupied by the DRAM refresh cycle during the program execution time is described below. Rate occupied by DRAM refresh cycle during program execution time Rate occupied by DRAM refresh cycle Refresh interval f(XIN) = 25 MHz f(XIN) = 16 MHz 15.625 s (Case of 512 refresh cycles, every 8 ms) 125 s (Case of 512 refresh cycles, every 64 ms) 2.6 % 0.3 % 4.2 % 0.5 % (2) The comparison results of two sample programs' execution times are listed below; one is for the case where SRAM is used and the other is for the case where DRAM is used. Use conditions : Execution program f(XIN) External data bus width Refresh interval Memory used as work area SRAM SRAM DRAM (bank FF16) DRAM (bank FF16) Sample program B (See (2/2)) 16 MHz 16 bits 13 s Execution time 3.4 ms 5.0 ms 3.9 ms 5.2 ms Speed comparison 1.00 1.47 1.15 1.53 Software wait valid area Nothing ROM and RAM Nothing ROM (1/2) 17-76 7721 Group User's Manual APPENDIX Appendix 9. 7721 Group Q & A DRAM A qSample program B SEP CLM .DATA .INDEX LDY LDX ASL SEM .DATA ROL ROL CLM .DATA ROR DEX DEX DEX BNE STA SEM .DATA STA CLM .DATA DEY DEY DEY BNE X 16 8 #69 #69 SOUR, X 8 SOUR+2, X B 16 A LOOP0: LOOP1: LOOP1 A, DEST, Y 8 B, DEST+2, Y 16 LOOP0 V SOUR, DEST : Work areas (2/2) 7721 Group User's Manual 17-77 APPENDIX Appendix 9. 7721 Group Q & A Watchdog timer Q When detecting the software runaway by the watchdog timer, if the same value as the contents of the reset vector address is set to the watchdog timer interrupt vector address, not performing software reset, how does it result in? When branching to the reset branch address within the watchdog timer interrupt routine, how does it result in? A The CPU registers and the SFR are not initialized in the above-mentioned way. Accordingly, the user must initialize all of them by software. Note that the processor interrupt priority level (IPL) retains "7" of the watchdog timer interrupt priority level and is not initialized. Consequently, all interrupt requests cannot be accepted. When rewriting the IPL by software, save once the 16-bit immediate value to the stack area and then restore that 16-bit immediate value to all bits of the processor status register (PS). When a software runaway occurs, we recommend to use software reset in order to initialize the microcomputer. 17-78 7721 Group User's Manual APPENDIX Appendix 10. Differences between 7721 Group and 7720 Group Appendix 10. Differences between 7721 Group and 7720 Group Table 2 Differences between M37721S2BFP and M37720S1AFP M37721S2BFP Item 1024 bytes (Note) Internal RAM size External clock input frequency Instruction execution time (minimum) Real-time Bit configuration of output real-time output channel Port latch state after using real-time output 25 MHz (maximum) 160 ns 4 bits ! 2 channels, or M37720S1AFP 512 bytes 16 MHz (maximum) 250 ns 4 bits ! 2 channels 6 bits ! 1channel and 2 bits ! 1channel Retains the value before using Undefined real-time output Limitation for instruction used when writing Nothing (LDM, STA instructions Exists (LDM, STA instructions can be used.) cannot be used.) to interrupt control register Timing when overrun error flag becomes "0" One of the following: One of the following: *When setting the receive enable *When setting the receive bit to "0" enable bit to "0" *When setting the serial I/O mode *When setting the serial I/O select bits to "0002" mode select bits to "0002" *When reading the receive buffer register ____ Serial I/O Conditions for outputting "L" of RTS When all of the following are When all of the following are satisfied: signal in clock synchronous serial I/O satisfied: *Receive enable bit = "1" *Receive enable bit = "1" mode *Reception is stopped. *Reception is stopped. *Dummy data is present in the transmit buffer register 12.5 Mbytes/sec 8 Mbytes/sec DMA shortest transfer rate (At 1-bus cycle transfer) Note: 512 bytes can be selected by software. For the M37721S1BFP, its internal RAM size is 512 bytes. 7721 Group User's Manual 17-79 APPENDIX Appendix 11. Electrical characteristics Appendix 11. Electrical characteristics The electrical characteristics of the M37721S2BFP are described below. For the latest data, inquire of addresses described last ("CONTACT ADDRESSES FOR FURTHER INFORMATION"). Absolute maximum ratings Symbol VCC AVCC VI VI Parameter Power source voltage Analog power source voltage ______ Input voltage RESET, CNVSS, BYTE Input voltage A8/D8-A15/D15, A16/D0-A23/D7, P43-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P97, ____ _____ Conditions Ratings -0.3 to 7 -0.3 to 7 -0.3 to 12 Unit V V V -0.3 to VCC+0.3 V P100-P107, RDY, HOLD, XIN, VREF VO Output voltage A0/MA0-A7/MA7, A8/D8-A15/D15, A16/D0-A23/D7, P43-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P97, P100-P107, ________ __ -0.3 to VCC+0.3 V 1, RESETOUT, XOUT, E, ST0, ____ ____ __ ST1, ALE, BLE, BHE, R/W Pd Topr Tstg Power dissipation Operating temperature Storage temperature Ta = 25 C 300 -20 to 85 -40 to 150 mW C C 17-80 7721 Group User's Manual APPENDIX Appendix 11. Electrical characteristics Recommended operating conditions (VCC = 5 V 10 %, Ta = -20 to 85 C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max. 5.0 4.5 5.5 Power source voltage Vcc V Vcc Analog power source voltage AVcc V 0 Power source voltage Vss V 0 Analog power source voltage AVss V High-level input voltage P43-P47, P50-P57, P60-P67, P70-P77, VIH ____ Vcc V P80-P87, P90-P97, P100-P107, RDY, 0.8 Vcc _____ ______ HOLD, BYTE, CNVss, RESET, XIN, VREF 0.5 Vcc Vcc VIH High-level input voltage A8/D8-A15/D15, A16/D0-A23/D7 V VIL Low-level input voltage P43-P47, P50-P57, P60-P67, P70-P77, ____ P80-P87, P90-P97, P100-P107, RDY, _____ ______ 0 0.2 Vcc V HOLD, BYTE, CNVSS, RESET, XIN, VREF 0 0.16 Vcc VIL Low-level input voltage V A8/D8-A15/D15, A16/D0-A23/D7 IOH (peak) High-level peak output current A0/MA0-A7/MA7, A8/D8-A15/D15, A16/D0-A23/D7, P43-P47, P50-P57, -10 mA P60-P67, P70-P77, P80-P87, ________ P90-P97, P100-P107, 1, RESETOUT, ____ ____ __ ST0, ST1, ALE, BLE, BHE, R/W IOH (avg) High-level average output A0/MA0-A7/MA7, A8/D8-A15/D15, current A16/D0-A23/D7, P43-P47, P50-P57, -5 mA P60-P67, P70-P77, P80-P87, _________ P90-P97, P100-P107, 1, RESETOUT, ____ ____ __ ST0, ST1, ALE, BLE, BHE, R/W IOL (peak) Low-level peak output current A0/MA0-A7/MA7, A8/D8-A15/D15, A16/D0-A23/D7, P43-P47, P50-P57, 10 P60-P67, P70-P77, P80-P87, mA _________ P90-P97, P100-P107, 1, RESETOUT, ____ ____ __ ST0, ST1, ALE, BLE, BHE, R/W IOL (avg) Low-level average A0/MA0-A7/MA7, A8/D8-A15/D15, output current A16/D0-A23/D7, P43-P47, P50-P57, 5 P60-P67, P70-P77, P80-P87, mA _________ P90-P97, P100-P107, 1, RESETOUT, ____ ____ __ ST0, ST1, ALE, BLE, BHE, R/W 25 f(XIN) External clock input frequency MHz Notes 1: Average output current is the average value of a 100 ms interval. ____ 2: ____ sum of IOL(peak) for P8, P9, A0/MA0-A7/MA7, A8/D8-A15/D15, A16/D0-A23/D7, ST0, ST1, ALE, BLE, The __ BHE, and R/W must be 80 mA or less; the ____ of IOH(peak) for P8, P9, A0/MA0-A7/MA7, A8/D8- sum ____ __ A15/D15, A16/D0-A23/D7, ST0, ST1, ALE, BLE, BHE, and R/W must be 80 mA or less; the sum of IOL(peak) for P4, P5, P6, P7, P10, and 1 must be 80 mA or less; the sum of IOH(peak) for P4, P5, P6, P7, P10, and 1 must be 80 mA or less. 7721 Group User's Manual 17-81 APPENDIX Appendix 11. Electrical characteristics Electrical characteristics (VCC = 5 V, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz, unless otherwise noted) Limits Parameter Symbol Test conditions Min. Typ. Max. Unit VOH High-level output A0/MA0-A7/MA7, A8/D8-A15/D15, A16/D0-A23/D7, P43- voltage P47, P50-P57, P60-P67, P70-P77, _________ V 3 IOH = -10 mA P80-P87, P90-P97,____ __ 1, RESETOUT, ST0, P100-P107, ____ ST1, ALE, BLE, BHE, R/W VOH High-level output A0/MA0-A7/MA7, A8/D8-A15/D15, A16/D0-A23/D7, MA8, ____ ____ ____ ____ __ V 4.7 IOH = -400 A voltage MA9, RAS, CAS, 1, ST0, ST1, BLE, BHE, R/W VOH High-level output ALE 3.1 IOH = -10 mA V voltage 4.8 IOH = -400 A __ VOH 3.4 IOH = -10 mA High-level output E V voltage IOH = -400 A 4.8 VOL Low-level output A0/MA0-A7/MA7, A8/D8-A15/D15, voltage A16/D0-A23/D7, P43-P47, P50-P57, P60-P67, V 2 IOL = 10 mA P70-P77, P80-P87, P90-P97, P100-P107, 1, ________ ____ ____ __ RESETOUT, ST0, ST1, ALE, BLE, BHE, R/W VOL Low-level output A0/MA0-A7/MA7, A8/D8-A15/D15,____ ____ V 0.45 voltage A16/D0-A23/D7, MA8, MA9, RAS, CAS, 1, ST0, ST1, IOL = 2 mA ____ ____ __ BLE, BHE, R/W VOL 1.9 Low-level output ALE IOL = 10 mA V 0.43 voltage IOL = 2 mA __ VOL 1.6 IOL = 10 mA Low-level output E V 0.4 voltage IOL = 2 mA _____ ____ ____ ____ VT+-VT- Hysteresis HOLD, ____ ____ _____ RDY, TA2IN-TA4IN, TB0IN, TB1IN, INT0-INT2, V 1 ADTRG, CTS0,________ ___CLK1, CTS1, CLK0, 0.4 ________ DMAREQ0-DMAREQ3, TC ______ VT+-VT- Hysteresis V 0.5 RESET 0.2 V VT+-VT- Hysteresis 0.3 XIN 0.1 IIH High-level input A8/D8-A15/D15, A16/D0-A23/D7, P43-P47, P50-P57, P60-P67, P70-P77, P80-P87, current ____ _____ 5 A VI = 5 V P90-P97, P100-P107, RDY, HOLD, BYTE, CNVss, ______ XIN, RESET IIL A8/D8-A15/D15, A16/D0-A23/D7, P43-P47, P50-P57, Low-level input -5 A P60-P67, P70-P77, P80-P87, P90-P97, P100-P107, VI = 0 V current ____ _____ ______ RDY, HOLD, BYTE, CNVss, XIN, RESET VRAM V RAM hold voltage 2 When clock is stopped. Icc Power source current f(XIN) = 25 MHz (Square 54 mA 27 waveform) Ta = 25 C (when clock is stopped) Ta = 85 C (when clock is stopped) 1 20 A A A-D CONVERTER CHARACTERISTICS (VCC = 5 V, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz, unless otherwise noted) Limits Unit Symbol Test conditions Parameter Min. Typ. Max. Resolution -- VREF = VCC 8 Bits VREF = VCC -- Absolute accuracy 3 LSB 2 VREF = VCC RLADDER Ladder resistance 10 k 9.12 tCONV Conversion time s 2 VREF Reference voltage VCC V 0 VIA Analog input voltage VREF V 17-82 7721 Group User's Manual APPENDIX Appendix 11. Electrical characteristics Internal peripheral devices' timing requirements (VCC = 5 V 10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz, unless otherwise noted) Note: The limits depend on f(XIN). Table 3 lists calculation formulas for the limits. Timer A input (Count input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) Parameter TAjIN input cycle time TAjIN input high-level pulse width TAjIN input low-level pulse width Limits Min. Max. 80 40 40 Unit ns ns ns Timer A input (Gating input in timer mode) Symbol tc(TA) tw(TAH) tw(TAL) Parameter TAjIN input cycle time TAjIN input high-level pulse width TAjIN input low-level pulse width Limits Min. Max. (Note) 320 (Note) 160 (Note) 160 Unit ns ns ns Timer A input (External trigger input in one-shot pulse mode) Symbol tc(TA) tw(TAH) tw(TAL) Parameter TAjIN input cycle time TAjIN input high-level pulse width TAjIN input low-level pulse width Limits Min. Max. (Note) 160 80 80 Unit ns ns ns Timer A input (External trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) Parameter TAjIN input high-level pulse width TAjIN input low-level pulse width Limits Min. Max. 80 80 Unit ns ns Timer A input (Up-down input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAjOUT TAjOUT TAjOUT TAjOUT TAjOUT input input input input input Parameter cycle time high-level pulse width low-level pulse width setup time hold time Limits Min. Max. 2000 1000 1000 400 400 Unit ns ns ns ns ns Timer A input (Two-phase pulse input in event counter mode) Symbol tc(TA) TAjIN input cycle time tsu(TAjIN-TAjOUT) TAjIN input setup time tsu(TAjOUT-TAjIN) TAjOUT input setup time Parameter Limits Min. Max. 800 200 200 Unit ns ns ns 7721 Group User's Manual 17-83 APPENDIX Appendix 11. Electrical characteristics Internal peripheral devices *Count input in event counter mode *Gating input in timer mode *External trigger input in one-shot pulse mode *External trigger input in pulse width modulation mode tc(TA) tw(TAH) TAjIN input tw(TAL) *Up-down input and count input in event counter mode tc(UP) tw(UPH) TAjOUT input (Up-down input) tw(UPL) TAjOUT input (Up-down input) TAjIN input (When counted at falling edge) th(TIN-UP) tsu(UP-TIN) TAjIN input (When counted at rising edge) *Two-phase pulse input in event counter mode tc(TA) TAjIN input tsu(TAjIN-TAjOUT) TAjOUT input tsu(TAjOUT-TAjIN) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) Test conditions *Vcc = 5 V 10 % *Input timing voltage : VIL = 1.0 V, VIH = 4.0 V 17-84 7721 Group User's Manual APPENDIX Appendix 11. Electrical characteristics Timer B input (Count input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) TBjIN TBjIN TBjIN TBjIN TBjIN TBjIN input input input input input input Parameter cycle time (one edge count) high-level pulse width (one edge count) low-level pulse width (one edge count) cycle time (both edges count) high-level pulse width (both edges count) low-level pulse width (both edges count) Limits Min. Max. 80 40 40 160 80 80 Unit ns ns ns ns ns ns Timer B input (Pulse period measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) Parameter TBjIN input cycle time TBjIN input high-level pulse width TBjIN input low-level pulse width Limits Min. Max. (Note) 320 (Note) 160 (Note) 160 Unit ns ns ns Timer B input (Pulse width measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) Parameter TBjIN input cycle time TBjIN input high-level pulse width TBjIN input low-level pulse width Limits Min. Max. (Note) 320 (Note) 160 (Note) 160 Unit ns ns ns A-D trigger input Symbol tc(AD) tw(ADL) Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi CLKi CLKi TxDi TxDi RxDi RxDi Parameter input cycle time input high-level pulse width input low-level pulse width output delay time hold time input setup time input hold time ____ Parameter ADTRG input cycle time (trigger enabled minimum) ADTRG input low-level pulse width Limits Min. Max. 1000 125 Unit ns ns Limits Min. Max. 200 100 100 80 0 20 90 Unit ns ns ns ns ns ns ns External interrupt INTi input Symbol ____ Parameter ____ tw(INH) tw(INL) INTi input high-level pulse width INTi input low-level pulse width Limits Min. Max. 250 250 Unit ns ns 7721 Group User's Manual 17-85 APPENDIX Appendix 11. Electrical characteristics Internal peripheral devices tc(TB) tw(TBH) TBjIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi input tw(CKL) th(C-Q) TxDi output td(C-Q) tsu(D-C) RxDi input th(C-D) tw(INL) INTi input tw(INH) Test conditions *Vcc = 5 V 10 % *Input timing voltage : VIL = 1.0 V, VIH = 4.0 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V 17-86 7721 Group User's Manual APPENDIX Appendix 11. Electrical characteristics Ready and Hold Timing requirements (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz, unless otherwise noted) Limits Parameter Symbol Min. Max. ____ tsu(RDY-1) RDY input setup time 55 _____ tsu(HOLD-1) ____ input setup time HOLD 55 th(1-RDY) RDY input hold time 0 _____ th(1-HOLD) HOLD input hold time 0 Unit ns ns ns ns Switching characteristics (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz, unless otherwise noted) Limits Parameter Unit Symbol Min. Max. ns td(1-STi) ST0, ST1 output delay time 40 Note: Figure 13 shows the test circuit. 7721 Group User's Manual 17-87 APPENDIX Appendix 11. Electrical characteristics *Ready function With no Wait 1 E output RDY input tsu(RDY1) th( 1-RDY) With Wait 1 E output RDY input tsu(RDY1) th( 1-RDY) Test conditions *Vcc = 5 V 10 % *Input timing voltage : VIL = 1.0 V, VIH = 4.0 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Hold function 1 tsu(HOLDHOLD input 1) th( 1-HOLD) td( STi output 1-STi) td( 1-STi) Test conditions *Vcc = 5 V 10 % *Input timing voltage : VIL = 1.0 V, VIH = 4.0 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V 17-88 7721 Group User's Manual APPENDIX Appendix 11. Electrical characteristics Microprocessor mode : with no Wait Note: The limits depend on f(XIN). Table 4 lists calculation formulas for the limits. Timing requirements (VCC = 5 V 10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz, unless otherwise noted) Limits Symbol Unit Parameter Min. Max. ns tc External clock input cycle time 40 ns tw(H) External clock input high-level pulse width 15 ns tw(L) External clock input low-level pulse width 15 tr External clock input rising time 8 ns tf External clock input falling time 8 ns ns tsu(PiD-E) Port Pi input setup time (i = 4-10) 60 ns th(E-PiD) Port Pi input hold time (i = 4-10) 0 Switching characteristics (VCC = 5 V 10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz, unless otherwise noted) Limits Symbol Parameter Min. Max. td(E-PiQ) Port Pi data output delay time (i = 4-10) 80 td(AL-E) (Note) Address low-order output delay time 15 td(E-DHQ) Data high-order output delay time (BYTE = "L") 35 tpxz(E-DHZ) Data high-order floating start delay time (BYTE = "L") 0 td(AM-E) (Note) Address middle-order output delay time 15 td(AM-ALE) Address middle-order output delay time (Note) 5 td(E-DLQ) Data low-order output delay time 35 tpxz(E-DLZ) Data low-order floating start delay time 0 td(AH-E) Address high-order output delay time (Note) 15 td(AH-ALE) Address high-order output delay time (Note) 5 td(ALE-E) ALE output delay time 4 tw(ALE) ALE pulse width (Note) 22 ____ td(BHE-E) (Note) BHE output delay time 20 ____ td(BLE-E) (Note) BLE output delay time 20 __ td(R/W-E) (Note) R/W output delay time 20 td(E-1) 1 output delay time 18 0 th(E-AL) (Note) Address low-order hold time 18 th(ALE-AM) Address middle-order hold time (BYTE = "L") 9 th(E-DHQ) Data high-order hold time (BYTE = "L") (Note) 18 tpzx(E-DHZ) Data high-order floating release delay time (BYTE = "L") (Note) 20 th(E-AM) Address middle-order hold time (BYTE = "H") (Note) 18 th(ALE-AH) Address high-order hold time 9 th(E-DLQ) (Note) Data low-order hold time 18 tpzx(E-DLZ) Data low-order floating release delay time (Note) 20 ____ th(E-BHE) (Note) BHE hold time 18 ____ th(E-BLE) (Note) BLE hold time 18 __ th(E-R/W) (Note) R/W hold time 18 tw(EL) (Note) E pulse width 55 tsu(A-DL) Data low-order setup time after address stabilization (Note) 50 tsu(ALE-DL) Data low-order setup time after rising of ALE (Note) 55 tsu(A-DH) Data high-order setup time after address stabilization (Note) 50 tsu(ALE-DH) Data high-order setup time after rising of ALE (Note) 55 Note: Figure 13 shows the test circuit. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7721 Group User's Manual 17-89 APPENDIX Appendix 11. Electrical characteristics Microprocessor mode : with no Wait f(XIN) tr tf tc 1 td(EE Address output A0-A7 Address output A8-A15 (BYTE = "H") Address/Data output A8/D8-A15/D15 (BYTE = "L") Data input D0-D15 (BYTE = "L") Address/Data output A16/D0-A23/D7 Data input D0-D7 ALE output 1) td(E- 1) tw(EL) td(AL-E) Address td(AM-E) td(AM-E) Address th(E-AL) th(E-AM) Address td(E-DHQ) Data th(ALE-AM) td(E-DLQ) Address th(E-DHQ) td(AM-ALE) td(AH-E) th(E-DLQ) Data td(AH-ALE) tw(ALE) td(BHE-E) th(ALE-AH) td(ALE-E) th(E-BHE) th(E-BLE) BHE output td(BLE-E) BLE output td(R/W-E) R/W output th(E-R/W) td(E-PiQ) Port Pi output (i = 4-10) Test conditions (port Pi) *Vcc = 5 V 10 % *Input timing voltage : VIL = 1.0 V, VIH = 4.0 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V Test conditions (except port Pi) *Vcc = 5 V 10 % *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Data input : VIL = 0.8 V, VIH = 2.5 V 17-90 7721 Group User's Manual APPENDIX Appendix 11. Electrical characteristics Microprocessor mode : with no Wait f(XIN) tr tf tc 1 td(EE 1) td(E- 1) tw(EL) td(AL-E) th(E-AL) Address td(AM-E) td(AM-E) Address Address output A0-A7 Address output A8-A15 (BYTE = "H") Address/Data output A8/D8-A15/D15 (BYTE = "L") Data input D8-D15 (BYTE = "L") Address/Data output A16/D0-A23/D7 th(E-AM) Address tpxz(E-DHZ) th(ALE-AM) tsu(A-DH) tsu(DH-E) tsu(ALE-DH) Data tpxz(E-DLZ) Address tpzx(E-DHZ) td(AM-ALE) th(E-DH) tpzx(E-DLZ) td(AH-E) td(AH-ALE) tsu(A-DL) tsu(ALE-DL) tw(ALE) th(ALE-AH) tsu(DL-E) Data Data input D0-D7 ALE output th(E-DL) td(ALE-E) th(E-BHE) th(E-BLE) th(E-R/W) tsu(PiD-E) td(E-PiQ) td(BHE-E) BHE output td(BLE-E) BLE output td(R/W-E) R/W output Port Pi input (i = 4-10) Test conditions (port Pi) *Vcc = 5 V 10 % *Input timing voltage : VIL = 1.0 V, VIH = 4.0 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V Test conditions (except port Pi) *Vcc = 5 V 10 % *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Data input : VIL = 0.8 V, VIH = 2.5 V 7721 Group User's Manual 17-91 APPENDIX Appendix 11. Electrical characteristics Microprocessor mode : with Wait Note: The limits depend on f(XIN). Table 4 lists calculation formulas for the limits. Timing requirements (VCC = 5 V 10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz, unless otherwise noted) Limits Symbol Unit Parameter Min. Max. ns tc External clock input cycle time 40 ns tw(H) External clock input high-level pulse width 15 ns tw(L) External clock input low-level pulse width 15 tr External clock input rising time 8 ns tf External clock input falling time 8 ns ns tsu(PiD-E) Port Pi input setup time (i = 4-10) 60 ns th(E-PiD) Port Pi input hold time (i = 4-10) 0 Switching characteristics (VCC = 5 V 10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz, unless otherwise noted) Limits Symbol Parameter Min. Max. td(E-PiQ) Port Pi data output delay time 80 td(AL-E) (Note) Address low-order output delay time 15 td(E-DHQ) Data high-order output delay time (BYTE = "L") 35 tpxz(E-DHZ) Data high-order floating start delay time (BYTE = "L") 0 td(AM-E) (Note) Address middle-order output delay time 15 td(AM-ALE) Address middle-order output delay time (Note) 5 td(E-DLQ) Data low-order output delay time 35 tpxz(E-DLZ) Data low-order floating start delay time 0 td(AH-E) (Note) Address high-order output delay time 15 td(AH-ALE) Address high-order output delay time (Note) 5 td(ALE-E) ALE output delay time 4 tw(ALE) (Note) ALE pulse width 22 ____ td(BHE-E) (Note) BHE output delay time 20 ____ td(BLE-E) (Note) BLE output delay time 20 __ td(R/W-E) (Note) R/W output delay time 20 td(E-1) 1 output delay time 18 0 th(E-AL) (Note) Address low-order hold time 18 th(ALE-AM) Address middle-order hold time (BYTE = "L") 9 th(E-DHQ) (Note) Data high-order hold time (BYTE = "L") 18 tpzx(E-DHZ) Data high-order floating release delay time (BYTE = "L") (Note) 20 th(E-AM) (Note) Address middle-order hold time (BYTE = "H") 18 th(ALE-AH) Address high-order hold time 9 th(E-DLQ) (Note) Data low-order hold time 18 tpzx(E-DLZ) Data low-order floating release delay time (Note) 20 ____ th(E-BHE) (Note) BHE hold time 18 ____ th(E-BLE) (Note) BLE hold time 18 __ th(E-R/W) (Note) R/W hold time 18 __ tw(EL) (Note) 135 E pulse width tsu(A-DL) (Note) Data low-order setup time after address stabilization 130 tsu(ALE-DL) Data low-order setup time after rising of ALE (Note) 135 tsu(A-DH) (Note) Data high-order setup time after address stabilization 130 tsu(ALE-DH) Data high-order setup time after rising of ALE (Note) 135 Note: Figure 13 shows the test circuit. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 17-92 7721 Group User's Manual APPENDIX Appendix 11. Electrical characteristics Microprocessor mode : with Wait f(XIN) tr tf tc 1 td(EE 1) td(Etd(AL-E) 1) tw(EL) th(E-AL) Address td(AM-E) Address td(AM-E) Address Address output A0-A7 Address output A8-A15 (BYTE = "H") Address/Data output A8/D8-A15/D15 (BYTE = "L") Data input D0-D15 (BYTE = "L") Address/Data output A16/D0-A23/D7 Data input D0-D7 ALE output th(E-AM) td(E-DHQ) Data th(E-DHQ) td(AM-ALE) td(AH-E) th(ALE-AM) td(E-DLQ) th(E-DLQ) Data Address td(AH-ALE) tw(ALE) td(BHE-E) th(ALE-AH) td(ALE-E) th(E-BHE) th(E-BLE) BHE output td(BLE-E) BLE output td(R/W-E) R/W output th(E-R/W) td(E-PiQ) Port Pi output (i = 4-10) Test conditions (port Pi) *Vcc = 5 V 10 % *Input timing voltage : VIL = 1.0 V, VIH = 4.0 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V Test conditions (except port Pi) *Vcc = 5 V 10 % *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Data input : VIL = 0.8 V, VIH = 2.5 V 7721 Group User's Manual 17-93 APPENDIX Appendix 11. Electrical characteristics Microprocessor mode : with Wait f(XIN) 1 tr tf t c td(EE 1) td(Etd(AL-E) 1) tw(EL) th(E-AL) Address td(AM-E) Address td(AM-E) Address Address output A0-A7 Address output A8-A15 (BYTE = "H") Address/Data output A8/D8-A15/D15 (BYTE = "L") Data input D8-D15 (BYTE = "L") Address/Data output A16/D0-A23/D7 th(E-AM) tpxz(E-DHZ) th(ALE-AM) tsu(A-DH) tsu(ALE-DH) tpxz(E-DLZ) Address tpzx(E-DHZ) td(AM-ALE) tsu(DH-E) Data th(E-DH) tpzx(E-DLZ) td(AH-E) td(AH-ALE) th(ALE-AH) tsu(A-DL) tsu(ALE-DL) tsu(DL-E) Data Data input D0-D7 th(E-DL) tw(ALE) ALE output td(ALE-E) th(E-BHE) th(E-BLE) th(E-R/W) tsu(PiD-E) td(E-PiQ) td(BHE-E) BHE output td(BLE-E) BLE output td(R/W-E) R/W output Port Pi input (i = 4-10) Test conditions (port Pi) *Vcc = 5 V 10 % *Input timing voltage : VIL = 1.0 V, VIH = 4.0 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V Test conditions (except port Pi) *Vcc = 5 V 10 % *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Data input : VIL = 0.8 V, VIH = 2.5 V 17-94 7721 Group User's Manual APPENDIX Appendix 11. Electrical characteristics DRAM control switching characteristics (VCC = 5 V 10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz, unless otherwise noted) Note: The limits depend on f(XIN). Table 5 lists calculation formulas for the limits. Read Symbol ____ Parameter (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) tw(RASL) RAS low-level pulse width ____ tw(CASL) CAS low-level pulse width ____ tw(RASH) CAS high-level pulse width ____ ____ td(RAS-CAS) RAS-CAS delay time ____ td(RA-RAS) Row address delay time before RAS ____ th(RAS-RA) Row address hold time after RAS ____ td(CA-CAS) Column address delay time before CAS ____ th(CAS-CA) Column address hold time after CAS __ ____ td(R/W-RAS) R/W delay time before RAS __ ____ th(CAS-R/W) R/W hold time after CAS __ td(E-CA) Column address delay time after E's low level ____ __ td(E-RASL) ____ delay time after __ low level RAS E's td(E-CASL) ____ delay time after __ low level CAS E's td(E-RASH) ____ delay time after __ high level RAS E's td(E-CASH) CAS delay time after E's high level Note: Figure 13 shows the test circuit. Write Symbol ____ Limits Min. Max. Unit ns 120 ns 92.5 ns 60 ns 28 ns 5 ns 18 ns 5 ns 100 ns 18 ns 18 65 ns 30 ns 77.5 ns 0 20 ns 20 ns 0 Parameter (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) tw(RASL) RAS low-level pulse width ____ tw(CASL) CAS low-level pulse width ____ tw(RASH) CAS high-level pulse width ____ ____ td(RAS-CAS) RAS-CAS delay time ____ td(RA-RAS) Row address delay time before RAS ____ th(RAS-RA) Row address hold time after RAS ____ td(CA-CAS) Column address delay time before CAS ____ th(CAS-CA) Column address hold time afrer CAS __ ____ td(R/W-RAS) R/W delay time before RAS __ ____ th(CAS-R/W) R/W hold time after CAS ____ __ td(E-RASL) RAS delay time after E's low level ____ __ td(E-CASL) ____ delay time after __ low level CAS E's td(E-RASH) ____ delay time after __ high level RAS E's td(E-CASH) CAS delay time after E's high level Note: Figure 13 shows the test circuit. Refresh state Symbol tw(RASL) RAS low-level pulse width ____ tw(CASL) CAS low-level pulse width ____ ___ td(CAS-RAS) CAS-RAS delay time ____ ____ th(RAS-CAS) CAS hold time after RAS Note: Figure 13 shows the test circuit. ____ Limits Unit Min. Max. ns 120 ns 55 ns 60 ns 60 ns 5 ns 18 ns 10 ns 60 ns 18 ns 18 30 ns 115 ns 80 20 ns 0 20 ns 0 Parameter (Note) (Note) (Note) (Note) Limits Min. Max. 120 55 17.5 17.5 Unit ns ns ns ns 7721 Group User's Manual 17-95 APPENDIX Appendix 11. Electrical characteristics At DRAM control 1 E tw(RASH) RAS output td(R/W-RAS) CAS output At read MA0-MA9 output R/W output td(RA-RAS) td(RAS-CAS) th(RAS-RA) td(E-RASL) td(E-CASL) td(CA-CAS) tw(RASL) td(E-RASH) td(E-CASH) tw(CASL) th(CAS-CA) Column address th(CAS-R/W) Row address td(E-CA) td(RAS-CAS) tw(RASH) th(RAS-RA) RAS output td(R/W-RAS) CAS output At write MA0-MA9 output R/W output td(RA-RAS) td(E-RASL) td(E-CASL) td(CA-CAS) Row address tw(RASL) td(E-RASH) td(E-CASH) tw(CASL) th(CAS-CA) Column address th(CAS-R/W) tw(RASL) RAS output At refreshing CAS output tw(CASL) td(CAS-RAS) th(RAS-CAS) Test conditions *Vcc = 5 V 10 % *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *D0-D15 input : VIL = 0.8 V, VIH = 2.5 V 17-96 7721 Group User's Manual APPENDIX Appendix 11. Electrical characteristics DMAC switching characteristics (VCC = 5 V 10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz, unless otherwise noted) Note: The limits depend on f(XIN). Table 6 lists calculation formulas for the limits. Limits Unit Min. Max. ns 60 ns 80 40 ns 60 ns ns 15 35 ns 0 ns ns 35 ns 0 ns ns 15 ns 4 ns 22 ns 20 ns 20 ns 20 ns 18 ns 9 ns 18 ns 20 ns 18 ns 9 ns 18 ns 20 ns 18 ns 18 ns 18 ns 55 ns 50 ns 50 ns 50 ns 60 ns 80 Symbol tsu(DRQ-1) tw(DRQ) td(1-STi) td(1-DAK) td(AL-E) td(E-DHQ) tpxz(E-DHZ) td(AM-E) td(E-DLQ) tpxz(E-DLZ) td(AH-E) td(ALE-E) tw(ALE) td(BHE-E) td(BLE-E) td(R/W-E) th(E-AL) th(ALE-AM) th(E-DHQ) tpzx(E-DHZ) th(E-AM) th(ALE-AH) th(E-DLQ) tpzx(E-DLZ) th(E-BHE) th(E-BLE) th(E-R/W) tw(EL) td(data) td(1-TC) tw(TC) tsu(TCIN) tw(TCIN) ________ Parameter DMAREQi input setup time ________ DMAREQi input pulse width ST0, ST1 output delay time ________ DMAACKi output delay time Address low-order output delay time Data high-order output delay time (BYTE = "L") Data high-order floating start delay time (BYTE = "L") Address middle-order output delay time Data low-order output delay time Data low-order floating start delay time Address high-order output delay time ALE output delay time ALE pulse width ____ BHE output delay time ____ BLE output delay time __ R/W output delay time Address low-order hold time Address middle-order hold time (BYTE = "L") Data high-order hold time (BYTE = "L") Data high-order floating release delay time (BYTE = "L") Address middle-order hold time (BYTE = "H") Address high-order hold time Data low-order hold time Data low-order floating release delay time ____ BHE hold time ____ BLE hold time __ R/W hold time __ E pulse width Copy delay time ___ TC output delay time ___ TC output pulse width ___ TC input setup time ___ TC input pulse width Note: Figures 13 and 14 show the test circuits. (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) 7721 Group User's Manual 17-97 APPENDIX Appendix 11. Electrical characteristics At DMA transfer *Burst transfer timing (External source DMAREQi) 1 E tsu(DRQ- 1) tw(EL) DMAREQi tw(DRQ) ST0 td( DMAACKi 1-STi) td( td(AL-E) 1-DAK) th(E-AL) Address Address Address A0-A7 output A8/D8-A15/D15 output (BYTE = "L") A8/D8-A15/D15 output (BYTE = "H") A16/D0-A23/D7 output Address Address td(E-DHQ) Address Data Address Address td(AM-E) Address Address th(E-AM) Address Address Data Address th(ALE-AM) Address Address td(AH-E) Address Data Address Address Address td(E-DLQ) Data Address tw(ALE) ALE output td(ALE-E) th(ALE-AH) th(E-BHE) th(E-BLE) th(E-R/W) td(BHE-E) BHE output td(BLE-E) BLE output td(R/W-E) R/W output Test conditions *Vcc = 5 V 10 % *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *D0-D15 input : VIL = 0.8 V, VIH = 2.5 V *DMAREQi input : VIL = 0.8 V, VIH = 2.5 V 17-98 7721 Group User's Manual APPENDIX Appendix 11. Electrical characteristics At DMA transfer *Cycle-steal transfer timing (External source DMAREQi) 1 E tsu(DRQ- 1) tw(EL) DMAREQi tw(DRQ) ST0 td( td( td(AL-E) td( 1-STi) td( DMAACKi 1-STi) 1-DAK) 1-DAK) th(E-AL) Address Address Address A0-A7 output A8/D8-A15/D15 output (BYTE = "L") A8/D8-A15/D15 output (BYTE = "H") A16/D0-A23/D7 output Address Address Address Data Address Address Address Address td(AM-E) Address Address Data Address Address Address th(E-AM) Address Address Address td(AH-E) Address Address tw(ALE) ALE output td(ALE-E) th(E-BHE) th(E-BLE) td(BHE-E) BHE output td(BLE-E) BLE output td(R/W-E) R/W output Test conditions *Vcc = 5 V 10 % *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *D0-D15 input : VIL = 0.8 V, VIH = 2.5 V *DMAREQi input : VIL = 0.8 V, VIH = 2.5 V 7721 Group User's Manual 17-99 APPENDIX Appendix 11. Electrical characteristics At DMA transfer *1-bus transfer timing 1 E td( DMAACKi 1-DAK) td( 1-DAK) td( 1-DAK) td( 1-DAK) td(AL-E) A0-A7 output A8/D8-A15/D15 output (BYTE = "L") D0-D15 input Address th(E-AL) Address td(AL-E) Address th(E-AL) tpxz(E-DHZ) tpzx(E-DHZ) Address Data tsu(DH-E) th(E-DH) td(data) td(data) tpxz(E-DLZ) tpzx(E-DLZ) tsu(DL-E) th(E-DL) A16/D0-A23/D7 output D0-D7 output Address Data Address tw(ALE) ALE output td(ALE-E) td(BHE-E) th(E-BHE) th(E-BLE) th(E-R/W) tw(ALE) td(ALE-E) td(BHE-E) td(BLE-E) td(R/W-E) th(E-BHE) th(E-BLE) th(E-R/W) BHE output td(BLE-E) BLE output td(R/W-E) R/W output Test conditions *Vcc = 5 V 10 % *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *D0-D15 input : VIL = 0.8 V, VIH = 2.5 V 17-100 7721 Group User's Manual APPENDIX Appendix 11. Electrical characteristics At DMA transfer *Transfer complete timing 1 E td( TC 1-TC) tw(TC) ST0 td( td( 1-STi) 1-DAK) DMAACKi th(E-AL) A0-A7 output A8/D8-A15/D15 output (BYTE = "L") A8/D8-A15/D15 output (BYTE = "H") A16/D0-A23/D7 output ALE output Address td(AL-E) Address Address Address Address th(E-DHQ) Address Data Address Address Address Data th(E-AM) Address Address Address Address td(AM-E) Address th(E-DLQ) Data Address Address td(AH-E) Data th(E-BHE) BHE output td(BHE-E) td(BLE-E) td(R/W-E) th(E-BLE) BLE output th(E-R/W) R/W output Test conditions *Vcc = 5 V 10 % *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *D0-D15 input : VIL = 0.8 V, VIH = 2.5 V 7721 Group User's Manual 17-101 APPENDIX Appendix 11. Electrical characteristics When DMA transfer is forcedly completed by TC input *TC input timing 1 E tsu(TCIN) TC input tw(TCIN) ST0 td( td( 1-STi) 1-DAK) DMAACKi td(AL-E) A0-A7 output A8/D8-A15/D15 output (BYTE = "L") A8/D8-A15/D15 output (BYTE = "H") A16/D0-A23/D7 output ALE output Destination address th(E-AL) Source address Source Destination address address Destination address Address td(E-DHQ) Data Address Data td(AM-E) Destination address th(E-AM) Source address Source Destination address address th(ALE-AM) Destination address Address td(AH-E) Data td(E-DLQ) Data Address tw(ALE) td(R/W-E) R/W output td(ALE-E) th(ALE-AH) th(E-R/W) Test conditions *Vcc = 5 V 10 % *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *D0-D15 input : VIL = 0.8 V, VIH = 2.5 V *TC input : VIL = 0.8 V, VIH = 2.5 V 17-102 7721 Group User's Manual APPENDIX Appendix 11. Electrical characteristics Table 3 Calculation formulas for internal peripheral devices' input/output timing depending on f(XIN) (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C) Timer A input (Gating input in timer mode) Symbol Calculation formula Unit 9 tc(TA) ns 8 ! 10 f(XIN) tw(TAH) tw(TAL) 4 ! 10 9 f(XIN) 4 ! 10 9 f(XIN) ns ns Timer A input (External trigger input in one-shot pulse mode) Symbol tc(TA) Calculation formula 4 ! 10 9 f(XIN) Unit ns Timer B input (Pulse period measurement mode) Calculation formula Symbol Unit 9 tc(TB) ns 8 ! 10 f(XIN) tw(TBH) tw(TBL) 4 ! 10 9 f(XIN) 4 ! 10 9 f(XIN) ns ns Timer B input (Pulse width measurement mode) Symbol Unit Calculation formula 9 tc(TB) ns 8 ! 10 f(XIN) tw(TBH) ns 4 ! 10 9 f(XIN) tw(TBL) 4 ! 10 9 f(XIN) ns 7721 Group User's Manual 17-103 APPENDIX Appendix 11. Electrical characteristics Table 4 Calculation formulas for bus timing depending on f(XIN) (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C) Symbol td(AL-E) td(AM-E) td(AH-E) td(AM-ALE) td(AH-ALE) tw(ALE) td(BLE-E) td(BHE-E) td(R/W-E) th(E-AL) th(E-AM) th(E-DLQ) th(E-DHQ) tpzx(E-DLZ) tpzx(E-DHZ) th(E-BLE) th(E-BHE) th(E-R/W) tw(EL) Calculation formula Unit 1 ! 10 9 - 25 f(XIN) 1 ! 10 9 - 35 f(XIN) 1 ! 10 9 - 18 f(XIN) 1 ! 10 9 - 20 f(XIN) 1 ! 10 9 - 22 f(XIN) 1 ! 10 9 - 22 f(XIN) 1 ! 10 9 - 20 f(XIN) 1 ! 10 9 - 22 f(XIN) 2 ! 10 9 - 25 f(XIN) 4 ! 10 9 - 25 f(XIN) 3 ! 10 9 - 70 f(XIN) 5 ! 10 9 - 70 f(XIN) 3 ! 10 9 - 65 f(XIN) 5 ! 10 9 - 65 f(XIN) ns ns ns ns ns ns ns ns ns ns ns ns ns ns Wait bit = "1" Wait bit = "0" tsu(A-DL) tsu(A-DH) Wait bit = "1" Wait bit = "0" tsu(ALE-DL) Wait bit = "1" tsu(ALE-DH) Wait bit = "0" 17-104 7721 Group User's Manual APPENDIX Appendix 11. Electrical characteristics Table 5 Calculation formulas for DRAM control bus timing depending of f(XIN) (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C) Read Symbol tw(RASL) tw(CASL) tw(RASH) td(RAS-CAS) td(RA-RAS) th(RAS-RA) Calculation formula 4 ! 10 f(XIN) 9 Unit ns ns ns ns ns ns Symbol th(CAS-CA) td(R/W-RAS) th(CAS-R/W) td(E-CA) td(E-CASL) Calculation formula 4 ! 10 f(XIN) 9 Unit ns ns ns ns ns - 40 - 60 - 22 3 ! 10 9 - 27.5 f(XIN) 2 ! 10 9 - 20 f(XIN) 1 ! 10 9 - 12 f(XIN) 1 ! 10 9 - 35 f(XIN) 1 ! 10 9 - 22 f(XIN) 1 ! 10 9 f(XIN) 1 ! 10 9 - 22 f(XIN) 1 ! 10 9 + 25 f(XIN) 1 ! 10 9 + 37.5 f(XIN) Write Symbol tw(RASL) tw(CASL) tw(RASH) td(RAS-CAS) td(RA-RAS) th(RAS-RA) Calculation formula 4 ! 10 f(XIN) 9 Unit ns ns ns ns ns ns Symbol td(CA-CAS) th(CAS-CA) td(R/W-RAS) th(CAS-R/W) td(E-CASL) Calculation formula 1 ! 10 f(XIN) 9 Unit ns ns ns ns ns - 40 - 25 - 30 - 60 2 ! 10 9 f(XIN) 3 ! 10 9 f(XIN) 2 ! 10 9 - 20 f(XIN) 2 ! 10 9 - 20 f(XIN) 1 ! 10 9 - 35 f(XIN) 1 ! 10 9 - 22 f(XIN) 1 ! 10 9 - 22 f(XIN) 1 ! 10 9 - 22 f(XIN) 2 ! 10 9 f(XIN) + 35(0) V V The value within ( ) is for the minimum value. Refresh Symbol tw(RASL) tw(CASL) Calculation formula 4 ! 10 f(XIN) 9 Unit ns ns Symbol td(CAS-RAS) th(RAS-CAS) Calculation formula 1 ! 10 9 - 22.5 f(XIN) 1 ! 10 9 - 22.5 f(XIN) Unit ns ns - 40 2 ! 10 9 - 25 f(XIN) 7721 Group User's Manual 17-105 APPENDIX Appendix 11. Electrical characteristics Table 6 Calculation formulas for DMA transfer bus timing depending on f(XIN) (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C) Symbol td(AL-E) td(AM-E) td(AH-E) tw(ALE) td(BLE-E) td(BHE-E) td(R/W-E) th(E-AL) th(E-AM) th(E-DLQ) th(E-DHQ) tpzx(E-DLZ) tpzx(E-DHZ) th(E-BLE) th(E-BHE) th(E-R/W) tw(EL) Transfer source/Transfer destination wait bit = "1" Transfer source/Transfer destination wait bit = "0" tw(TC) Calculation formula Unit 1 ! 10 9 f(XIN) 1 ! 10 9 f(XIN) 1 ! 10 9 f(XIN) 1 ! 10 9 f(XIN) 1 ! 10 9 f(XIN) 1 ! 10 9 f(XIN) 1 ! 10 9 f(XIN) 2 ! 10 9 f(XIN) 4 ! 10 9 f(XIN) 2 ! 10 9 f(XIN) - 25 - 18 - 20 - 22 - 22 - 20 - 22 - 25 - 25 - 30 ns ns ns ns ns ns ns ns ns ns A0/MA0-A7/MA7 A8/D8-A15/D15 A16/D0-A23/D7 P4 P5 P6 P7 P8 P9 P10 E 1 100 pF 3 k TC 100 pF Fig. 13 Test circuit for each pin ___ Fig. 14 ___ circuit for TC output delay time and Test TC output pulse width 17-106 7721 Group User's Manual APPENDIX Appendix 12. Standard characteristics Appendix 12. Standard characteristics Standard characteristics described below are just examples of the M37721S2BFP's characteristics and are not guaranteed. For each parameter's limits, refer to section "Appendix 11. Electrical characteristics." 1. Programmable I/O port (CMOS output) standard characteristics (1) P-channel IOH-VOH characteristics 30.0 24.0 Ta = 25 C IOH [mA] 18.0 Ta = 85 C 12.0 6.0 0 1.0 2.0 3.0 4.0 5.0 VOH [V] (2) N-channel IOL-VOL characteristics 30.0 24.0 Ta = 25 C IOL [mA] 18.0 Ta = 85 C 12.0 6.0 0 1.0 2.0 3.0 4.0 5.0 VOL [V] 7721 Group User's Manual 17-107 APPENDIX Appendix 12. Standard characteristics 2. Icc-f(XIN) standard characteristics (1) Icc-f(XIN) characteristics on operating and at reset Measurement condition (Vcc = 5.0 V, Ta = 25 C, f(XIN) : square waveform, microprocessor mode) 30 20 Icc [mA] On operating At reset 10 0 0 5 10 15 f(XIN) [MHz] 20 25 30 (2) Wait mode Measurement condition (Vcc = 5.0 V, Ta = 25 C, f(XIN) : square waveform, microprocessor mode) 10 8 Icc [mA] 6 4 2 0 0 5 10 15 f(XIN) [MHz] 20 25 30 17-108 7721 Group User's Manual APPENDIX Appendix 12. Standard characteristics 3. A-D converter standard characteristics The lower lines of the graph indicate the absolute precision errors. These are expressed as the deviation from the ideal value when the output code changes. For example, the change in output code from 0 to 1 should occur at 10 mV, but the measured value is +2 mV. Accordingly, the measured point of change is 10 + 2 = 12 mV. The upper lines of the graph indicate the input voltage width for which the output code is constant. For example, the measured input voltage width for which the output code is 15 is 24 mV, so that the differential non-linear error is 24 - 20 = 4 mV (0.2 LSB). [Measurement conditions] *Vcc = 5 V, VREF = 5.12 V, f(XIN) = 25 MHz, Ta = 25 C, AD = f2 divided by 2 30 20 30 20 10 0 ERROR [mV] 10 0 -10 -20 -30 30 20 0 8 16 24 32 40 48 56 64 STEP No. 72 80 88 96 104 112 120 128 30 20 10 0 [mV] 10 0 -10 -20 -30 128 136 144 152 160 168 176 184 192 200 STEP No. 208 216 224 232 240 248 256 7721 Group User's Manual 1LSB WIDTH [mV] ERROR 1LSB WIDTH [mV] 17-109 APPENDIX Appendix 12. Standard characteristics MEMORANDUM 17-110 7721 Group User's Manual GLOSSARY GLOSSARY This section briefly explains the terms used in this user's manual. The terms defined here apply to this manual only. Term Access Access space Access characteristics Branch Bus control signal Countdown Count source Meaning Means performing read, write, or read and write. In DRAMC, also means performing DRAM refresh. An accessible memory space of up to 16 Mbytes. Means whether accessible or not. Means moving the program's execution point (= address) to another location. _____ __ __ ____ ____ ____ _____ A generic name for ALE, E, R/W, BLE, BHE, RDY, HOLD, HLDA, BYTE, ST0, and ST1 signals. Means decreasing by 1 and counting. A signal that is counted by timers A and B, the UARTi baud rate register (BRGi) and the watchdog timer. That is f2, f16, f64, f512 selected by the count source select bits and others. Means increasing by 1 and counting. Countdown An accessible area for external devices connected. It is up to 16- Internal area Mbyte external area. A generic name for the external address bus and the external data bus. Devices connected externally to the microcomputer. A generic name for a memory, an I/O device and a peripheral IC. An accessible internal area. A generic name for areas of the External area internal RAM and the SFR. A routine that is automatically executed when an interrupt request is accepted. Set the start address of this routine into the interrupt vector table. Countup Access Access Relevant term Countup External area External bus External device Internal area Interrupt routine A state where the countup resultant is greater than the counter Underflow resolution. Countup R e a d - m o d i f y - w r i t e An instruction that reads the memory contents, modifies them and writes back to the same address. Relevant instructions are instruction the ASL, ASR, CLB, DEC, INC, LSR, ROL, ROR, SEB instructions. Overflow Signal required for access A generic name for bus control, address bus, and data bus signals. B u s c o n t r o l to external device signal A state where the oscillation circuit halts and the program execution Wait mode Stop mode is stopped. By executing the STP instruction, the microcomputer enters the stop mode. UART Clock asynchronous serial I/O. When used to designate the name Clock of a functional block, this term also means the serial I/O which synchronous can be switched to the cock synchronous serial I/O. serial I/O A state where the countdown resultant is greater than the counter Overflow resolution. Countdown A state where the oscillation circuit is operating, however, the Stop mode program execution is stopped. By executing the WIT instruction, the microcomputer enters the wait mode. Underflow Wait mode 2 7721 Group User's Manual MITSUBISHI SEMICONDUCTORS USER'S MANUAL 7721 Group Sep. First Edition 1997 Editioned by Committee of editing of Mitsubishi Semiconductor USER'S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. (c)1997 MITSUBISHI ELECTRIC CORPORATION User's Manual 7721 Group (c) 1997 MITSUBISHI ELECTRIC CORPORATION. New publication, effective Sep. 1997. Specifications subject to change without notice. |
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